IEEE P1149.8.1/D0.7, August 2009
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IEEE P1149.8.1™/D0.7
Draft Standard for Boundary-ScanBased Stimulus of Interconnections to
Passive and/or Active Components
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Prepared by the Boundary-Scan Selective Toggle Working Group of the
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IEEE Computer Society Test Technology Standards Committee
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Introduction
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This introduction is not part of IEEE P1149.8.1/D0.7, Draft Standard for Boundary-Scan-Based Stimulus of
Interconnections to Passive and/or Active Components.
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<Select this text and type or paste introduction text>
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Notice to users
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Laws and regulations
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Users of these documents should consult all applicable laws and regulations. Compliance with the
provisions of this standard does not imply compliance to any applicable regulatory requirements.
Implementers of the standard are responsible for observing or referring to the applicable regulatory
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Copyrights
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Updating of IEEE documents
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Errata
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Errata, if any, for this and all other standards can be accessed at the following URL:
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IEEE P1149.8.1/D0.7, August 2009
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Interpretations
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Current interpretations can be accessed at the following URL: http://standards.ieee.org/reading/ieee/interp/
index.html.
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Patents
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Attention is called to the possibility that implementation of this standard may require use of subject matter
covered by patent rights. By publication of this standard, no position is taken with respect to the existence
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or scope of Patents Claims or determining whether any licensing terms or conditions provided in
connection with submission of a Letter of Assurance, if any, or in any licensing agreements are reasonable
or non-discriminatory. Users of this standard are expressly advised that determination of the validity of any
patent rights, and the risk of infringement of such rights, is entirely their own responsibility. Further
information may be obtained from the IEEE Standards Association.
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Participants
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At the time this draft standard was completed, the Boundary-Scan Selective Toggle Working Group had the
following membership:
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Jeffrey Burgess, Chair
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Stephen Sunter, Vice Chair
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Kenneth P. Parker, Editor
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Scott Bowden
Steve Butkovich
Floyd Conner
Adam Cron
Dave Dubberke
Ted Eaton
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The following members of the individual balloting committee voted on this standard. Balloters may have
voted for approval, disapproval, or abstention.
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(to be supplied by IEEE)
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Heiko Ehrenberg
James J. Grealish
Robert Kelly
Tom Langford
Adam W. Ley
Sophocles Metsis
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Thai-Minh Nguyen
David Paul
Dirk Reese
Anthony Suto
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IEEE P1149.8.1/D0.7, August 2009
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CONTENTS
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1. Overview .................................................................................................................................................... 1
1.1 Scope ................................................................................................................................................... 1
1.2 Purpose ................................................................................................................................................ 1
1.3 Context ................................................................................................................................................ 1
1.4 Organization of the standard................................................................................................................ 2
1.5 Background reading............................................................................................................................. 3
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2. Normative references.................................................................................................................................. 4
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3. Definitions .................................................................................................................................................. 4
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4. Technology................................................................................................................................................. 5
4.1 Evolution of printed circuit assembly technology ............................................................................... 5
4.2 Shifts in board testing challenges ........................................................................................................ 6
4.3 Signal pin types ................................................................................................................................... 7
4.3.1 Classification of pins.................................................................................................................... 7
4.3.2 Differential pins ........................................................................................................................... 8
4.4 Defects targeted by the standard........................................................................................................ 11
4.5 Selective Toggle Theory of Operation............................................................................................... 13
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5. Instructions ............................................................................................................................................... 14
5.1 IEEE Std 1149.1 instructions............................................................................................................. 14
5.1.1 Rules .......................................................................................................................................... 14
5.1.2 Description................................................................................................................................. 14
5.2 Instructions for selective toggling and guarding................................................................................ 14
5.3 The TOGGLE_SETUP instruction.................................................................................................... 14
5.3.1 Rules .......................................................................................................................................... 15
5.3.2 Permissions ................................................................................................................................ 15
5.3.3 Description................................................................................................................................. 15
5.4 The SELECTIVE_TOGGLE instruction........................................................................................... 15
5.4.1 Rules .......................................................................................................................................... 15
5.4.2 Permissions ................................................................................................................................ 17
5.4.3 Description................................................................................................................................. 17
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6. Pin implementation specifications............................................................................................................ 20
6.1 Pin classification................................................................................................................................ 20
6.1.1 Rules .......................................................................................................................................... 20
6.1.2 Recommendations...................................................................................................................... 20
6.1.3 Description................................................................................................................................. 20
6.2 Implementation of normal pins.......................................................................................................... 21
6.2.1 Rules .......................................................................................................................................... 21
6.2.2 Description................................................................................................................................. 21
6.3 Implementation of ST-pins ................................................................................................................ 22
6.3.1 Single-ended output pins............................................................................................................ 23
6.3.1.1 Rules................................................................................................................................... 23
6.3.1.2 Recommendations .............................................................................................................. 23
6.3.1.3 Description ......................................................................................................................... 23
6.3.2 Single-ended input pins.............................................................................................................. 26
6.3.2.1 Rules................................................................................................................................... 26
6.3.2.2 Recommendations .............................................................................................................. 26
6.3.2.3 Permissions ........................................................................................................................ 26
6.3.2.4 Description ......................................................................................................................... 27
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6.3.3 Single-ended bidirectional pins.................................................................................................. 28
6.3.3.1 Rules................................................................................................................................... 28
6.3.3.2 Description ......................................................................................................................... 28
6.3.4 Differential output pins .............................................................................................................. 28
6.3.4.1 Rules................................................................................................................................... 29
6.3.4.2 Permissions ........................................................................................................................ 29
6.3.4.3 Description ......................................................................................................................... 29
6.3.5 Differential input pins ................................................................................................................ 30
6.3.5.1 Rules................................................................................................................................... 30
6.3.5.2 Description ......................................................................................................................... 30
6.4 Toggle Behavior for ST-pins ............................................................................................................. 30
6.4.1 Rules .......................................................................................................................................... 31
6.4.2 Description................................................................................................................................. 31
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7. The Toggle Control register ..................................................................................................................... 32
7.1 Rules .................................................................................................................................................. 33
7.2 Permissions........................................................................................................................................ 33
7.3 Recommendations ............................................................................................................................. 33
7.4 Description ........................................................................................................................................ 33
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8. Conformance and documentation requirements ....................................................................................... 34
8.1 Conformance ..................................................................................................................................... 34
8.1.1 Rules .......................................................................................................................................... 34
8.1.2 Description................................................................................................................................. 34
8.2 Documentation................................................................................................................................... 35
8.2.1 Rules .......................................................................................................................................... 35
8.2.2 Description................................................................................................................................. 35
8.3 BSDL package for Selective Toggle description (STD_1149_8_1_2009) ........................................ 35
8.4 BSDL extension structure.................................................................................................................. 35
8.5 BSDL attribute definitions................................................................................................................. 36
8.6 Example BSDL.................................................................................................................................. 36
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Annex A (informative) Unpowered Testing for Open Connections on Printed Circuit Assemblies ............ 37
A.1 Problem Description ......................................................................................................................... 37
A.2 Unpowered Capacitive Opens Detection .......................................................................................... 37
A.3 Replacing Tester AC Stimulus with Boundary-Scan Stimulus......................................................... 41
A.4 Coverage Deficiencies ...................................................................................................................... 42
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IEEE P1149.8.1/D0.7, August 2009
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Draft Standard for Boundary-ScanBased Stimulus of Interconnections to
Passive and/or Active Components
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1. Overview
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1.1 Scope
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This standard specifies extensions to IEEE Std 1149.1 that define the boundary-scan structures and
methods required to facilitate boundary-scan-based stimulus of interconnections to passive and/or active
components. Such networks are not adequately addressed by existing standards, including those networks
that are AC-coupled or differential. The selective AC stimulus generation enabled by this standard, when
combined with non-contact signal sensing, will allow testing of the connections between devices adhering
to this standard and circuit elements such as series components, sockets, connectors, and integrated circuits
that do not implement IEEE Std 1149.1. This standard also specifies Boundary-Scan Description Language
(BSDL) extensions to IEEE Std 1149.1 required to describe and support the new structures and methods.
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1.2 Purpose
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The purpose of this standard is to codify testability circuitry added to an integrated circuit incremental to
the testability provisions specified by IEEE Std 1149.1. This will enable selective AC stimulus generation
that, when combined with non-contact signal sensing, allows testing signal paths between devices adhering
to this standard and passive and/or active components.
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[Editor’s note: We may elect to re-word the purpose (extracted from the PAR) to also include
facilities to test for shorted nodes we once had direct access to. This will follow from amending the
PAR.]
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1.3 Context
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Figure 1 shows a printed circuit assembly containing many types of devices. Of these, some could be
compliant with IEEE Std 1149.1 for the support of testing activities. These devices contain Boundary-Scan
testability circuitry which allows them to participate in manufacturing tests that detect and diagnose faults
such as open solder joints, shorts and missing devices.
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IEEE P1149.8.1/D0.7, August 2009
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The additional testability elements added by this standard to these same integrated circuits (ICs) allow this
interconnect testing, to be conducted between these ICs and passive or active components that do not
support IEEE Std 1149.1, when these testability elements are operated in conjunction with alternative
sensing technologies.
5 Figure 1 —A printed circuit assembly containing a variety of components interconnected by
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printed wiring. Some ICs contain IEEE Std 1149.1 features that support Boundary-Scan
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interconnect testing.
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This standard is built on top of IEEE Std 1149.1 using the same Test Access Port and Boundary-Scan
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architecture. It adds new instructions that cause drivers to emit AC waveforms that are compatible with
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alternative sensing technologies.
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[Editor’s note: We may elect to re-word the context to also mention facilities to test for shorted nodes
we once had direct access to. This will follow from amending the purpose above.]
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There are two audiences addressed by this document. The first is made up of integrated circuit device
designers (device designers) and the second is a more general class of integrated circuit device users
(device users). Device designers will use this standard while creating new devices that adhere to the rules
of this standard. Device users will make use of those features. Device users include board and system
designers, design-for-test consultants and test engineers. In many cases, it is expected that there will be
communication and negotiation between the two groups, as the device users will lobby for investments in
the silicon made by device designers who will balance these requests against various factors (schedule,
cost) and trade those off for enhanced testability and defect coverage.
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1.4 Organization of the standard
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Clause 1, Overview, provides an overview and context for this standard.
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Clause 2, Normative references, provides references necessary to understand this standard.
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Clause 3, Definitions, defines terminology and acronyms used in this standard.
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IEEE P1149.8.1/D0.7, August 2009
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Clause 4, Technology, is a tutorial that outlines the technologies addressed and utilized by this standard.
This clause does not contain rules.
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Clause 5, Instructions, provides rules for instructions used for testing.
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Clause 6, Pin implementation specifications, provides rules for I/O pin implementation.
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Clause 7, The Toggle Control register, provides rules for the design and behavior of a toggle control
register used to control the operation of the SELECTIVE_TOGGLE instruction.
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Clause 8, Conformance and documentation requirements, provides rules for conformance and documentation of devices designed to this standard.
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Annex A, (informative) Unpowered Testing for Open Connections on Printed Circuit Assemblies,
describes a capacitively sensed test technology for testing for open connections between printed circuit
assemblies and device pins.
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1.5 Background reading
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Readers unfamiliar with IEEE Std 1149.1 might find it helpful to study some of the following books and
papers, some of which also discuss unpowered capacitive testing:
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Parker, K. P., The Boundary-Scan Handbook, 3rd Edition, Analog and Digital, Kluwer Academic
Publishers, 2003.
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A description of the design and use of IEEE Std 1149.1, 1149.4, 1149.6 and 1532, written from the point of
view of practicing test engineers.
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Turner, T., Capacitive Leadframe Testing, Proceedings, International Test Conference, pg 925, Washington
DC, October 1996.
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Part of a lecture series (ITC 1996 Lecture Series on Unpowered Opens Testing) that described a taxonomy
of unpowered techniques for detecting open joints between devices and boards.
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Dubberke, D., Grealish, J. J. and Van Dick, B. I., Solving In-Circuit Defect Coverage Holes with a Novel
Boundary Scan Application, Proceedings, International Test Conference, paper 11.2, Santa Clara CA,
October 2008.
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This paper describes the types of board designs that benefit from a marriage of capacitive sensing
technology with Boundary-Scan stimulus and postulates some precursor technology to features
incorporated by this standard.
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Norrgard, D. and Parker, K. P., Augmenting Boundary-Scan Tests for Enhanced Defect Coverage,
Proceedings, International Test Conference, paper 11.3, Santa Clara CA, October 2008.
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A companion to Dubberke (above) that shows experimental results of using Boundary-Scan stimulus
provided by the EXTEST instruction for performing capacitive defect sensing. This paper points out the
shortcomings of EXTEST-based capability which leads to features implemented by this standard.
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Sunter, S. and Parker, K. P., Testing Bridges to Nowhere - Combining Boundary Scan and Capacitive
Sensing, Proceedings, International Test Conference, paper 2.1, Austin TX, November 2009.
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IEEE P1149.8.1/D0.7, August 2009
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This paper describes technology and design options for implementing chip-based AC stimuli for capacitive
sensing. Its intention is to alert the test community about this on coming standard.
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Tee, C. L., Tan, T. H. and Ng, C. C., Augmenting Board Test Coverage with New Intel Powered Opens
Boundary-Scan Instruction, Proceedings, International Test Conference, paper 10.21, Austin TX,
November 2009.
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This paper describes experiments with silicon implementations of precursors to the SELECTIVE_TOGGLE
instruction.
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2. Normative references
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The following referenced documents are indispensable for the application of this document (i.e., they must
be understood and used, so each referenced document is cited in text and its relationship to this document is
explained). For dated references, only the edition cited applies. For undated references, the latest edition of
the referenced document (including any amendments or corrigenda) applies.
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IEEE Std 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture
2)
IEEE Std 1149.6, IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks
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3. Definitions
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For the purposes of this draft standard, the following terms and definitions apply. The Authoritative
Dictionary of IEEE Standards Terms should be referenced for terms not defined in this clause.
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3.1 Balun cell: A cell in the Boundary register used to select the “balanced/unbalanced” (abbreviated as
“balun”) behavior of a differential pin driver. Balanced behavior means a differential driver has both legs
operating in completely complementary fashion as would be their normal system function. Unbalanced
behavior means they are no longer complementary..
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3.2 Bed-of-nails: A test fixture that contains many spring-loaded probes positioned to contact conductive
targets on the surface of a printed circuit assembly. Each probe is mapped via fixture wiring to one or more
tester resources provided in a regular array below the fixture.
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3.3 Defect: An unacceptable deviation from a norm. A defect requires action which may include repairing
the defect or discarding the assembly containing the defect. This justifies investment in tests and diagnostic
procedures aimed at discovering and eliminating defects. Examples of manufacturing defects on printed
circuit assemblies are: missing solder causing open connections, bridging solder causing shorts, missing
components, incorrect components, dead components, components that are misaligned, etc.
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3.4 Device designer: The person(s) responsible for implementing circuitry within an integrated circuit
device, and who make tradeoff decisions for circuit features, performance levels, cost and producibility.
Device designers are charged with making additional tradeoffs in their designs that affect the producibility
of subsequent levels of product hierarchy, such as printed circuit assemblies and systems.
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3.5 Device user: Persons who utilize integrated circuits provided by device designers. These include
printed circuit assembly and system designers, as well as testability consultants and test engineers. Device
users will provide information to inform tradeoff decisions made by device designers.
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IEEE P1149.8.1/D0.7, August 2009
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3.6 Differential pins: A pair of input or output pins that are complementarily dependent. For example, the
(ideal, noise-free) voltage waveforms seen during data passage are mirror images of each other. Contrast
with single-ended pins.
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3.7 Loaded board test: A set of tests performed on printed circuit assemblies that determine if the
printed circuit assembly has been constructed properly and does not contain defects.
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3.8 Normal pins: Device pins defined as those that will not be provisioned with the Selective Toggle
capability. (Contrast with “ST-pins”.)
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3.9 Opens: An “open” is a defect condition which breaks an intended electrical connection. Typically this
may occur when an electrical device on a printed circuit assembly has a missing or broken connection, for
example, a missing ball joint in a ball grid array, a pin with missing solder, or a pin that has been bent or
broken off of its device.
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3.10 Printed circuit assembly: (Also known as PCA.) A printed circuit board that has had circuit
components attached to it such that those components can receive and/or transmit signals among their
connections.
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3.11 Printed circuit board: (Also known as PCB.) A substrate containing embedded wiring and metallic
planar structures. A PCB serves as a mounting substrate for numerous electrical devices, with the
embedded wiring forming interconnections between device pins.
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3.12 Selective Toggle: The name of the principle feature enabled by this standard; the ability to cause some
pins to toggle output drive states while other remain at pre-assigned static output drive levels.
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3.13 Single-ended pin: an input or output pin that is not part of a pin pair but is an independent path for
information. Contrast with differential pins.
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3.14 ST-pins: Device pins defined as those in need of the Selective Toggle capability defined by this
standard and requiring an output drive capability. (Contrast with “normal pins”.)
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3.15 Test pad: A conductive target on the surface of a printed circuit assembly that can be contacted by a
test probe in a bed-of-nails fixture. This provides electrical access to a circuit node that can be used for
testing.
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3.16 Toggle: A single transition of a signal from one stable state (of two possible states) to a second stable
state.
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3.17 Unbalanced differential pins: The outputs of a differential driver (negative and positive legs) that,
under the influence of instructions defined by this standard, have a non-complementary and asymmetrical
behavior.
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3.18 Unpowered opens test: A test for open pin connections between a printed circuit assembly and
device pins that does not require the assembly to have power applied to support the test.
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4. Technology
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4.1 Evolution of printed circuit assembly technology
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It is the nature of the electronics industry to undergo large technological change on a regular basis. The
driving force for these changes can be traced mainly to “Moore’s Law” that observes that integrated
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IEEE P1149.8.1/D0.7, August 2009
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circuits double in density periodically, typically every 18 months. This has both increased the capabilities
of products while driving down their costs. For printed circuit assemblies, change has manifested itself in
several ways.
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IC packages have become physically smaller while pin counts have risen dramatically. This leads
to concomitant increases in board layout density. Other devices (for example, termination resistors) have also decreased in size to match up better with the decreasing dimensions in board
layouts. Increased layout density may lead to increased board layer counts in order to pack more
interconnects into smaller areas.
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IC operating frequencies have risen dramatically. This leads to the need for controlled impedance
board layout technology. Controlled impedance layout rules are much stricter and will sometimes
lead to increases in board layer counts as intervening layers may need ground planes between
them. As a result, board layouts may contain more interconnect on inner layers that are not visible
at the surface layers, and, layout rules may not permit the application of standard test pads to
surface traces.
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While densities and operating frequencies have risen adding complexity to designing and
manufacturing printed circuit assemblies, there has been contrary pressure to lower the cost of
these assemblies, even though the scaling effects of Moore’s law have not been as accessible to
board technology beyond the integrated circuit level.1 For testing printed circuit assemblies, this
has translated into doing far more over time, but with pressure for an overall reduction in cost.
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High level architecture has also played a role. For example, many product categories consist of multi-board
implementations. These boards are connected directly to each other (or via backplanes) in the final product,
but during individual board test, there may be vacant connectors which do not have mating boards attached.
Global manufacturing, customs and tax laws also create conditions where boards are manufactured and
tested while certain components (typically large, costly components) are missing. Such components are
thus socketed so that they can be added later. Thus, vacant sockets become a test problem – how can they
be tested for proper assembly and attachment?
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4.2 Shifts in board testing challenges
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These evolutionary trends create board test issues and can be categorized as density-driven, or architecturedriven. Density-driven problems come from growing difficulty in physically accessing specific points
within a board for test purposes. Access limitations have been predicted for over 20 years and some designfor-testability technologies such as IEEE Std 1149.1 Boundary-Scan have been developed and adopted to
varying degrees across the electronics industry. However, adopting Boundary-Scan has a lesser effect on
solving architecturally-driven problems; that of large amounts of interconnect that cannot be tested in
traditional ways even when Boundary-Scan is available to counteract declining access. A major example of
this problem is when Boundary-Scan devices are connected to non-Boundary-Scan devices, even passive
devices like connectors and sockets. While Boundary-Scan can test interconnections between compliant
devices, it was not specifically intended to test interconnections to devices that cannot cooperate via that
standard.2
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In the middle of the 1990s, a novel test technology was invented which quickly became widely adopted,
known generically as unpowered capacitive opens testing. This technology is described in Annex A, where
sections A.1 and A.2 describe a test coverage problem, and a solution presented by unpowered capacitive
opens testing. Section A.3 then discusses how this test technique, originally developed for boards where
significant physical access is possible, can be updated by using Boundary-Scan to provide test stimulus
1
Gains provided by Moore’s law, it is argued, should not be dissipated at the board and system levels.
Note that conventional digital ICs may be tested with Boundary-Scan resources that exist in surrounding compliant devices, if
enough of those resources exist to support such a test, and any timing requirements of the test can be honored by such an approach.
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where physical access is no longer possible. Note that the “unpowered” property is eliminated when
Boundary-Scan is utilized. While Boundary-Scan can indeed provide some relief, there are some significant
defect coverage deficiencies, described in section A.4, that remain. In essence, the IEEE 1149.1 standard
does not provide enough capability to adequately solve this problem. New capabilities added to BoundaryScan that can provide a solution are the subject of this standard and are provided in following clauses.
6
4.3 Signal pin types
7
4.3.1 Classification of pins
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13
When implementing this standard, a device designer should take note of the intended use of a device and
then categorize the signal pins as “normal” or in need of “selective toggle” functionality. This standard will
refer to these categories as normal pins and as “ST-pins”. The normal pins will be implemented in full
compliance with IEEE Std 1149.1. The ST-pins will also have full compliance with IEEE Std 1149.1, but
will respond to new instructions provided by this standard. ST-pins will have more capability in these
significant ways:
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15
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18
⎯
All pins identified as ST-pins that would normally be implemented as inputs only will be given
drive capability as well. This effectively converts them to bidirectional pins and they must be provisioned with Boundary-Scan capabilities per IEEE Std 1149.1 rules for bidirectional pins. The
system behavior of these drivers could be permanently disabled, with the test mode behavior
controlled by a boundary register control cell.
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⎯
Single-ended pins identified as ST-pins will be provided with self-monitoring observe capability,
per option 2 of rule 11.6.1a) in IEEE Std 1149.1-2001. The threshold used to determine the logic
level should not be close to the level that two adjacent drivers might reach when they are at
opposite states and shorted together. The self-monitoring feature is intended for use with EXTEST.
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24
⎯
Differential pins identified as ST-pins will be provided with self-monitoring observe capability.
The self-monitoring feature is intended for use with EXTEST.
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26
⎯
All pins identified as ST-pins will be provided with new drive functionality under the control of
new testing instructions provided by this standard.
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⎯
Differential drivers will have an “unbalancing” feature added so that the two normallycomplementary legs will exhibit differentiated waveforms while under the control of new instructions provided by this standard. Because of this, both pins of a differential pair (never just one) are
classified either as normal or as ST-pins.
Normal pins will perform as if EXTEST has been loaded when these new testing instructions are in effect.
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The decision on pin classification is made with respect to the anticipated board architecture that a device is
intended to reside within, and to the goals required for adequate test coverage for the board architecture.
The principle example of board test technology is described in Annex A, but others exist or may be
developed as a result of the capabilities offered by this standard. An example of a board architecture that
would require pin classification is shown in Figure 2. In this example, device U1 will be given a BoundaryScan capability, but is also being considered for compliance to this standard.
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The signal pins of U1 are circled and labeled as normal (in black) or ST-pins (in blue). The decision is
based on whether Boundary-Scan can test the interconnections to other devices. The interconnections
between U1 and both U2 and U3 are fully provisioned with 1149.1 in all these devices. Those pins of U1
that connect to U2 and U3 are classified as normal. However the interconnect between U1 and the socket
S1 and the connectors C1, C2 and C3 are untestable for open connections, since all of the devices S1, C1C3 will be vacant during test. The pins involved here are classified as ST-pins as devices S1, C1-C3 are
incapable, by themselves, in participating in a Boundary-Scan test. The test strategy is to use capacitive
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opens test to supply coverage for these device interconnects. Note that U1 will need additional drive
capability (bidirectional) on those ST-pin signals that propagate to U1 from a socket or connector (circled
in red). This has the added benefit that the functional inputs, since they are to be provisioned with
bidirectional capability, can be tested with Boundary-Scan tests for shorts.
C3: Memory connector (empty)
C2: Memory connector (empty)
C1: Memory connector (empty)
ST-pins
U2:
BoundaryScan
device
S1:
Large socket for a silicon device
that is not present during board
testing.
5
6
7
8
9
Normal
pins
U1:
Silicon device
undergoing pin
classification.
U3:
BoundaryScan
device
Figure 2 — Board architecture determining pin classification.
So the device designer, utilizing information about board architecture and test coverage needs, will
categorize device pins into “normal pin” and “ST-pin” types at the outset of implementing this standard.
The device designer may also incorporate scheduling, technology and economic factors into the decision,
trading off defect coverage.
10
4.3.2 Differential pins
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A specific requirement for this standard is that differential drivers of ST-pins, under the influence of an
instruction from this standard, become unbalanced. It is instructive to look at a “typical” differential driver
circuit and its normal behavior. A simplified circuit is shown in Figure 3. This circuit is a steering network
for a current source IS and a termination RS. When data 0 is applied, two of the four FETs (Field Effect
Transistors) turn on steering the current I0 in one direction through RS. When a data 1 is applied the
opposite FETs turn on (while the original FETs turn off) reversing the current I1 in RS. Since the
magnitudes of IS = I0 = I1, this means the voltage drop across RS will switch so that the voltage drop
changes sign, but otherwise has the identical value for either polarity of data. A downstream differential
receiver will ignore voltage offsets and respond only to the voltage drop. The net effect is the two leg
voltage waveforms will appear to be nearly perfectly symmetric to each other centered at some offset
voltage.
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27
The capacitive opens test technique (see Annex A) depends on a signal being capacitively coupled into a
sense plate. If the capacitance from signals Pos and Neg in Figure 3 are coupled to a sense plate with
approximately equal capacitance, then, being symmetric they will cancel and the sense plate will see no net
signal. To get an observable signal at the sense plate, one of the legs of the differential amplifier, under
control of a specific condition set up by this standard, must be made different, or unbalanced with respect
to its complementary signal.
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One way to do this is to examine the effect of the current source IS. The amount of current produced by the
current source determines the voltages seen at the outputs Pos and Neg. The two waveform charts in Figure
3 show the voltages at Pos and Neg when IS is set to 6 mA and 12 mA. The voltage swing at the pins
changes by a factor of 2, and there is an offset change which is a function of the voltage drops across the
FETs.
Voltage (IS = 12 mA)
6
Differential
Driver
2.25v
1.05v
1
0
Neg
Pos
1200 mV
Data
Time
Pos
I0 R S
I1
Data 0,1
Current Source
IS
Voltage (IS = 6 mA)
Neg
2.775v
2.175v
1
0
Neg
600 mV
Pos
Data
Time
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8
9
10
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Figure 3 — Simplified schematic for a differential driver.
By adding a control signal to the current source, it can switch between two levels of current. This allows
controlled unbalancing. During testing the Data signal would be held constant while the current control
signal would be toggled, producing waveforms on the two legs, as seen in Figure 4. There is action on both
legs, but both legs are now in phase instead of being perfectly symmetrical. Thus a defect-free pair of legs
will now generate a visible signal in a sense plate rather than the null signal seen before due to cancellation
by symmetry. However, setting Data to 0 or 1 causes one of the two pins to have somewhat more swing
than the other, but, since the measurement of capacitance (at the sense plate) is largely independent of
signal amplitude, two pins worth of capacitance would be measured in either case. This means this scheme
could detect one pin being open, but not allow reliable indication which of the two was open. If both were
open, then no signal would be detected indicating both pins were open.
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Voltage (Data = 0)
IEEE P1149.8.1/D0.7, August 2009
Differential
Driver
2.775v Neg
2.250v
2.175v
Pos
1.05v
0.525 v
1.125 v
12 mA
Current Select
6 mA
Time
Pos
I 0 RS
I1
Voltage (Data = 1)
Neg
Data 0,1
Current
Select 0, 1
Current Source
IS=6,12 mA
2.775v Pos
2.250v
2.175v
1.05v
0.525 v
1.125 v
Neg
12 mA
Current Select
6 mA
Time
1
2
3
4
5
6
7
8
Both Figure 3 and Figure 4 show a source termination resistance RS that provides a path for the current
flow. RS could be implemented within the IC, or be provided as part of external circuitry. If RS is part of the
external circuitry, this path may not exist. For example, the path could be broken due to an open defect at a
device pin, or, because the termination is located on a plug-in assembly that will not be present during
testing. (The device itself is assumed to be defect-free, meaning the current path would not be interrupted
on-chip.) In the first case a defect causes the open path where in the second, a defect-free path will not pass
current.
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[Editor’s note: On my (potentially flawed) analysis, for the case where the current path is open, we
could get nearly rail-to-rail complementary signals in Figure 3, and in Figure 4, we would NOT get
the unbalancing, but also get rail-to-rail complementary signals. If this is true, then maybe we have
to mandate that differential signals have termination before these differential signals can be declared
to be “ST-pin” signals. The termination could be on-chip, or, by agreement with the device users, be
implemented on the PCA. If PCA-based termination is expected, then maybe this fact should be
documented in the BSDL for checking.]
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17
The current sources in Figure 3 and Figure 4 could be implemented as shown in Figure 5. (Note the
selectable current source implementation shown is one of several that are possible.)
18
The control of the data and current select signals in Figure 3 and Figure 4 are given in clauses 5 and 6.
Figure 4 — Driver with a controllable dual-current source.
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Current
Select
Current
Select
Standard Current Source
Selectable Current Source
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4
[Editor’s note: What should the specs be on the output waveforms in the loaded and unloaded case?
Steve Sunter suggests “AC sum of the differential signals should meet the same spec as for singleended signals”.]
5
4.4 Defects targeted by the standard
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7
8
9
10
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Figure 5 — Current source implementations.
This standard (as well as IEEE Std 1149.1) provides test support for detecting “manufacturing process
defects” that are found on printed circuit boards coming out of the manufacturing process. These defects
include missing devices (ICs, resistors, capacitors, etc.), improperly mounted devices (e.g., rotated 180
degrees), open solder joints, shorted solder joints, misaligned and dead devices. This standard focuses on
those defects concentrated in interconnect between devices that support this standard and other devices,
passive or active, that do not, but are testable by virtue of a non-contact sense technology. (See Annex A.)
Device implementing this
standard, in test mode.
Device being
sensed.
1
U1
Node1
1
2
2
Pwr
3
Gnd
Node2
4
Node4
5
6
Node5
1
2
S1
3
Node3
C1
1
4
2
5
1
6
7
2
8
R1
Pwr
Gnd
7
Node6
1
C2
1
8
12
13
14
Node8
2
Node7
R2
2
C3
Node9
Figure 6 — Interconnects between a stimulating device and a device being tested.
Figure 6, along with Table 1, show a group of interconnect defects between a device U1 that implements
this standard and device S1 that is to be tested. U1 is in test mode so all of its ST-pins have drive and self11
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monitor capability. Device S1 has a non-contact test sensor in place. Other devices such as coupling
capacitors and termination resistors exist. A listing of possible defects and their effects is shown in Table 1.
3
Table 1 — Potential defects for the circuit in Figure 6
Defect
ID
2
3
Defect site
(Note 1)
Node1 shorted to fixed
voltage (power or ground)
U1 pin 1 open
C1 pin 1 open (Note 3)
Missing solder, bent pin
Missing solder, missing capacitor
4
Node1 shorted to Node2
Excess solder
1
Possible defect cause(s)
Excess solder
6
Node3 shorted to fixed
voltage (power or ground)
Node2 shorted to Node3
7
Node4 shorted to Node5
Excess solder, defective resistor
8
R1 pin 1 open
Missing solder, missing resistor
9
U1 pin 4 open
Missing solder, bent pin
10
U1 pin 7 open
Missing solder
11
Node5 shorted to Node7
Excess solder
12
S1 pin 7 open
Missing solder, bent pin
13
Node7 shorted to Node9
Excess solder, defective resistor
14
R2 pin 1 open
Missing solder, missing resistor
15
Both U1 pins 4 and 5 open
Missing solder, bent pins
16
Node1 shorted to Node7
Excess solder
5
Typical failure syndrome(s)
Fails EXTEST self-monitor;
reduced signal at sense plate
Reduced signal at sense plate
Reduced signal at sense plate
Fails EXTEST self-monitor;
reduced signal at sense plate
Excess solder
Reduced signal at sense plate
Excess solder, defective capacitor
Not detected
Fails EXTEST self-monitor; excess
amplitude in unbalanced mode may
be sensed, but depends on driver
technology.
Not detected
Reduced signal at sense plate
(Note 2)
Reduced signal at sense plate when
testing pin 5. Increased signal at
sense plate when testing pin 6
(Note 2)
Increased signal at sense plate when
testing U1 pin 5. Reduced signal at
sense plate when testing U1 pin 7
Reduced signal at sense plate
Increased signal at sense plate when
testing either U1 pin 7 or U1 pin 8.
Possibly detected dependent on
driver technology. (Note 4)
Not detected
No signal sensed when driver is
complementary. Reduced signal at
sense plate when driver is
unbalanced.
Increased signal at sense plate when
testing U1 pin 1. Reduced signal at
sense plate when testing U1 pin 7
NOTE 1— Defects that are equivalent or symmetric in behavior have only one entry in this table.
NOTE 2— Some syndromes will depend on terminations.
NOTE 3— Assumes the coupling capacitance is large compared to the sensed capacitance. This is typically true by
several orders of magnitude.
NOTE 4— For example, LVDS technology can give a reduced sensed signal, but CML may produce
complementary (cancelling) signals.
4
5
In Table 1 all defects except 6, 8 and 14 are testable with conventional Boundary-Scan and/or capacitive
sensing.
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4.5 Selective Toggle Theory of Operation
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3
4
This is a high-level discussion of how board testing for manufacturing defects, using Boundary-Scan and
capacitive sensing measurements are facilitated by Selective Toggle. Details, rules and recommendations
follow in clauses 5 and 6.
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6
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Before Boundary-Scan-type tests are conducted, many board testers will conduct tests with the board in an
unpowered state. Such testers depend on nodal access to many points on surface(s) of the board. Shorts
testing is conducted at this time, as well as the measurement of many passive component values, as
supported by nodal access. In some cases, access limitations will not allow some components or potential
shorts to be tested. These are then left for other test techniques to follow that require the board to be
powered. Defects found in the unpowered state (particularly shorts) may be repaired before proceeding.
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As with all Boundary-Scan-type tests, a PCA is first properly conditioned to support the test. Conditioning
includes powering up the necessary portions of the board in an appropriate sequence, and then asserting
control states on important nodes, such as power-on reset signals, oscillator disables and bus disables as
needed to bring the board to a stable state conducive to the test. Note that part of a Boundary-Scan test
strategy may be to use Boundary-Scan driver resources to condition certain board signals to high or low
values to further support the needs of the test during its execution. This becomes a “background pattern” of
node states needed to support the test. In some cases, this background pattern must be held constant for the
duration of the test and thus supersedes testing of those nodes. Analysis of such cases is a part of test
engineering.
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Conventional Boundary-Scan testing using the 1149.1 EXTEST instruction may then be run since it
focuses on finding shorts and open connections between Boundary-Scan devices. If shorts are indeed
detected, power may be quickly removed from the board to prevent damage. These may be repaired before
continuing; a decision made by the test engineering. The detection of opens may not precipitate such action
since they are less likely cause damage. Indeed, a test engineer may run a selection of Boundary-Scan tests
that focus on various defects, ordered to find dangerous shorts quickly, followed by less damaging defects
later. Each such test may be “stand-alone” meaning it is entirely responsible for setup of the test conditions
it needs and is not dependent on other preceding tests to leave these conditions behind. Such tests can be
rearranged in order, or even skipped if desired. Such tests will start and end in the Test-Logic-Reset state.
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When a Boundary-Scan test making use of the features in this standard is first initiated, all the ICs that
participate are in system mode, meaning their I/O pins are controlled by their system functionality. Using
the PRELOAD instruction, boundary register states are set up as will be needed by the test when it enters
test mode, controlled by either EXTEST or the SELECTIVE_TOGGLE instruction provided by this
standard.. To simplify this discussion, assume there is only one IC being used to test one device-under-test
(DUT) with the SELECTIVE_TOGGLE instruction. The normal pins will behave as per EXTEST, but the
ST-pins will perform as specified by SELECTIVE_TOGGLE.
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The preload sequence is used to deliver a background pattern of necessary hold states, and also, an initial
state pattern for all normal and ST-pins. This can be a simple all-zero or all-one pattern for the ST-pins, or
a more random-looking pattern needed to enhance test performance. For example, some ST-pins might fan
out to an array of memory ICs and it is necessary to assure that all the chip-select lines of this array are all
one, while the write enables are all zero. This would become part of an initial state shifted in by
PRELOAD.
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Once the initial state is set up, then the SELECTIVE_TOGGLE instruction is loaded and activated. This
causes all normal and ST-pin drivers to take on their initial states. The boundary register is still in place for
shifting and updating. However, the normal pins behave as EXTEST mandates, meaning any new states
updated to these pins will change their states. The ST-pins will interpret ones shifted into their register cells
not as new data, but as a command for that pin to toggle from and back to its initial state while in the RunTest/Idle TAP state. One or more transitions may occur depending on how long the Run-Test/Idle TAP
state persists. If a zero is shifted in, that is a command for that pin to retain its initial state for the duration
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in Run-Test/Idle. On subsequent shifting, new pins can be selected to toggle while previously toggled pins
again become quiescent. For testing with capacitive sense plates, only one pin (per plate) is selected for
toggling while all the rest are held at static states. The number of transitions sensed by the capacitive plate
is determined by the technology used to convert transitions into test information. Depending on this
technology, 1 transition (a step function), 2 transitions (an impulse function) or many transitions (producing
a frequency) may be required. The SELECTIVE_TOGGLE instruction is designed to offer this flexibility.
7
5. Instructions
8
9
IEEE Std 1149.1 is the foundation for this standard. All instructions provided by IEEE Std 1149.1 perform
as specified in that standard for all pins.
10
5.1 IEEE Std 1149.1 instructions
11
5.1.1 Rules
12
13
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a)
17
5.1.2 Description
18
19
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22
IEEE Std 1149.1 allows a single data register cell to control a differential driver, but treats this situation as
a digital-to-analog boundary, where no rules are given to govern the behavior of the analog portion. IEEE
Std 1149.1 does maintain that there be no signal inversion between data register cells and digital pins. Rule
a) in 5.1.1 clarifies that a single data register cell providing data to a differential driver that controls a pair
of pins will have no inversion with one pin and signal inversion with the other.
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5.2 Instructions for selective toggling and guarding
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This standard mandates the addition of two new instructions. The first is TOGGLE_SETUP (see 5.3) and
the second is SELECTIVE_TOGGLE (see 5.4). The TOGGLE_SETUP instruction is used to control
parametric performance features of the SELECTIVE_TOGGLE instruction. The SELECTIVE_TOGGLE
instruction provides the ability to cause ST-pin drivers to either hold stable logic values, or to toggle
selected pins a precise number of times, and at a toggle frequency determined by the TCK frequency. The
toggle frequency is a divided value of TCK controlled by toggle control register loaded by the
TOGGLE_SETUP instruction.
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5.3 The TOGGLE_SETUP instruction
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This standard specifies a mandatory normal mode instruction, TOGGLE_SETUP, which allows parameters
that control the behavior of SELECTIVE_TOGGLE to be loaded into a toggle control register (see Clause
7). While this instruction is in effect, the I/O pins of the device are in their system mode of operation.
All instructions specified by IEEE Std 1149.1 shall perform as specified in that standard, and for any
such instruction that controls or observes pins, all pins shall also perform as specified by that
standard, with one exception: for any output or bidirectional pair of pins controlled by a differential
driver, there shall be a logical inversion between the boundary register data cell and one of the driven
pins.
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5.3.1 Rules
2
3
4
5
6
7
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10
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a)
A TOGGLE_SETUP instruction shall be provided for components that possess ST-pins.
b)
The TOGGLE_SETUP instruction shall become effective at the falling edge of TCK in the Update-IR
TAP Controller state.
c)
While the TOGGLE_SETUP instruction is in effect, the device system pins shall operate in system
mode.
d)
The TOGGLE_SETUP instruction shall select only the toggle control register to be connected for
serial access between test data in (TDI) and test data out (TDO) in the Shift-DR TAP Controller state.
e)
While the TOGGLE_SETUP instruction is in effect, data bits shall be shifted into the toggle control
register upon rising edges of TCK while in the Shift-DR TAP controller state.
f)
While the TOGGLE_SETUP instruction is in effect, data bits shall be loaded into the parallel hold
portion of the toggle control register upon the falling edge of TCK in the Update-DR TAP controller
state.
14
NOTE— The meaning of the data bits in the toggle control register is described in Clause 7.
15
5.3.2 Permissions
16
a)
17
5.3.3 Description
18
19
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21
22
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The TOGGLE_SETUP instruction is used to load configuration data into a toggle control register. This is a
data register that operates as defined by IEEE Std 1149.1 for data registers. The configuration data controls
the performance of the SELECTIVE_TOGGLE instruction (see 5.4). The TOGGLE_SETUP instruction is
a system mode instruction, so the normal behavior of the device and its I/O is unaffected by this instruction.
It is intended that this instruction be used to configure the toggle control register with bits appropriate for
the SELECTIVE_TOGGLE instruction’s subsequent operation before entering test mode
24
5.4 The SELECTIVE_TOGGLE instruction
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This standard specifies a mandatory test mode instruction, SELECTIVE_TOGGLE, which governs new
capabilities defined for ST-pins (see 4.3.1). All normal pins will perform as if the IEEE Std 1149.1
EXTEST instruction is operating whenever the SELECTIVE_TOGGLE instruction is effective.
28
5.4.1 Rules
29
a)
30
NOTE 1—ST-pins are identified by the classification process described in 4.3.1 and 6.1.
31
NOTE 2—ST-pins are provisioned with drive capability (see 6.3.2) and self-monitoring capability (see 6.3.1).
32
NOTE 3—ST-pins that are differential are provisioned with unbalancing capability described in 6.3.4.
33
34
b)
The binary value(s) for the TOGGLE_SETUP instruction may be selected by the device designer.
A SELECTIVE_TOGGLE instruction shall be provided for components that possess ST-pins.
The SELECTIVE_TOGGLE instruction shall become effective at the falling edge of TCK in the
Update-IR TAP Controller state.
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NOTE—By “effective” it is meant that (enabled) system pins shall respond to the content of the boundary
3
4
5
6
c)
7
8
9
d)
register as specified below
The SELECTIVE_TOGGLE instruction shall select only the boundary register to be connected for
serial access between test data in (TDI) and test data out (TDO) in the Shift-DR TAP Controller state.
NOTE—The boundary register is the same register, in length, organization, and construction as that targeted
by the EXTEST instruction.
Normal pins shall perform exactly as specified for the EXTEST instruction by IEEE Std 1149.1
whenever the SELECTIVE_TOGGLE instruction is effective, based on the content of the boundary
register.
10
NOTE—Normal pins are identified by the classification process described in 4.3.1 and 6.1.
11
12
13
e)
14
NOTE— The content of the boundary register driver control cells will determine which drivers are enabled.
15
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17
f)
18
NOTE—Normal pins will transfer the content of their capture flip-flops to the update flip-flops as per IEEE Std 1149.1.
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g)
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NOTE 1—From IEEE Std 1149.1, a driver may have an optional control cell in the boundary register that controls
whether it is enabled to drive a valid state or produces an undriven state. These control cells may be updated with
different data each time the Update-DR state is passed while SELECTIVE_TOGGLE is in effect. When enable data is
changed, drivers may become enabled or disabled, and the results of this should be factored into test algorithm design.
34
35
NOTE 2—The “toggle select condition” exists for an ST-pin when the capture flip-flop for that pin’s data cell contains
a ‘1’. If the cell contains a ‘0’, then the condition does not exist.
36
37
NOTE 3—The “selected falling edge” of TCK is that determined by the TCK divisor held in the toggle control register,
as loaded by the TOGGLE_SETUP instruction. See the discussion in 6.4.
38
39
NOTE 4—When toggling of an ST-pin is concluded the final state is recorded in the boundary register data cell for that
ST-pin, and this may be the opposite state that was originally established by rule 5.4.1e).
40
41
h)
With the SELECTIVE_TOGGLE instruction shifted into the Instruction Register, then upon the
falling edge of TCK in the Update-IR state, the ST-pin drivers will behave identically to the behavior
of EXTEST, based on the content of the boundary register.
With the SELECTIVE_TOGGLE instruction in effect and when a falling TCK edge occurs in the
Update-DR TAP state, the update flip-flop of the data cells associated with ST-pins shall retain their
current state.
With the ST-pin driver in an active (enabled) state, the SELECTIVE_TOGGLE instruction in effect
and when a toggle select condition exists for that pin, the output signal on that ST-pin shall be
controlled as follows:
1)
the output signal shall transition to the opposite of the state resulting from rule 5.4.1e) on the
first falling edge of TCK that occurs after entering the Run-Test/Idle TAP Controller state, and
2)
the output signal shall invert its state on subsequent selected falling edges of TCK while still in
the Run-Test/Idle TAP Controller state, and
3)
the output signal shall not change its driven state at any other time that the
SELECTIVE_TOGGLE instruction remains effective, and
4)
upon exiting the Run-Test/Idle state, the final state of the output signal shall be held in the
associated boundary register data cell update flip-flop.
When an ST-pin driver is disabled, the input to that driver shall still behave as mandated in rule g)
above.
16
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1
2
NOTE—Only part 4) in rule g) can be observed by examining subsequent pin behavior, that is, when the driver is later
enabled.
3
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5
6
i)
7
5.4.2 Permissions
8
9
a)
With the ST-pin driver in an active (enabled) state, the SELECTIVE_TOGGLE instruction in effect
and a toggle select condition absent for that pin, the output signal on that AC pin shall be controlled
exactly as specified for the EXTEST instruction by IEEE Std 1149.1, with its state determined by the
content of the update flip-flop of the associated boundary register data cell.
The binary value(s) for the SELECTIVE_TOGGLE instruction may be selected by the device
designer.
10
5.4.3 Description
11
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17
The SELECTIVE_TOGGLE instruction implements new stimulus behaviors for ST-pins and simultaneously behaves identically to IEEE Std 1149.1 EXTEST for normal pins. The SELECTIVE_TOGGLE
instruction causes data produced by selected ST-pin drivers to be inverted on the first falling edge of TCK
after entering the Run-Test/Idle TAP Controller state, and to be subsequently toggled on selected falling
edge of TCK while remaining in the Run-Test/Idle state. Upon exiting the Run-Test/Idle TAP Controller
state, the driver may be in its original or inverted states. ST-pin drivers that are not selected, and drivers on
normal pins, remain constant.
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22
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25
NOTE—Drivers implementing EXTEST_TRAIN from IEEE Std 1149.6 may change state one-half TCK cycle after
leaving the Run-Test/Idle TAP Controller state so that the state of the driver is the same as when Run-Test/Idle was
entered. This behavior is not implemented by SELECTIVE_TOGGLE. This should be kept in mind when
implementing both IEEE Std 1149.6 AC-pin behavior and ST-pin behavior on the same pins of a device.
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Also, before the SELECTIVE_TOGGLE instruction is loaded into the Instruction Register, the boundary
register is preloaded with initial data using the PRELOAD instruction. This initial data will be used by
SELECTIVE_TOGGLE to define the initial static states of each ST-pin. Each ST-pin will then either hold
this state, or toggle this state at the appropriate times, when not enabled or enabled for toggling,
respectively. The selection of holding or toggling is determined by subsequent data loads shifted into the
boundary register while SELECTIVE_TOGGLE is in effect. This PRELOAD sequence used to prepare for
SELECTIVE_TOGGLE operation is shown in Figure 7, where at the time flagged by Note 1 (falling edge
of TCK in the Update-DR state) the shifting of preload data is just being completed and the data is being
updated in the Update flip-flops of the boundary register cells. After that time, the Instruction Register
shifting for loading the SELECTIVE_TOGGLE opcode is performed. Then at the time flagged by Note 2
(falling edge of TCK in the Update-IR state) the SELECTIVE_TOGGLE instruction is updated into the
Instruction Register. As a result of this, the boundary register takes control of the output drivers as the
device moves from system mode to test mode. Two ST-pin traces are shown; one that is in hold mode
(labeled the “hold driver”) and one that is going to be enabled for toggling (labeled the “toggle driver”).
Figure 7 shows both of these ST-pins taking the low state, although either pin may take any desired initial
state. The right side of this diagram contains ellipses that form a starting point for some following diagrams
that illustrate important SELECTIVE_TOGGLE behaviors.
Before the SELECTIVE_TOGGLE instruction is loaded into the Instruction Register, the toggle control
register is preloaded with initial data using the TOGGLE_SETUP instruction. This determines the TCK
divisor that will be used to determine the number of TCK falling edges that separate ST-pin transitions
when in the Run-Test/Idle TAP controller state.
17
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IEEE P1149.8.1/D0.7, August 2009
Note 1
Instruction
TAP State
Note 2
PRELOAD
E1DR
PRELOAD
UDR
SDRS
SIRS
CIR
SIR
E1IR
SELECTIVE_TOGGLE
SDRS
UIR
CDR
SDR
TCK
Hold Driver
(System Mode)
(Test Mode)
Toggle Driver (System Mode)
(Test Mode)
1
2
3
4
5
6
7
8
9
10
11
The diagram in Figure 8 begins at the end of shifting data into the boundary register (see the right side of
Figure 7) after SELECTIVE_TOGGLE has become effective. The bits shifted into the boundary register
determine which ST-pins will be enabled for toggling (signified by a 1) and those that will hold their
current state (signified by a 0), while in the Run-Test/Idle state. At the time flagged by Note 3 (the first
falling edge of TCK in the Run-Test/Idle state) the toggle driver changes state while the hold driver stays
stable. The Run-Test/Idle state is exited after just one TCK cycle, so the toggle driver remains static in the
new state. Subsequent shifting of new data into the boundary register could change the current toggle
driver(s) into hold driver(s) and another hold driver could be selected for toggling. Again note that this
example showed both the hold driver and toggle driver starting in the low state, but either could have been
high at the start, depending on the preloaded data.
12
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20
21
22
This behavior can be used to support test algorithms (and associated tester hardware) that utilize a step
function as the measurement stimulus. Typically, the step function is sensed by tester hardware that
responds to a single transition at a known point in time. It may also require that no new stimulus events
occur for some time after the step function occurs in order not to interfere with the measurement. This time
between events could be assured by the length of time that it takes to shift a new toggle/hold pattern into
the combined chain boundary registers. If the underlying test algorithm finds the shift time is insufficient,
then more time can be inserted by programming a higher TCK divider value and waiting in the RunTest/Idle state for a lesser time, such that no additional transition occurs before leaving the Run-Test/Idle
state. Time delay can also be inserted by passing to the Pause-DR state for some arbitrary length of time
during the shifting of new data. The fact that the toggled pin is left in the opposite state must also be
accounted for by the test algorithm, as appropriate.
Figure 7 — PRELOAD sequence used to set up SELECTIVE_TOGGLE operation.
Instruction
TAP State
SELECTIVE_TOGGLE
SDR
E1DR
UDR
RTI
SDRS
CDR
SDR
TCK
Hold Driver
(Test Mode)
Note 3
Toggle Driver (Test Mode)
23
(Test Mode)
Figure 8 — Using SELECTIVE_TOGGLE to perform a step function.
18
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IEEE P1149.8.1/D0.7, August 2009
SELECTIVE_TOGGLE
Instruction
TAP State
SDR
E1DR
UDR
RTI
RTI
SDRS
CDR
SDR
TCK
Hold Driver
Note 3
(Test Mode)
Toggle Driver (Test Mode)
1
2
3
4
5
6
7
8
9
10
11
12
The diagram in Figure 9 also begins at the end of shifting data into the boundary register (see the right side
of Figure 7) after SELECTIVE_TOGGLE has become effective. The bits shifted into the boundary register
determine which ST-pins will be enabled for toggling (signified by a 1) and those that will hold their
current state (signified by a 0), while in the Run-Test/Idle state. In this example, assume the TCK divisor is
0, meaning no extra TCK cycles are waited between pin transition events. At the two times flagged by Note
3 (falling edge of TCK in the Run-Test/Idle state) the toggle driver changes state while the hold driver stays
stable. The Run-Test/Idle state is exited after two TCK cycles, so the toggle driver returns to its initial state.
Subsequent shifting of new data into the boundary register could change the current toggle driver(s) into
hold driver(s) and another hold driver could be selected for toggling. Again note that this example showed
both the hold driver and toggle driver starting in the low state, but either could have been high at the start,
depending on the preloaded data.
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20
21
22
This behavior can be used to support test algorithms (and associated tester hardware) that utilize an impulse
function for the measurement stimulus. One parameter of importance may be the width of this impulse,
which can range from one TCK period, to 1/8000th of a second per the rules of the TCK divider (see 6.4). It
may also require that no new stimulus events occur for some time after the impulse function occurs in order
not to interfere with the measurement. This time between impulse events could be assured by the length of
time that it takes to shift a new toggle/hold pattern into the combined chain boundary registers. If the
underlying test algorithm finds the shift time is insufficient, then more time can be inserted by waiting in
the Run-Test/Idle state for a lesser time than the TCK delay time such that no additional transition occurs
before leaving the Run-Test/Idle state. Time delay can also be inserted by passing to the Pause-DR state for
some arbitrary length of time during the shifting of new data.
Figure 9 — Using SELECTIVE_TOGGLE to perform an impulse function.
Instruction
TAP State
SELECTIVE_TOGGLE
SDR
E1DR
UDR
SELECTIVE_TOGGLE
RTI
RTI
RTI
RTI
RTI
SDRS
CDR
SDR
TCK
Hold Driver
(Test Mode)
Note 3 Note 3
Note 3
Toggle Driver (Test Mode)
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28
Figure 10 — Using SELECTIVE_TOGGLE to create a frequency signal.
The diagram in Figure 10 again begins at the end of shifting data into the boundary register (see the right
side of Figure 7) after SELECTIVE_TOGGLE has become effective. The bits shifted into the boundary
register determine which ST-pins will be enabled for toggling (signified by a 1) and those that will hold
their current state (signified by a 0), in the Run-Test/Idle state. In this example, assume the TCK divisor is
0, meaning no extra TCK cycles are waited between pin transition events. At several times flagged by Note
19
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IEEE P1149.8.1/D0.7, August 2009
1
2
3
4
5
6
7
3 (falling edge of TCK in the Run-Test/Idle state) the toggle driver changes state while the hold driver stays
stable. The Run-Test/Idle state is exited after multiple TCK cycles, so the toggle driver returns to its initial
state if the cycle count is even, or stays in the opposite state if the cycle count is odd. Subsequent shifting of
new data into the boundary register could change the current toggle driver(s) into hold driver(s) and another
hold driver could be selected for toggling. Again note that this example showed both the hold driver and
toggle driver starting in the low state, but either could have been high at the start, depending on the
preloaded data.
8
9
10
11
12
This behavior can be used to support test algorithms (and associated tester hardware) that utilize a
frequency signal for the measurement stimulus. One parameter of importance will be the frequency, which
can range from ½ the TCK frequency to around 8kHz, per the rules of the TCK divider (see 6.4). The
amount of time spent in the Run-Test/Idle state will depend on the amount of averaging needed by the
frequency-based measurement.
13
6. Pin implementation specifications
14
6.1 Pin classification
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6.1.1 Rules
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18
a)
The device designer shall survey the expected use of a device’s system pins and shall designate those
that need to support the selective toggle functionality as being “ST-pins”.
b)
All other system pins not selected in a) shall be designated as “normal” pins.
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NOTE—This nomenclature, ST-pins and normal pins (see 4.3.1), will be used in subsequent rules, recommendations
and descriptions. The concept of “system pin” is defined by IEEE Std 1149.1.
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c)
22
NOTE—Thus both will either be classified as normal or as ST-pins.
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6.1.2 Recommendations
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a)
27
6.1.3 Description
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Adding selective toggle functionality will cost a device designer some design time and will consume some
on-chip resources. This must be traded off against benefits gained at PCA testing which may include lower
overall product cost and the acceleration of product development. A designer may be somewhat aware of
these tradeoffs but should consult with board designers and test engineers who know the details of the PCA
application of the device, and who can quantize the benefits of this new functionality.
In the case of differential pairs of signals, both shall be considered together during classification.
The device designer should consult with device users as to the expected uses of pins, and should also
take into account tradeoffs of device costs and design time versus enhanced defect coverage during
testing.
20
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IEEE P1149.8.1/D0.7, August 2009
1
6.2 Implementation of normal pins
2
6.2.1 Rules
3
4
5
6
a)
Normal pins shall be implemented exactly as mandated by IEEE Std 1149.1 for all instructions
defined by that standard.
b)
For the SELECTIVE_TOGGLE instruction defined by this standard, normal pins shall behave exactly
as they would for the EXTEST instruction defined by IEEE Std 1149.1.
7
6.2.2 Description
8
9
10
11
Normal pins implement EXTEST behavior when the SELECTIVE_TOGGLE instruction is active. This
means they can hold logic states or be inactive (high impedance) depending on their implementation and
the content of their controlling boundary register cells. Thus they can participate in selective toggle testing
by holding background logic states needed for the stability of the test.
SO
G1
Mode
System
Logic
M2
1
PI
PO
G1
ShiftDR
M1
1
1
R1
Output
Driver
R2
1D
1D
C1
C1
1
Instruction
Mode
BYPASS
0
SAMPLE and PRELOAD
0
EXTEST
1
SELECTIVE_TOGGLE
1
SI
ClockDR
UpdateDR
Boundary Register Cell BC_1 from
Figure 11-30, IEEE Std 1149.1-2001
12 Figure 11 —Conceptual implementation of a single-ended normal pin boundary register cell.
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NOTE—Figure 11 is not normative. The circuitry shown implements the rules for single-ended output driver cells
found in IEEE Std 1149.1, but is one of many possible designs.
A possible implementation of a normal pin output boundary register cell is shown in Figure 11, taken from
IEEE Std 1149.1 (called a “BC_1” cell) and is reproduced here as a basis for describing boundary register
cells needed for this standard. The mode table in this figure has a new entry for the
SELECTIVE_TOGGLE instruction. The ‘Mode’ signal is provided by instruction decode circuitry, and
would only change value on the falling edge of TCK in the Update-IR TAP state, or the Test-Logic-Reset
TAP state. The “SI” input is the shift input for the cell. The “SO” output is the shift output. These signals
pass boundary register shift data in and out of the cell. The “PI” signal is the parallel input of the cell,
which in this context (an output pin cell) receives data from the system logic of the IC. The “ShiftDR”
signal is derived from the TAP controller and determines whether the R1 flip-flop gets data from “SI”
(during shifting in the Shift-DR TAP state) or from “PI” (during parallel capture in the Capture-DR TAP
state). The “PO” signal is used to provide data to the output driver. Finally, there are two clock signals,
“ClockDR” which loads data into the R1 flip-flop, also often referred to as the “Capture” flip-flop.
ClockDR is derived from the rising edge of TCK and is active in the Capture-DR and Shift-DR TAP states.
21
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IEEE P1149.8.1/D0.7, August 2009
1
2
The “UpdateDR” clocks data into the R2 flip-flop, often referred to as the “Update” flip-flop. UpdateDR is
derived from the falling edge of TCK, and is active in the Update-DR TAP state.
3
4
5
6
7
8
The “self-monitor” capability given in option 2 of rule 11.6.1a) in IEEE Std 1149.1-2001 can be used in
normal pin cell design to increase testability of the board. This option takes the pin state of the device and
feeds it back to the Capture flip-flop so that the pin’s actual state is captured. This enables detection of
shorts, where a driver cannot achieve the state it is trying to reach, Cell BC_10 offers self-monitoring
capability, as shown in Figure 12 but does not support the INTEST instruction. Cell BC_9 does support the
INTEST instruction, at the cost of an extra multiplexer.
Boundary Register Cell BC_10 from
Figure 11-33, IEEE Std 1149.1-2001
Instruction
Mode
BYPASS
0
SAMPLE and PRELOAD
0
EXTEST
1
SELECTIVE_TOGGLE
1
SO
M2
G
System
Logic
PI
Output
Driver
0
PO
1
M1
R2
Q
R1
D
Q
G
0
D
1
CK
CK
SI
Mode
UpdateDR
ShiftDR
ClockDR
9
10
11
12
13
14
Boundary register cells that service normal pins for device inputs an bidirectional pins would be similarly
changed, meaning they would be identical to those designs given in IEEE Std 1149.1, but would have an
entry in their mode tables for the SELECTIVE_TOGGLE instruction, and that mode entry would be
identical to that for EXTEST. This is similarly true for boundary register cells that act as driver enable
control cells for output drivers on normal pins.
15
6.3 Implementation of ST-pins
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Pins designated by the designer as ST-pins start out having system definitions as inputs, outputs and
bidirectional, either single-ended or differential. This standard requires some additional features for these
pins that are to be available in test mode. One example is an ST-pin that in system mode is a simple, singleended input. In test mode it will be required to have a drive capability, so one way to implement this pin
would be to choose a bidirectional design for that pin. This implies a control signal for the drive enable.
The control signal would not exist in the system definition of the device, so the drive capability would not
be accessible in the device while in system mode. In effect, the test mode capability of the pin is a superset
of its system requirement. Note that the BSDL description of this pin will describe this superset, so it will
list this pin as “inout” even though the system mode use of the pin is a simple input.
Figure 12 — A self-monitoring cell for an output pin.
22
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IEEE P1149.8.1/D0.7, August 2009
1
6.3.1 Single-ended output pins
2
6.3.1.1 Rules
3
4
5
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10
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a)
An enabled single-ended output pin, when designated as an ST-pin and when the SELECTIVE_TOGGLE instruction first becomes effective (at the falling edge of TCK in the Update-IR TAP
state) shall produce a low voltage or a high voltage on the pin when the related boundary register cell
contains a 0 or a 1 respectively.
b)
An enabled single-ended output pin, when designated as an ST-pin, during execution of the SELECTIVE_TOGGLE instruction, and when selected for toggling, shall transition between one stable
voltage level to another stable voltage level only at the times given by rule 5.4.1g).
c)
The change in voltage prescribed in rule b) shall be monotonic.
d)
The change in voltage prescribed in rule b) shall occur in a time period no greater than fivc
microseconds as measured from the 10% to 90% levels of change.
e)
The conditions for verifying rules b), c) and d) shall be provided by the device manufacturer in the
device's datasheet section for measuring AC performance.
f)
A single-ended output pin, when designated as an ST-pin, during execution of the EXTEST
instruction, shall load a digitized representation of the driven pin state into the capture flip-flop of the
data cell for that driver in the boundary register, at the rising edge of TCK in the Capture-DR state.
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NOTE— This is the “self-monitor” capability given in option 2 of rule 11.6.1a) in IEEE Std 1149.1-2001.
19
6.3.1.2 Recommendations
20
21
22
23
24
25
a)
The change in voltage prescribed in rule 6.3.1.1b) should be no less than 400 millivolts.
b)
For rule 6.3.1.1f), the threshold voltage used to digitize the output pin state should be significantly
different than the voltage that would appear on the pin when that pin driver was shorted to an adjacent
pin driver.
c)
For rule 6.3.1.1f), the point in the driver-to-pin circuitry where the pin voltage is monitored should be
as close to the pin as possible.
26
6.3.1.3 Description
27
28
29
30
31
32
33
34
Rule 6.3.1.1b) mandates that a toggling pin transition between two voltage levels when so enabled during
operation of SELECTIVE_TOGGLE. One way to do this is to use the existing native driver with its drive
levels and switching time, which should have no difficulty in meeting (exceeding) the requirement of rules
6.3.1.1c) and d). This approach will likely also exceed the minimum voltage swing recommendation of
6.3.1.2a) as well. A robust voltage swing is important to capacitive sensing to help differentiate a toggle
signal from local noise contributions. Indeed, when considering capacitive sense testing it is advised that
test engineers consider the capabilities of their measurement systems with respect to the voltage swings
generated by ST-pins.
35
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38
39
40
41
42
ST-pins will often be those which drive PCA signals that have no tester resources, or, complementary
Boundary-Scan facilities, somewhere else on the PCA to support testing for shorted pins. Since driven pins
on devices are very often adjacent to each other, it is likely that a manufacturing defect might cause a short
between two drivers. If one or both of these pins is an ST-pin, then the self-monitor capability can be used,
during conventional Boundary-Scan (i.e., EXTEST-based) testing to detect these shorts. Rule 6.3.1.1f)
requires the device designer to select option 2 when implementing rule 11.6.1a) of IEEE Std 1149.1-2001.
The self-monitor feature is also active during SELECTIVE_TOGGLE, allowing verification of a driver’s
last output state after exiting the Run-Test/Idle TAP state.
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IEEE P1149.8.1/D0.7, August 2009
1
2
3
4
5
6
7
Recommendations 6.3.1.2b) and c) offer design guidance to help detect shorted drivers. If the voltage that
appears on two shorted driver pins is very close to the threshold voltage, and there are some voltage drops
along the current paths, it is possible for each monitor to digitize the driven values that are above/below the
actual pin’s voltage. This can occur when the short-circuit voltage at the pin, plus or minus the voltage
drops along the current path, gives a voltage seen by the monitor that is above or below the threshold, even
though it is not a valid logic level. If this happens, then both self-monitors may observe “correct” data
when there is a short between the driver pins.
8
9
10
11
12
13
14
A possible boundary register cell design to support single-ended ST-pin drivers is found in Figure 13.
Multiplexers M1 and M2, plus flip-flops R1 and R2 are the same as seen in Figure 12, as are the signals
labeled Mode, PI, PO, ShiftDR, SI, SO, ClockDR, and UpdateDR. Toggle_TCK is the divided version of
TCK given in section 6.4. TogHold is a signal that is 1 only when the effective instruction is
SELECTIVE_TOGGLE. RTIState is a signal that is 1 only when the TAP is in the Run-Test/Idle state. A
new multiplexer M3 is inserted between R1 and R2. Its purpose is to allow a selection of two data sources
to be updated into R2 from R1. Those two choices are
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1)
The content of R1, used to support normal 1149.1 instruction execution, and
2)
The content of R2 when the state of flip-flop R1 is 0, or, the complemented content of R2 when
the state of flip-flop R1 is 1. This content is derived from Exclusive-Or gate E.
The control and multiplexers M1 and M2 are the same as seen before in Figure 12. Clocking of R1 is also
the same. The R2 flip-flop is clocked by one of two signals:
1)
the UpdateDR clock, which only clocks R2 when a falling TCK occurs in the Update-DR TAP
state while the SELECTIVE_TOGGLE instruction is not in effect, or
2)
the UpdateRTI signal which is generated by new logic in the form of gates A, B, C, D and latch
R3.
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IEEE P1149.8.1/D0.7, August 2009
SO
System
Logic
PI
Output
Driver
M2
G
0
PO
1
M1
M3
R2
Q
R1
G
0
Q
G
0
D
D
1
1
ShiftDR
CK
E
CK
SI
ClockDR
Mode
Located near
pins
Located near
TAP
UpdateSelect
RTIState
TogHold
A
D
Q
UpdateDel
UpdateRTI
B
R3
D
G
T-UpdateDR
Toggle_TCK
TogHold is ‘1’ when SELECTIVE_TOGGLE
is the effective instruction. (Note TogHold
only changes in the Update-IR TAP state,
when RTIState is ‘0’.)
The Toggle_TCK signal comes from
the TCK divider subsystem.
Latch R3 suppresses a race condition
between TCK and RTIState.
1
UpdateDR
C
RTIState is 1 when the
TAP is in the Run-Test/Idle
state.
Gates A, B, C, D and latch
R3 can be located near the
TAP, with T-UpdateDR and
UpdateSelect distributed to
all ST-pins.
Instruction
Mode
BYPASS
0
SAMPLE and PRELOAD
0
EXTEST
1
SELECTIVE_TOGGLE
1
Figure 13 — Conceptual implementation of a single-ended ST-pin boundary register cell.
2
3
4
5
6
7
8
9
10
11
12
NOTE—Figure 13 is not normative. The circuitry shown implements the rules for single-ended output driver cells
found in IEEE Std 1149.1 and in this standard, but is one of many possible designs.
13
14
With this structure, data loaded into R1 becomes a selector that determines if a given ST-pin will hold data
(R1 contains 0) or toggle data (R1 contains 1) while in the Run-Test/Idle state. The initial state of the pin is
The UpdateRTI signal produces clocks only when the SELECTIVE_TOGGLE instruction is in effect,
when the TAP is in the Run-Test/Idle state, and when Toggle_TCK is falling (see 6.4). This allows the
loading of R2 with the output of the new M3 multiplexer. Then the capture flip-flop (R1) contains a 0, then
R2 stays constant as Toggle_TCK clocks occur in the Run-Test/Idle state. If R1 contains 1, then each
successive falling edge of Toggle_TCK will invert the state of R2. The state or R2 supplies data to the
output driver which will thus either remain constant or toggle. Latch R3 is only present to suppress a race
condition between RTIState and Toggle_TCK; this race could otherwise improperly clock R2 at incorrect
times. Note that gates A, B, C, D and latch R3 are common to all ST-pins and thus can be located near the
TAP with signals T-UpdateDR and UpdateSelect distributed to all ST-pins.
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1
2
3
4
determined by the data that was updated into the R2 flip-flop by the PRELOAD instruction (at the falling
edge of TCK in the Update-DR TAP state). On subsequent passages through Update-DR while
SELECTIVE_TOGGLE is in effect, the data in R2 is not reloaded from R1, but stays at the last value it had
while in the Run-Test/Idle TAP state.
5
6.3.2 Single-ended input pins
6
6.3.2.1 Rules
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
a)
A single-ended input pin, when designated as an ST-pin, when the SELECTIVE_TOGGLE
instruction first become effective (at the falling edge of TCK in the Update-IR TAP state) shall
produce a low voltage or a high voltage on the pin when the related boundary register cell contains a 0
or a 1 respectively.
b)
A single-ended input pin, when designated as an ST-pin, during execution of the SELECTIVE_TOGGLE instruction, and when selected for toggling, shall transition between one stable
voltage level to another stable voltage level only at the times given by rule 5.4.1g).
c)
The change in voltage prescribed in rule b) shall be monotonic.
d)
The change in voltage prescribed in rule b) shall occur in a time period no greater than fivc
microseconds as measured from the 10% to 90% levels of change.
e)
The conditions for verifying rules b), c) and d) shall be provided by the device manufacturer in the
device's datasheet section for measuring AC performance.
f)
A single-ended input pin, when designated as an ST-pin, during execution of the EXTEST instruction,
shall load a digitized representation of the driven pin state into the capture flip-flop of the data cell for
that driver in the boundary register, at the rising edge of TCK in the Capture-DR state.
22
NOTE—This is the “self-monitor” capability given in option 2 of rule 11.6.1a) in IEEE Std 1149.1-2001.
23
6.3.2.2 Recommendations
24
25
26
27
28
29
30
31
a)
The change in voltage prescribed in rule 6.3.2.1b) should be no less than 400 milivolts.
b)
For rule 6.3.2.1f), the threshold voltage used to digitize the output pin state should be significantly
different than the voltage that would appear on the pin when that pin driver was shorted to an adjacent
pin driver.
c)
For rule 6.3.2.1f), the point in the driver-to-pin circuitry where the pin voltage is monitored should be
as close to the pin as possible.
d)
For rule 6.3.2.1f), the voltage levels produced should be compatible with expected Boundary-Scan
receiver levels of other devices that may be connected to these pins.
32
6.3.2.3 Permissions
33
34
35
a)
A single-ended input pin, when designated as an ST-pin, may be given the capability of disabling its
driver capability, during execution of the EXTEST and SELECTIVE_TOGGLE instructions, under
the control of the content of a boundary register control cell for that pin.
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1
6.3.2.4 Description
2
3
4
5
An important goal of this standard is for ST-pins to have stimulus capability. When a device pin, in its
system definition, is an input, which means a drive capability must be added in test mode so that during
testing (with EXTEST, for shorts, and SELECTIVE_TOGGLE, for opens) defects can be sensed. The rules
and recommendations given in 6.3.2 provide:
6
•
that a drive capability be added to ST-pins that are system inputs,
7
•
the change in driven levels be greater than a minimum amplitude and
8
•
the driven levels can be self-monitored.
9
10
The boundary register cell shown in Figure 13 contains the drive capability needed to support the
transformation of an input pin to an ST-pin input pin.
11
12
13
14
Since this drive capability is only present during testing, that implies an ability to turn it off (for system
operation) that could be made controllable by a boundary register control cell, as allowed by permission
6.3.2.3a). While this adds cost in the form of a new boundary register cell, it adds flexibility for automatic
program generators that analyze PCA interconnections and create Boundary-Scan tests for them.
15
16
17
18
19
One way to add output drive capability to a system input pin is to implement the pin as a bidirectional pin,
where the system mode input to its control cell is fixed at the disabled state. Another is to eliminate the
control cell and only enable the driver when the EXTEST or SELECTIVE_TOGGLE instructions are
effective. Figure 14 shows options on how a normal input pin may be equipped for drive control when they
are designated as ST-pins.
20
21
22
23
24
25
NOTE—Cells BC_1, BC_2, BC_7 and BC_8 shown in Figure 14 are boundary register cells defined in IEEE Std
1149.1.
[Editor’s note: We will have to replace BC_1 (etc.) in Figure 14 and this note with “TH_1” (etc.) as
we refine this document. New cells introduced by this standard contain the extra logic to implement
selective toggle behavior, and while not important for ATPG of Boundary-Scan tests, are useful for
cueing synthesis tools for automated Boundary-Scan insertion.]
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BC_1 Cell
C
U
BC_8 Cell
C
BC_7 Cell
U
EXTEST
SELECTIVE_TOGGLE
Normal Input Pin
1
ST-pin Input Pin
C
U
C
U
BC_2 Cell
ST-pin Input Pin with
control cell
Figure 14 —Normal input pin and two implementations of an ST-pin input pin.
2
6.3.3 Single-ended bidirectional pins
3
6.3.3.1 Rules
4
5
a)
6
6.3.3.2 Description
Single-ended bidirectional pins shall obey the same rules as for single-ended output pins as given in
6.3.1.1 and shall consider the same recommendations given in 6.3.1.2.
7
8
9
10
11
Single-ended bidirectional pins already have the ability to control and observe their connected nodes, so for
the purpose of this standard, it is sufficient to support the drive capabilities required for
SELECTIVE_TOGGLE as given for single-ended output pins in 6.3.1. Also, these pins shall be able to
self-monitor their drivers to detect shorts to other nodes during EXTEST based testing. This implies a cell
design based on the BC_7 or BC_8 cells designs from IEEE Std 1149.1.
12
13
[Editor’s note: This will need updating when we define cells for this standard, probably named TH_7
and TH_8.]
14
15
6.3.4 Differential output pins
16
17
18
19
Differential drivers normally output two complementary signals that, when sensed by a capacitive sense
plate, may cancel almost completely, yielding no reliably discernable signal at the plate. However, if one
signal path has an open connection, then that path will have an attenuated signal and the sense plate will see
the signal from the opposite leg. The phase of the observed signal thus indicates the leg that is open.
20
21
22
For some defect cases, notably, a short across the two legs, or, opens on both legs, there will be little or no
observable signal at a sense plate. The driver is made self-monitoring and can thus detect shorts, and it can
also be operated in an unbalanced mode where the two legs are no longer complementary. This unbalanced
28
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1
2
mode provides a detectable signal when there are no defects present, and will provide a means of detecting
the case of both legs having open defects.
3
6.3.4.1 Rules
4
5
6
7
8
9
10
11
12
a)
If a device contains differential ST-pin drivers, then there shall be at least one additional cell in the
boundary register which is designated as a balance/unbalance bit and be called a “balun” bit, and this
cell shall be denoted as “internal” in the BSDL description of the device boundary register.
b)
When the SELECTIVE_TOGGLE instruction is in effect, all enabled differential drivers shall be
influenced by a balun bit value as follows:
13
14
NOTE—“Substantially tracking” means the waveforms seen at each pin are similar in shape but may differ in the
actual voltages produced. See the example shown in Figure 4 in 4.3.2.
15
16
17
18
19
20
21
22
c)
When the SELECTIVE_TOGGLE instruction is in effect, the positive leg of an enabled differential
driver shall obey rules 6.3.1.1a) through e) given for single-ended outputs.
d)
When the SELECTIVE_TOGGLE instruction is in effect, the negative leg of an enabled differential
driver shall either be complementary to the positive leg (balun = 0) or it shall substantially track the
positive leg (balun = 1).
e)
When the EXTEST instruction is in effect, the states of the two differential pins shall be compared by
a hysteretic comparator and the digitized result captured by the boundary register cell that provides
data for the driver.
23
24
NOTE—This is a self-monitor concept for a differential pair. The hysteresis provides for a stable result when a dead
short appears across the two differential pins.
25
26
27
28
29
f)
30
6.3.4.2 Permissions
31
32
a)
33
6.3.4.3 Description
34
Figure 15 shows an example of a set of differential drivers that share an output enable cell and a balun cell.
1)
If the balun bit is 0, then the differential driver shall operate normally with complementary
voltages appearing on the two legs.
2)
If the balun bit is 1, then the differential driver shall operate in an unbalanced mode with the
voltage at the negative leg substantially tracking the voltage appearing at the positive leg.
The hysteresis of the comparator shall be between 10 and 40 percent of driver’s normal voltage
swing.
[Editor’s note: the 10-40% figures are a rank guess on my part. We want to reject noise that may
make two shorted legs appear to be momentarily different. We should pick values that are easily
implemented.]
More than one balun bit may be added to the boundary register by a designer as needed to alleviate
layout routing problems.
35
36
37
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Enable
Positive Leg
C U
Data
Negative Leg
Balun
C U
C U
System
Logic
C U
Balun Cell
(Internal)
C U
C U
Control
Cell
C U
1
2
3
4
5
The balun cell is an internal cell with no connection to the system logic. It may be located anywhere in the
boundary register that is convenient for signal distribution, and more balun cells can be added if needed.
All differential outputs that are ST-pins must be controlled by a balun cell somewhere in the boundary
register.
6
6.3.5 Differential input pins
7
6.3.5.1 Rules
8
6.3.5.2 Description
9
6.4 Toggle Behavior for ST-pins
10
11
12
13
14
15
Figure 15 : Differential drivers with enable control and balun cells.
A clock signal named Toggle-TCK is used to trigger transition events on selected, enabled ST-pins. This
signal is generated by a set of decodes derived from the TAP state machine, TCK and the instruction
decoder. This signal can have a frequency derived from TCK under control of the toggle control register
content (see clause 7). The value stored in the toggle control register is a delay counter value that governs
the number of TCK falling edges that occur between enabled ST-pin transition events. This value may
range from 0 to 2N-1 where N is the number of bits in the toggle control register. Thus the maximum
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1
2
frequency of ST-pin transitions is ½ TCK (for a delay count of 0) and correspondingly lower frequencies as
the delay count increases.
3
6.4.1 Rules
4
5
6
7
8
9
10
11
12
13
14
a)
When the SELECTIVE_TOGGLE instruction is in effect, a Toggle-TCK signal that triggers
transition events on the selected, enabled ST-pin drivers shall be provided to all ST-pins.
b)
The Toggle-TCK signal shall trigger a first transition event on the first falling edge of TCK after
entering the Run-Test/Idle TAP state.
c)
Subsequent transition events shall be triggered only while the TAP remains in the Run-Test/Idle TAP
state.
d)
The Toggle-TCK signal shall trigger a subsequent transition event when the number of falling TCK
edges that have occurred since the last transition event is equal to the number stored in the toggle
control register.
15
6.4.2 Description
16
17
18
19
The following waveform diagrams show how enabled ST-pins toggle when the toggle control register is set
to 0, meaning no falling TCK edges are ignored; when the toggle control register is set to 1, meaning
exactly 1 falling TCK edge is ignored; and when the toggle control register is set to C meaning C falling
TCK edges are ignored, where 1 < C ≤ 2N-1.
20
21
22
23
In these diagrams the TAP state name (abbreviated) is indicated along with TCK at the top. Then a “Count”
of the number of skipped TCK falling edges is shown. The Toggle_Clk signal is shown next which, on
falling edges, triggers transitions of enabled ST-pin drivers. The bottom trace shows the state of an enabled
ST-pin driver and when it changes.
NOTE—These rules produce transitions on enabled ST-pins that satisfy requirements specified by rule
5.4.1g), parts 1), 2) and 3).
TAP State
E1DR
UDR
RTI
RTI
RTI
RTI
0
0
0
0
SDRS
CDR
TCK
Count
0
0
0
Toggle-Clk
Toggle Driver
State
24
25
26
27
28
Initial State
Inverted
State
Initial
State
Inverted
State
Initial State
Figure 16 — Waveforms for delay count 0.
Figure 16 shows the case where the count of falling edges to ignore is 0. This results in enabled ST-pins
that change with frequency ½ TCK. In this example, the Run-Test/Idle TAP state was entered an even
number of times, so upon exiting that state, the toggling driver had returned to its initial state. If RunTest/Idle had been entered an odd number of times, the final driver state would be inverted.
31
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TAP State
E1DR
UDR
RTI
RTI
RTI
RTI
RTI
RTI
0
1
0
1
0
0
SDRS
CDR
TCK
Count
0
Toggle_Clk
Toggle Driver
State
1
2
3
4
Inverted State
Initial State
Initial State
Inverted State
Figure 17 — Waveforms for delay count 1.
Figure 17 shows the case where the count of falling edges to ignore is 1. This results in enabled ST-pins
that change with frequency ¼ TCK. In this example, the driver was left in its inverted state after three
transitions.
TAP State
E1DR
UDR
RTI
RTI
RTI
0
1
2
RTI
RTI
RTI
RTI
SDRS
CDR
TCK
Count
0
C-2
C-1
C
0
0
Toggle_Clk
Toggle Driver
State
Initial State
Inverted State
Inverted State
Initial State
Figure 18 — Waveforms for delay count C, where 1 < C ≤ 2N-1.
5
6
7
Figure 18 shows the case where the count of falling edges to ignore is C. Now C falling TCK edges are
ignored between ST-pin transitions.
8
9
10
11
With proper initialization of the toggle control register and choice of the number of TCK cycles spent in the
Run-Test/Idle state, this system can produce a step function, an impulse function with a width of C+1 TCK
cycles, or a specific frequency divided down from that of TCK, within the frequency resolution determined
by the choice of FMax and N. (See 7.4.)
12
13
[Editor’s note: No implementation example is given. Do we want to provide one, a’la my email of
6/23/2009 that showed up up-counter with equality checker?]
14
7. The Toggle Control register
15
16
17
18
A mandatory, toggle control register is provided as a target for the mandatory TOGGLE_SETUP
instruction (see 5.3). This register is used to control the behavior of the SELECTIVE_TOGGLE instruction
as described in 6.4. This register is required in addition to those registers (bypass, boundary-scan, and
optionally, the device identification register) prescribed by IEEE Std 1149.1.
19
[Editor’s note: The only control function now specified is the TCK delay counter.]
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1
7.1 Rules
2
3
4
5
6
a)
A data register named “toggle control” containing N bits (with N > 0) shall be provided.
b)
The toggle control register shall load each bit with a ‘1’ on the rising edge of TCK in the Capture-DR
TAP controller state.
c)
The toggle control register shall shift bits from TDI to TDO on rising edges of TCK in the Shift-DR
TAP controller state, when the TOGGLE_SETUP instruction is in effect.
7
NOTE— The TOGGLE_SETUP instruction is described in 5.3.
8
9
10
d)
11
12
13
NOTE— This integer, between 0 and 2N-1, is loaded into delay counter after the issuance of each ST-pin toggle and
thus governs the delay (in TCK cycles) between all transition events when the SELECTIVE_TOGGLE instruction is in
effect.
14
15
16
e)
17
NOTE— The equation expressing this is:
18
7.2 Permissions
19
20
a)
21
7.3 Recommendations
22
a)
23
7.4 Description
24
25
26
27
28
29
30
31
32
The toggle control register contains N bits placed between TDI and TDO when the TOGGLE_SETUP
instruction is in effect. This register captures a deterministic pattern (all ones) when passing through the
Capture-DR TAP controller state. These bits come out upon shifting in the Shift-DR TAP controller state,
while an N-bit integer is being placed in the toggle control register. This integer is then used as an upper
limit for a counter used to determine the number of falling TCK edges that are ignored until the next
transition event on currently selected ST-pins governed by the SELECTIVE_TOGGLE instruction. The allone pattern can be observed on TDO during shifting to verify the existence of the toggle control register,
and it also serves as a default divider (2N-1) if shifting is skipped by passing around the Shift-DR state by
route of the Exit1-DR to Update-DR states. Details of the TCK divider are found in 6.4.
33
34
35
36
37
38
When a chain of devices must be used during a test, some devices may not be used for toggling signals (or
may not support the features of this standard). In this case, those devices will not have a toggle control
register set up during the test and would typically remain in BYPASS mode. Those devices that do need to
have the toggle control register set to specific patterns would capture the all-one pattern upon passing the
Capture-DR tap control state while those in BYPASS would capture ‘0’ bits. This allows a test algorithm
an opportunity to validate that the chained instruction registers are operating properly.
The toggle control register content shall be used to specify the delay between successive transition
events on enabled ST-pins when the SELECTIVE_TOGGLE instruction is in effect and when the
TAP is in the Run-Test/Idle state.
The value of N shall be an integer greater than or equal to the base-2 logarithm of the quotient of FMax
divided by 8000, where FMax is the maximum TCK frequency (in hertz) supported by the design of the
device.
N = ⎡log 2 ( FMax / 8000) ⎤
The parallel hold portion of the toggle control register (if implemented) may be utilized in the design
of the delay counter circuitry provided in section 6.4.
The maximum TCK frequency (FMax) of the device should be greater than 1 megahertz.
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1
2
3
A test algorithm which sets a given TCK clock rate will then calculate a count integer that will achieve the
relatively longer time delay between transition events needed to satisfy the requirements of the capacitance
measurement system. The frequency F of pin toggling based on a divider integer C, where 0 ≤ C ≤ 2N-1, is:
4
F = TCK / (2*(C + 1))
5
6
7
8
9
10
11
12
13
14
Rule 7.1e) assures that a toggling pin can achieve a frequency as low as 8 kilohertz from a TCK running at
the rated maximum for the device. The 8 kilohertz number is a legacy of capacitive opens testing metrology
systems that use 8 kilohertz stimulus sources. Recommendation 7.2a) gives a lower limit for TCK
frequency that could achieve an 8 kilohertz toggle rate at an ST-pin. At the low limit of 1 MHz, the count
would need to be 61 (requiring N = 6) and the toggle frequency achieved would be 8065 Hz. A count of 62
would produce a toggle frequency of 7937 Hz. The value of each count at this TCK rate is 128 hertz. For a
maximum TCK frequency of 20 MHz, a count of 1249 (requiring N = 11) would produce a toggle
frequency of exactly 8000 hertz, and a count of 1250 would produce 7994 hertz. The value of each count at
this TCK rate is 6 hertz. In general, for a given TCK and count C, the frequency resolution of one count
increment is (in hertz):
15
ΔFC, C+1 = TCK / (2C2 + 6C + 4)
16
Note for low values of C, the frequency resolution of each count may be quite large.
17
8. Conformance and documentation requirements
18
8.1 Conformance
19
8.1.1 Rules
20
a)
21
NOTE 1—Due to rule 5.1.1a), this also implies conformance with the rules set out in IEEE Std 1149.1.
22
23
24
NOTE 2—If compliance enable pins are present, the enabled state indicates compliance to all requirements of both
IEEE Std 1149.1 and this specification. See IEEE Std 1149.1-2001, section 4.8, Subordination of this standard within a
higher-level test strategy.
25
8.1.2 Description
26
27
28
Conformance to the rules set out herein and in IEEE Std 1149.1 is essential for testing boards and other
assemblies containing interconnections, allowing manufacturing defects such as shorted or open solder
joints to be found and repaired before shipment. Conformance allows:
A component conforming to this standard shall comply with all rules provided herein.
29
30
•
IC vendors to provide testability features in a standardized way, so that each new IC design
does not need new engineering investment to provide testability.
31
32
•
makers of Automatic Test Equipment to develop and continually refine standardized tools for
the automation of test development, test execution, and diagnosis of failures.
33
34
35
•
end-users to develop test methodologies in a way that is both standard and in line with a
strategic direction, making full use of the automation provided by tools, to allow them to
produce very large and complex boards and systems more rapidly and efficiently.
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1
8.2 Documentation
2
3
4
Because adherence to this standard implies adherence to IEEE Std 1149.1, all devices conforming to this
standard shall have a description supplied in Boundary-Scan Description Language (BSDL) provided with
IEEE Std 1149.1.
5
8.2.1 Rules
6
a)
7
8
NOTE—See IEEE Std 1149.1 for a description of IEEE BSDL. The precursor to IEEE BSDL developed in 1990
cannot be used for documentation because it does not support the concept of “BSDL Extensions.”
A component conforming to this standard shall be documented with a BSDL description.
9
10
11
b)
12
13
14
15
NOTE— New BSDL syntax (contained within a “BSDL extension”) for describing concepts and structures introduced
by this standard are given in 8.4. A BSDL extension is a mechanism provided by IEEE Std 1149.1-2001 (see User
extensions to BSDL, B.8.17) which allows proprietary syntax to be provided that will allow tools to work that are
unaware of this syntax.
16
17
c)
18
19
NOTE—This includes boundary register cell ordering and the nominal values of analog parameters such as voltage
levels of output transitions.
20
21
22
23
d)
24
25
NOTE— In addition, the manufacturer would also specify typical electrical parameters for device pins, including TAP
signal voltage level requirements, and the power requirements of the device.
26
8.2.2 Description
27
<Fill in BSDL body detail here.>
28
8.3 BSDL package for Selective Toggle description (STD_1149_8_1_2009)
When the SELECTIVE_TOGGLE instruction is implemented in a component, then this instruction
shall have both the register relationship and optional provisions documented via the syntax provided
by BSDL and the BSDL extension provided by this standard.
Prime and second source devices shall have nominally identical implementations of publicly
accessible test circuitry, with the sole exception of the device identification code.
Other properties of a device shall be documented by the manufacturer, including:
1)
<property 1>
2)
<property 2>
3)
<property 3>
29
30
8.4 BSDL extension structure
31
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1
8.5 BSDL attribute definitions
2
3
8.6 Example BSDL
4
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IEEE P1149.8.1/D0.7, August 2009
1
Annex A
2
(informative)
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Unpowered Testing for Open Connections on Printed Circuit Assemblies
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A.1 Problem Description
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The problem space described here is that of finding defects in printed circuit assemblies. This type of
testing is referred to as “Loaded Board Test” and is typically the first type of testing performed on loaded
circuit boards after they come out of the attachment step (typically soldering). Loaded board test focuses on
finding “manufacturing defects”. One class of such defects results in open connections between board
signals and the intended connection points of various components. Another class is that of shorts (unwanted
connectivity) between pins.)
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There are several types of test approaches to discovering manufacturing defects such that remedial action
can be taken. Such actions include repair of the board, discarding the board, and process monitoring and
control. A common type of test used heavily across the industry is known as “In-Circuit Test” (ICT). It uses
a “bed-of-nails” access technology to provide access to board signals for test purposes. With ICT
equipment, there come a variety of testing tools that can be focused on finding the relevant defects that may
occur in manufacturing. These tools typically set up “stimulus experiments” that are monitored by other
ICT resources to judge whether any defects are present in the area of focus. Many such experiments are
used in concert to test an entire board of arbitrary complexity. The next subclauses describe one type of test
technology, invented over 15 years ago and known in industry as “TestJet3 ®”. This technology is
sometimes described generically as “unpowered capacitive opens detection”.
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A.2 Unpowered Capacitive Opens Detection
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Unpowered capacitive opens detection technology is aimed at finding open solder joints between printed
circuit assemblies (PCA) and devices mounted on the board. Considered here is one class4 of device:
connectors. A connector on a board is intended (ultimately) to mate with another connector on some other
assembly such as a plug-in daughter board, a memory or I/O card, etc. However, during manufacturing
board test, the connector is present, but the mating assembly is not present. Thus there are connections from
board signals to the vacant connector, but there is nothing active in the connector itself which can be used
for testing.
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One approach to testing this connector for opens between it and the board is to plug in a mating connector
that has additional wiring and/or other resources to support testing. The problem with this is one of
practicality, it takes time to plug in this mating connector, and if the board being tested has numerous
connectors, it can become time consuming and error-prone to do this. There are also maintenance issues
with these mating units. Thus this approach has limited viability.
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The heart of this problem of connector testing is that of sensing. Given access to the board’s nodes via the
bed-of-nails fixture, how can open solder joints between the connector and board be detected? The answer
is to sense whether signals on the board can get into the connector. The mating connector idea supports
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TestJet® is a registered trademark of Agilent Technologies. Any trademarks referenced in this document are the property of their
respective owners.
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Many other types of device are also testable with this technology, such as sockets, termination network packages, Integrated Circuits,
etc. This example is simple and illustrative, and represents a widespread problem across industry.
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this, but is not generally practical. Another is to think about an alternative way of sensing the presence of
these signals.
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The unpowered capacitive opens detection idea does this with capacitive sensing. A small signal sensor is
mounted over the open mouth of the connector, in close physical proximity, but not actually inserted into it
as shown in Figure A.1.
Signal
(to Tester)
(internal conductors)
Buffer
Sense
plate
Ball
Connections
Vacant Connector
Test access pad
In-Circuit
access
PC
Board
Tester AC Source stimulates
one pin, all others are grounded
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Figure A.1— BGA Connector and sense plate, with In-Circuit Test access to board signals.
The sense plate has a conductor that is thus hovering over the connector, and in close proximity to the
topmost tip of each connector pin, of which there may be hundreds. There is a small capacitive coupling
between this sense plate and the tip of each connector pin. The In-Circuit tester has access to each board
node that is attached (via solder) to the connector. It can then ground all but one of these pins and stimulate
one in particular with an AC signal. This AC signal couples into the sense plate with a magnitude
proportional to capacitance, where a local buffer amplifies the signal. This buffered signal is passed back to
the ICT system which measures the capacitance of the coupling. An equivalent circuit of this measurement
is shown in Figure A.2. The measured capacitance in the defect-free case is called CS and it can be
compared to a known-good expected value. In the earlier history of this measurement technology, typical
values of CS were greater than 100 femtofarads (fF). This was due to larger geometries of devices in the
past. With the relentless progress in miniaturization, these values may now be much lower, with many less
than 40 fF.
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Sense Plate
CS
Defect-Free Connection
Connector Pin
AC
Source
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Measured
Capacitance = CS
AC
Detector
Figure A.2— An equivalent circuit of a capacitance measurement in the defect-free case.
In the event of an open defect that disconnects the connector pin from the board, there is an equivalent
circuit seen in Figure A.3. Here there is a series of two capacitors, the original CS and a new one formed by
the board’s solder pad and the connector’s solder point, which is labeled CO. The series combination of
capacitances is lower in value than CS was by itself. It is not unusual to see defective pin measurement
values that are less than 5 fF. If CS for this measurement is 40 fF, then solving for CO gives about 6 fF of
open joint capacitance.
CS
Sense Plate
Connector Pin
Connector Lead
CO
Measured
Capacitance =
Solder Pad
CS CO
CS + CO
With Open Solder Defect
AC
Detector
AC
Source
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As long as the change in measured capacitance is greater than the measurement uncertainty in the detector,
open joints can be detected reliably.
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Some notes about the AC source are in order. It is typically a sinusoid, with no DC offset, with a magnitude
of 400 millivolts or less. This prevents current flow in other devices on the same board net that are
connected to it which may contain semiconductor junctions (typically ESD protection diodes), because a
voltage 200 millivolts above or below ground will not turn these on. The frequency of the source may be
relatively low, for example, around 8 kHz. Higher frequencies can begin to introduce other problems with
crosstalk coupling or attenuation in the bed-of-nails fixture.
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The original capacitive opens detection technique is an unpowered test technology, meaning it is used with
the board in an unpowered state. This also allows the connection of the other nodes to ground without fear
of shorting critical signals or power leads. This “guarding” of the other signals helps quiet the board for this
fairly sensitive measurement. Notice also that because of the bed-of-nails access, shorts between these
Figure A.3— An equivalent circuit of a capacitance measurement when the stimulated pin
is open.
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nodes are detectable by a “shorts test” that examines each node for independence from the others. This
important class of defects is usually detected in a different phase of testing and they are assumed to be
absent at the time of unpowered opens testing.
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It is important to note that there are additional defect coverage opportunities presented by capacitive opens
test. Figure A.4 shows a case where, due to the positioning of a tester nail, it is possible to detect several
open solder joints along the path between the nail and the sensed connector, and also if the resistor R is
present. The value of R is unlikely to interfere with the stimulus of the connector pin, unless it is a very
large resistance such as 10 Megohms or larger. On typical boards, it would likely be a series termination
resistor with a value of 50 to 100 ohms.
Sense Plate
Soldered Connections
Connector
R
Board
Test Pad
Printed Trace
Tester Nail
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Figure A.4—Three solder joints and the presence of resistor R are tested.
The sense plate is typically an inexpensive piece of simple, two-sided printed circuit board stock, cut to fit
the general outline of the device being sensed. The top side is where a buffer amplifier is mounted, and is
also a ground plane. The bottom side is positioned over the device being sensed and its conductive plate
forms the top half of the sensed capacitance. An example of a sense plate/buffer assembly is shown in
Figure A.5.
Buffer Amplifier
Sense Plate
Spring-loaded Supports
(Side View)
(Top View)
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Figure A.5—Top and side views of a sense plate and buffer amplifier.
Often, a device to be sensed is visible on the top side of a board. The sense plate/buffer assembly is
suspended over the target device by the two spring-loaded supports attached to the top portion of the test
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fixture. As this portion is lowered into position the spring-loaded supports compress slightly as the sense
plate comes into position over the target device. Figure A.6 shows an example of a sense plate/buffer
assembly inside a fixture, contacting a target device. The two spring-loaded supports also supply power and
retrieve sense information from the buffer/amplifier.
Mounting block
in top cover
Buffer
Sense Plate
Spring posts
DUT
Board under test
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If the target device is located on the bottom of the board, then the sense plate is mounted in a milled recess
in the test fixture board support platen.
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A.3 Replacing Tester AC Stimulus with Boundary-Scan Stimulus
Figure A.6—A sense plate/buffer assembly inside a fixture in testing position.
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As noted in clause 4, it is increasingly difficult to gain electrical access to test points on a board to be
tested. Capacitive opens test is a “forgiving” technology in that (unlike some other test technologies) the
loss of some test point access causes a linear degradation in defect coverage for opens. However, as access
becomes increasingly difficult, the loss of coverage for opens has become a major concern.
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The question becomes how to substitute a “limited access” technology for the bed-of-nails and use it to
perform guarding and stimulation needed for the capacitive technique. The answer is that IEEE 1149.1
Boundary-Scan can be used for this. Boundary-Scan drivers under the control of the EXTEST instruction
can be used to hold most nodes steady while stimulating just one. This differs from conventional capacitive
opens testing in certain ways: first, the native drive levels of a driver are being used which may be more or
less than the 200 millivolts used in the past. Second, those signals doing “guard” functions are not all
grounded as in the past, but held to some logic value which is not necessarily ground (0 volts). Experiments
have shown these differences are not problematic. The measurement system is AC coupled at the sense
plate, so grounded guards are not important; they just need to be held constant. (There is negligible current
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flow in the guarded pins.) The act of guarding can be done with either high or low logic values, and since
signals are not being connected together by relays, they can have different states. Since the power is applied
when using Boundary-Scan, conventional guarding with relays would not be possible anyway due to that
shorting many active signals together. The change in stimulus signal strength can also be accommodated.
The final big difference is that power must be applied to the board such that the Boundary-Scan facilities
become active. Thus extraneous signals may be present that may add noise into the capacitve
measurements.
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The fact that access have been lost, but replaced with Boundary-Scan capability, means that shorts between
inaccessible nodes that are both driven and observed by Boundary-Scan can still be detected.
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A capacitive opens test implementation that uses Boundary-Scan stimulation has been demonstrated in a
commercial ICT system, testing real production boards. However, there are some issues that can cause loss
of defect coverage.
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A.4 Coverage Deficiencies
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In Figure A.7 there is a Boundary-Scan IC (U1) that is connected to the pins of a connector, but not all
Boundary-Scan pins are equivalent. Some of U1’s pins have drivers and can be used (when EXTEST is in
effect) to support capacitive opens measurements. However, some of U1’s pins are only capable of
receiving signals and thus cannot either guard (hold the associated signal at a fixed potential) or stimulate
their associated signals. Opens on these signals will not be covered by capacitive opens test based on
Boundary-Scan resources in U1. Shorts between these signals are also not detectable by conventional
Boundary-Scan tests since their states are not controllable.
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A second problem arises when a Boundary Register cell supplies data to a differential driver, rather than a
single-ended driver. This will mean that two, logically complementary signals are driven to the connector.
When one goes from low-to-high, the other signal will move high-to-low in (near) perfect symmetry. This
means there are canceling signals at the sense plate and, the sense plate buffer sees no signal at all in the
defect-free case. If one pin is open, there will no longer be signal cancellation at the sense plate and the
defect can be seen. However, there are other defects (for example, both pins being open) that cannot be
seen. In general it is not a good testing practice to have the lack of signal indicate a passing result.
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Finally, to emulate an AC stimulus frequency, for example, 8 kHz, it is necessary to update the content of
the Boundary Register rapidly enough (with EXTEST in effect) to cause a given pin to move at this
frequency. But, the number of (combined) Boundary Register cells in the chain of devices that must be
shifted will effectively form a frequency divider on TCK. If this divider ratio is high, there may be practical
problems creating the target stimulus frequency. This could prevent the technique from being applicable at
all in some cases.
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TMS
TCK
TDI
TDO
TDI
TCK TMS
TDO
BScan Device U1
Bscan Driven
Bscan Observed
Vacant
Connector
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Figure A.7— A Boundary-Scan device that drives and observes signals that go to a
connector.
It is the mission of this standard to provide solutions for these problems, such that maximum coverage is
achievable in practice. This will allow the retention of significant test coverage as electrical access with
conventional bed-of-nails declines.
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