A novel track and hold circuit with offset and gain calibration
Can Zhu*1, Rongbin Hu1, Lei Zhang2, Yonglu Wang1, Zhengping Zhang2, Rongke Ye2, and Yuhan Gao2
1
Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, China, zhu_can@163.com,
hurongbin2000@126.com, wangyonglu@126.com
2
No.24 Research Institute, China Electronics Technology Group Corporation, Chongqing 400060, China,
zhangzhengping@126.com, yerongke@126.com, gaoyuhan@126.com
Abstract
A novel track and hold circuit in 0.18μm SiGe BiCMOS process is presented, whose offset and gain can be
digitally calibrated, and which can be used in a time-interleaved ADC to improve its performances. The simulated
results show that the proposed track and hold circuit can sample a signal at a rate of 1.25GHz, while consuming just
50mW. The offset calibration can get a range of 26.6mW with a step of 0.1mW, while the gain calibration gets a range
of 33.28dB with a step of 0.13dB.
1. Introduction
As the development of the digital circuit, more and more information can be processed digitally, but the real
word is analog, so an ADC (analog to digital converter) is still needed to convert the analog signals to digital signals for
digital processing [1-4]. As the digital processing speed achieves gigahertz, faster ADCs are needed. There are several
ways to design ultra-fast ADCs, but the interleaved sampling technique is the best one. In an interleaved ADC, several
ADCs sample a single analog signal alternately by a fixed time interval. In order to achieve higher performances, the
channels of an interleaved ADC must match each other excellently. But current integrated circuit manufacture process
has many unstable factors, so the channels can’t match each other as needed when the circuits are manufactured. For
this kind of problem, someone proposed to digitally calibrate each channel to obtain matching. Some of the main
calibrating objects are the gain and offset of every sub-ADC channel, which can be accomplished by calibrating the
track and hold circuit [5-6] in front of each sub-ADC. In this paper, a novel track and hold circuit is presented, whose
offset and gain can be digitally calibrated, and which can be used in a interleaved ADC to improve its performances.
2. Structure
As shown in figure 1, it is the structure of the proposed track and hold circuit, which consists of a emitter
degenerate differential amplifier 101, another differential pair 102 used for offset calibration, a output driver 103, a pair
of input buffers 108 and 109, a pair of two-stage switches 110 and 111, a pair of filtering resistors 112 and 113, a pair of
sampling capacitors 114 and 115, and another pair of buffers 116 and 117. The whole circuit is symmetrical or full
differential.
Figure 1 the structure of the proposed track and hold circuit
978-1-4673-5225-3/14/$31.00 ©2014 IEEE
The buffers 108 and 109, 116 and 117 have a gain of one, and so does the output drivers 103. Consequently, the
whole gain of the track and hold circuit is decided by the full differential amplifier 101. So the gain is
G 
g m Rc
,
1  g m Re
(1)
where Rc is the resistance of the resistors R1 and R2, whose values are the same, Re is the resistance of the resistors R3
and R4, whose values are the same too, and gm is transconductance of NPN transistor N1 and N2, which are designed to
be identical. Furthermore, according to semiconductor transistor physics, we get
gm 
Ic
I
 tail ,
VT 2VT
(2)
where Ic is the collector current of NPN transistor N1 or N2, VT is a physical constant which is equal to 26mV at the
room temperature, and Itail is the tail current of the differential amplifier. Combining (1) and (2), we get
G
I tail Rc
,
2VT  I tail Re
(3)
so the gain can be adjusted by changing the tail current, which can be accomplished by a current-type DAC1 as shown
in figure 1, and the current source 131 is used as a constant bias.
When there is no offset calibration, the current DAC2 is shut off and no current passes through NPN differential
pair of N3 and N4. When the offset calibration is initiated, the output offset voltage is calculated as
(VOUTP  VOUTN ) offset   I DAC 2 Rc ,
(4)
where VOUTP is the positive output terminal, VOUTN is the negative output terminal, (VOUTP-VOUTN)offset is the
differential output of the track and hold circuit when the differential input is zero, and IDAC2 is output current of DAC2.
According (4), we find that the offset of the track and hold circuit can be modulated through DAC2, which can be
controlled by digital codes.
3. The two-stage sampling switches
As shown figure 1, the pair of two-stage switches 110 and 111 is used to combine with sampling capacitors 114
and 115 to realize the tracking and holding function. The small filtering resistors 112 and 113 are used to filter the
glitches generated in the sampling process. Because of the two-stage switches, better isolation between the incoming
signals and the sampled signals on the sampling capacitors is achieved. The circuit of the two-stage sampling switches
with the sampling capacitors and the input butters are shown in figure 2.
Figure 2 the two-stage switches with input buffer and sampling capacitor
As shown in figure 2, the circuit consists of input buffer 231, the first current switch 212, the second current
switch 232, the diode-connected bipolar transistor 233, the PMOS transistor 234, the driving transistor 213, the
saturation-protecting circuit 235, the filtering resistor 112 and the sampling capacitor 214. The inpurt buffer 108, the
filtering resistor 112 and the sampling capacitor 214 are the same elements as that shown in figure 1. The saturationprotecting circuit 235 is used to prevent the NPN transisotr 242 from getting into the saturated state, which will slow
down the whole circuit badly. The clock signals are full differential, the positive terminal of which is CLK+ and the
negative is CLK-.
4. The calibration DAC
As shown in figure 1, the current-type DACs are used to calibrate the offset and gain of the track and hold circuit.
In order to obtain high resolution, two current-type DACs are cascaded to form one single DAC. The two DACs are
connected by a 2:1 current mirror. So, as shown in figure 3, it consists of three parts: the first DAC including 373, 374,
375, and 376, the current mirror 371, and the second DAC. The two DACs have the same structure but different scales.
Figure 3 the current-type DAC used for calibration
The first DAC uses an R-2R network 374 combined with a transistor set 375 to get scaled current, a switch set
376 is used to switch the scaled currents between the Vcc and Iout lines. The input bias network 373 receives the
reference current 310 and transfers it proportionally to every branch of the DAC.
5. Simulation
A popular 0.18μm SiGe BiCMOS process PDK (process design kid) is used to construct and simulate the
proposed track and hold. In order to evaluate the linearity of the circuit, we input a sin wave and calculate the DFT at
the output. Then the spectrum shown in figure 4 is got. Further simulation shows that the proposed track and hold
circuit has performances summarized in table 1.
Figure 4 the spectrum of the proposed track and hold circuit
Table 1 summary of the proposed track and hold circuit
process
0.18μm SiGe BiCMOS
Power supply
3.3V
Sampling rate
SNR
1.25Gsps
45dBc
SFDR
Power consumption
60dB
50mW
Offset calibration step
0.1mV
Offset calibration range
26.6mV
Offset calibration step
0.13dB
Gain calibration
33.28dB
6. Conclusion
A novel track and hold circuit in 0.18μm SiGe BiCMOS process is presented, whose offset and gain can be
digitally calibrated, and which can be used in a interleaved ADC to improve its performances. The simulated results
show that the proposed track and hold circuit can sample a signal at a rate of 1.25GHz, while consuming just 50mW.
The offset calibration can get a range of 26.6mW with a step of 0.1mW, while the gain calibration gets a range of
33.28dB with a step of 0.13dB.
7. Acknowledgments
This work was financially supported by the national key laboratory foundation (9140C090104120C09032). The
research work was done at Analog Integrated Circuit Laboratory on Science and Technology. The CAD tools and
instruments of the laboratory helped the authors a lot. The authors thank RuZhang Li, Guangbin Chen, Yuxin Wang,
Dongbin Hu, and other members of Analog Integrated Circuit Laboratory on Science and Technology.
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