16.7
A 120GHz 10Gb/s Phase-Modulating Transmitter in
65nm LP CMOS
Noël Deferm, Patrick Reynaert
KU Leuven, Leuven, Belgium
This paper presents a 120GHz fully integrated 65nm low power (LP) CMOS
transmitter which achieves data rates above 10Gb/s. At these high frequencies
an extremely high bandwidth is available. This allows multi gigabit per second
communication which provides an answer to the ever increasing demand for
higher data rates in wireless systems. However, wideband modulation of a
120GHz signal in 65nm LP CMOS is a challenge.
To achieve a high data rate at these high frequencies, a straightforward and
high speed phase modulator architecture is implemented. Figure 16.7.1 shows
the complete schematic of the transmitter. The LO input signal is first buffered
by a 2-stage buffer amplifier. The phase generation is done by a novel
differential branch line coupler that generates two differential quadrature
signals. These 2 signals are fed into two 6-stage driver amplifiers. By means of
differential splitters, each signal is split in an in-phase and an inverted signal.
This results in 4 differential signals with relative phases of 0, 90, 180 and 270
degrees, allowing phase modulation. The actual modulation is carried out by a
4-to-1 analog multiplexer which selects the generated 120GHz phases
depending on the modulation scheme. The high-speed MUX is directly driven
by digital signals and takes over the function of a conventional DAC and
upconverter. The output of the MUX is buffered and fed into a 9-stage
differential PA.
The novel differential branchline coupler that generates the four phases, is
based on a single ended branchline coupler. A 120GHz on chip signal has a
wavelength of about 1.2mm. Conventional branchline couplers have a width
and length of about Ȝ/4, which is thus about 300µm. The use of slow-wave
transmission lines, which have a higher artificial relative permittivity, resulting in
lower phase velocity and shorter wavelengths, leads to a very compact design.
The differential branchline coupler consumes an area of 140µm by 180µm
which is almost 4 times less than a conventional branchline coupler. The 50ȍ
differential lines of the coupler are designed in the top metal layers and only
have a bottom shield. A branchline coupler also needs a transmission line with
a value of 50ȍ/¥2. To implement this 35ȍ differential slow-wave line, an extra
top shield is added. The use of a differential structure results in a less
complicated and more compact slow-wave line than the single ended version.
On top of that, the inverted signals are also available. The measured phases
that are generated by this transmitter are shown in figure 16.7.3.
The analog multiplexer consists of 4 differential pairs which can be switched on
or off by their tail current source (See figure 16.7.2). The tail current source is
directly driven by a buffered differential digital signal. If two quadrature phase
channels are switched on together, an additional 45° interpolated phase can be
realized, resulting in an 8-point QAM constellation. The AM of this signal can be
removed by pushing the PA into saturation, which also improves the overall
power efficiency of the system. This will result in an 8PSK modulation scheme.
Because of measurement setup limitations, the PA couldn’’t be driven into
saturation and only QPSK and 8QAM constellation were measured. The
impedance matching circuits between the switches and the drivers are realized
with differential transmission lines. Series matching circuits, which are needed
to connect active devices over long distance, are build with high characteristic
impedance transmission lines. The parallel stubs are a combination of high Zc
lines and slow-wave lines. This results in a length of 100µm, which is 3 times
shorter than a conventional 300µm Ȝ/4 stub. The complete area of the
multiplexer is 700µm by 650µm. The two 6-stage driver chains between the
branchline coupler and the MUX consume twice an area of 350µm by 150µm.
After the multiplexer, the signal is amplified by the differential power amplifier.
Simulations point out that the Gmax at 120GHz of a pseudo differential pair
after gate-drain capacitive neutralization is about 6dB for small devices
(W=8µm) and 5dB for larger devices (W=20µm). The loss in the differential
parallel matching stubs is about 2.5 to 3dB, depending on the size of the
transistors to match to. When a gain of 20dB is desired this means that about 9
stages are needed. The 3dB bandwidth of the PA is 8GHz. The use of short
parallel transmission line stubs with high characteristic impedance results in a
very compact design. The 9-stage PA only consumes an area of about 550µm
by 300µm.
Both input and output GSG probepads are single ended. The single ended
signals are converted to differential signals by creating a high impedance
common mode ground return path. In this way baluns, which are lossy and
consume a lot of area, are not needed [5]. This technique is also used between
the different stages in the amplifiers to overcome common mode stability
problems.
Different measurement setups were used to measure the complete behavior of
the transmitter. The generation of the LO was done with an F-band source
module. Signals were brought on chip via 50µm pitch GSG Picoprobes.
Downconversion of the QPSK or 8QAM modulated 120GHz output signal was
done with an external F-band mixer. The IF output signal of the mixer was fed
into a high-speed oscilloscope to visualize the waveforms and to demodulate
the output signal.
Figures 16.7.4 and 16.7.5 show the measured constellations, spectra and
waveforms for different modulation schemes and data rates. For QPSK
modulation, the results for a 4Gb/s and a 10Gb/s data rate are shown. The
results for 8QAM modulation are also shown and this for a data rate of 6Gb/s.
Higher data rates are impeded by the limited bandwidth of the downconversion
mixer and oscilloscope, resulting in a reduced demodulation performance.
The measured output power at 118GHz was -6.5dBm. The generator that was
used to create the LO has a limited output power and as a result the saturated
output power of the PA could not be reached. Simulations reveal a saturated
output power higher than 0dBm over a frequency range of more than 8 GHz,
centered around 118GHz.
Figure 16.7.6 gives a summary of the results and a comparison with other mmwave transmitters. Compared to other mm-wave transmitters it has the highest
carrier frequency and the lowest supply voltage. By using the on-chip
differential branchline coupler and high-speed multiplexer, the presented
architecture enables multi gigabit per second data rates at 120GHz.
Furthermore, the architecture allows for both QPSK and 8QAM. The transmitter
consumes an area of about 1875µm by 940µm (See figure 16.7.7), operates
from a 1V supply and consumes 200mW.
Acknowledgements:
The authors would like to thank NXP research Eindhoven to support this work.
The IWT Flanders is acknowledged for their financial support. Rhode &
Schwarz is also acknowledged for supporting the measurement setup.
References:
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Solution,”” ISSCC Dig. Tech. Papers, pp. 414-415, Feb. 2010.
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65nm CMOS Transmitter Front-End with 8GHz IF Bandwidth and 20dB IRRatio,”” ISSCC Dig. Tech. Papers, pp. 418-419, Feb. 2010.
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Figure 16.7.1: Circuit diagram of the 120GHz transmitter.
Figure 16.7.2: Circuit diagram of one multiplexer driver and switch.
Figure 16.7.3: Measurement of the 4 generated phases vs. frequency.
Figure 16.7.4: Measurement of 4Gb/s QPSK constellation, spectrum and
modulated IF signal.
Figure 16.7.5: Constellation and spectrum of the modulated IF signal for
10Gb/s QPSK and 6Gb/s 8QAM.
Figure 16.7.6: Comparison with other work.