1
Chapter 8
Differential
and
Multistage
Amplifiers
EE 3120 Microelectronics II
Suketu Naik
Operational Amplifier Circuit Components
2
1. Ch 7: Current Mirrors and Biasing
2. Ch 9: Frequency Response
3. Ch 8: Active-Loaded Differential Pair
4. Ch 10: Feedback
5. Ch 11: Output Stages
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Active-Loaded Differential Pair
3
Two Stage
Op Amp
(MOSFET)
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4
Learning Objectives
1) MOS and the bipolar differential amplifiers: how
they reject common-mode noise or interference and
amplify differential signals
2) The analysis and design of MOS and BJT differential
amplifiers: utilizing passive resistive loads, currentsource loads, and cascodes
3) The structure, analysis, and design of amplifiers
composed of two or more stages in cascade
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Why Differential?
5
0) What is a differential signal?
1) Differential circuits are less sensitive to noise and
interference
2) Differential configuration enables biasing the amplifier and
coupling of amplifier stages without bypass and coupling
capacitors
3) Useful in IC design because of good matching between the
transistors
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6
MOS Differential Pair
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8.1. The MOS Differential Pair
7
Differential Pair
 Two matched transistors
(Q1 and Q2) joined and
biased by a constant current
source I
 FETs should not enter
triode region
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8
Input Common Mode Range
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8.1.1. Operation with a Common-Mode Input Voltage
9
 Suppose that two gate
terminals are joined
together and connected to
a common-mode voltage
(VCM)
 vG1 = vG2 = VCM
 Q1 and Q2 are matched
 Current I will divide
equally between the two
transistors.
 ID1 = ID2 = I/2,
 VS = VCM – VGS; where
VGS is the gate-tosource voltage.
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8.1.1. Operation with a Common-Mode Input Voltage
10
 Equations (8.2) through (8.8)
describe this circuit (channel- (8.2) I  1 kn W VGS  Vt 2
2 2 L
length modulation is neglected)
 Note the range (max and min) (8.3) VOV  VGS  Vt
of input common-mode voltage
I 1 W 2
(8.4)  kn VOV
(VCM): beyond this range the
2 2 L
diff pair leaves saturation
(8.5) VOV
I W

kn L
(8.6) vD1  vD2
I
 VDD  RD
2
I
(8.7) max VCM   Vt  VDD  RD
2
(8.8) min VCM   VSS  VCS  Vt  VOV
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8.1.2. Operation with a Differential Input Voltage
11
 vid is applied to Q1 and Q2
is grounded:
 vid = vGS1 – vGS2 > 0
 iD1 > iD2
 The opposite applies if Q1
is grounded
 The differential pair
responds to a differencemode or differential
input signals.
 The diff pair provides
corresponding
differential output signal
between the two drains
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12
Differential Input Voltage
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13
8.1.2. Operation with a Differential Input Voltage
 Two input terminals
connected to a differntial
signal vid
 Bias current I of a perfectly
symmetrical differential pair
divides equally
 To steer the current
completely to one side of the
pair, a difference input voltage
vid of at least √2VOV is needed.
1 W 
2
(8.9) I   kn   vGS 1  Vt 
2 L 
(8.9) vGS 1  Vt  2I / kn W / L 
(8.9) vGS 1  Vt  2VOV
(8.10) max  vid   VGS 1  v S
(8.10) max  vid   2VOV
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14
Large Signal Operation
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8.1.3 Large-Signal Operation
 Objective: derive
expressions for drain
current iD1 and iD2 in
terms of differential
signal vid = vG1 – vG2
15
 Assumptions:
 Perfectly matched
transistors
 Channel-length
modulation is
neglected
 Load independence
is present
 Saturation region
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16
8.1.3 Large-Signal Operation
 Step #1: Expression drain
currents for Q1 and Q2.
 Step #2: Take the square roots
of both sides of both (8.11)
and (8.12)
 Step #3: Subtract (8.14) from
(8.15) and perform appropriate
substitution.
 Step #4: Note the constantcurrent bias constraint.
1 W
2

(8.11) iD1  kn  vGS 1  Vt 
2 L
1 W
2

(8.12) iD 2  kn  vGS 2  Vt 
2 L

(8.13) iD1
1 W

kn  vGS 1  Vt 
2 L
1 W
(8.14) iD2 
kn  vGS 2  Vt 
2 L

(8.15) vGS 1  vGS 2  vG 1  vG 2  vid
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8.1.3 Large-Signal Operation
 Step #5: Simplify
(8.15).
 Step #6: Incorporate
the constant-current
bias.
 Step #7: Solve (8.16)
and (8.17) for the two
unknowns – iD1 and iD2.
17
(8.17) iD1  iD 2  I

1 W 2
(8.17) 2 iD1 iD 2  I  kn vid
2 L

I  I
(8.23) iD1   
2  VOV
(8.24) iD2
I  I
 
2  VOV
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  vid 
 vid /2 
  1  

 2 
 VOV 
2
  vid 
 vid /2 
  1  

2
V
 
 OV 
2
Suketu Naik
8.1.3 Large-Signal Operation
small-signal approximation
 Transfer characteristics of (8.23)
I  I  vid
and (8.24) are nonlinear.
(8.25) iD1   

2
V
 OV  2
 Linear amplification is desirable
and vid will be as small as possible.
I  I  vid
(8.26) iD2   

2
V
 For a given value of VOV, the only
 OV  2
option is to keep vid/2 much
 I  vid
(8.27) id  

smaller than VOV.
 VOV  2
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Suketu Naik
8.1.3 Large-Signal Operation
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Figure 8.7: The linear range of operation of the MOS differential pair can be extended
by operating the transistor at a higher value of VOV .
 VOV increases (smaller W/L): Gain will decrease, Linearity will increase
 VOV decreases (larger W/L): Gain will increase, Linearity will decrease
 Can increase the bias current to increase gm and gain
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20
Small-signal Operation
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8.2 Small-Signal Operation of the MOS Differential Pair
Virtual ground at the source
- Elimintates need for large
bypass capacitor
21
VCM = bias voltage at the gate
vid = differential small signal
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8.2.1 Differential Gain
 For MOS pair, each device
operates with drain current
I/2 and corresponding
overdrive voltage (VOV).
 gm = I/VOV
 ro = |VA|/(I/2).
22
1
(8.28) vG1  VCM  vid
2
1
(8.29) vG 2  VCM  vid
2

2ID 2(I /2)
I
(8.30) gm 


VOV
VOV
VOV

vid
(8.31) vo1  gm RD
2
v
(8.32) vo2  gm id RD
2

vod
(8.35) Ad 
 gm RD
vid
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8.2.1 Differential Gain
23
 vi1 = VCM + vid/2 and vi2 =
VCM – vid/2 causes a virtual
signal ground to appear on
the common-source
(common-emitter)
connection
 Current in Q1 increases by
gmvid/2 and the current in
Q2 decreases by gmvid/2
 Voltage amplitudes of
gm(RD||ro)vid/2 develop at the
two drains
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8.2.2. The Differential Half-Circuit
24
 Figure 8.9 (right): The
equivalent differential halfcircuit of the differential
amplifier of Figure 8.8
 Here Q1 is biased at I/2 and
is operating at VOV
 This circuit may be used to
determine the differential
voltage gain of the
differential amplifier Ad =
vod/vid.
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8.2.3 The Differential Amplifier with Current-Source Loads
25
 To obtain higher gain, the passive resistances (RD) can be
replaced with current sources.
 Ad = gm1(ro1||ro3)
Figure 8.11: (a) Differential amplifier
with current-source loads formed by
Q3 and Q4. (b) Differential half-circuit
of the amplifier in (a).
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8.2.4 Cascode Differential Amplifier
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 Gain can be
increased via
cascode
configuration –
discussed in Section
7.3
 Ad = gm1(Ron||Rop)
 Ron = (gm3ro3)ro1
 Rop = (gm5ro5)ro7
Figure 8.12: (a) Cascode differential
amplifier; and (b) its differential half
circuit.
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27
Common Mode Rejection Ratio (CMRR)
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8.2.5 Common-Mode Gain and Common-Mode Rejection ratio (CMRR)
28
a) vin = VCM (DC common-mode signal) + vicm (common-mode noise
or interference)
b) current source with fininte output resistance RSS
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8.2.5 Common-Mode Gain and Common-Mode Rejection ratio (CMRR)
29
c) T model without ro
d) common-mode half circuit
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8.2.5 Common-Mode Gain and Common-Mode Rejection ratio (CMRR)
30
i
(8.41) vicm 
 2iRSS
gm

 Equation (8.43) describes
effect of common-mode
signal (vicm) on vo1 and
vo2.
vicm
(8.42) i 
1/ gm  2RSS

RD
(8.43) vo1  vo2  
vicm
1/ gm  2RSS

vicm RD
(8.44) vo1  vo2  
2RSS

(8.45) vod  vo2  vo1  0
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8.2.5 Common-Mode Gain and Common-Mode Rejection ratio (CMRR)
31
 When the output is taken singleRD
(8.46)
v


vicm
o1
ended, magnitude of common2RSS
mode gain is defined in (8.46) and
RD 's are
mismatched
(8.47)
RD  RD
(8.47) vo2  
vicm
 Taking the output differentially
2RSS
results in the perfectly matched
case, in zero A (infinite CMRR)                      
cm
 Mismatches between the drain
resistances make Acm finite even
when the output is taken
differentially.
RD
vicm
2RSS

(8.48) vod  vo2  vo1 
vod  RD  RD  RD 
(8.49) Acm 




vicm 2RSS  2RSS   RD 
 CMRR is the ratio of differential                      
gain over common-mode gain
Ad
(8.50) CMRR 
Acm
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32
8.4.1 Input Offset Voltage
Device mismatches cause a finite dc voltage at the output
Apply a small voltage of opposite polarity to cancel the offset
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33
BJT Differential Pair
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8.3 The BJT Differential Pair
34
 Figure 8.15 shows the basic
BJT differential-pair
configuration
 It is similar to the MOSFET
circuit – composed of two
matched transistors biased
by a constant-current source
– and is modeled by similar
expressions.
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8.3.1 Basic Operation
35
 Suppose that the two bases joined together and connected to a commonmode voltage VCM
 Since Q1 and Q2 are matched, and assuming an ideal bias current I with
infinite output resistance, this current will flow equally through both
transistors.
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36
Input Common Mode Range
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8.3.2 Input Common-Mode Range
37
 The allowable range of VCM
is determined at the upper
end by Q1 and Q2 leaving
the active mode and
entering saturation.
 Equations (8.66) and (8.67)
define the minimum and
maximum common-mode
input voltages.
I
(8.66) max VCM   VC  0.4  VCC   RC  0.4
2

(8.67) min VCM   VEE  VCS  VBE
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38
Large Signal Operation
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8.3.3 Large Signal Operation
39
(1) Note that the linear
range of BJT diff pair
is smaller than the
MOS diff pair
(2) It can be used for
fast switching (ECL
logic) by current
steering: e.g. current
flows entirely in one
branch then switches
to the other branch;
requires only 4VT
(3) The difference
input signal, vid should
be less than VT/2 to
linear amplification
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How to increase the linear range?
40
Figure 8.18 The transfer characteristics of the BJT differential pair (a) can be linearized (b)
(i.e., the linear range of operation can be extended) by including resistances in the emitters.
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41
Small Signal Operation
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8.3.4 Small Signal Operation
42
Bias voltage
(DC)
+ small
signal (ac)
IC
I
gm 

......(8.80)
VT 2VT
ic 
I vid
2VT
vid
vid
 gm
 ie  
....(8.83)
2
2
2re
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43
8.3.4 Small Signal Operation: half-circuit
Virtual
Ground
Ad  gm ( RC || ro )......(8.95)
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8.3.4 Small Signal Operation: single-ended input
44
(1) Emitter voltage is no longer at virtual
ground.
(2) Voltage at the emitters is appx.
Vid /2
Note that we can apply
signal in the MOS diff
pair in similar fashion
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8.3.5 Common-mode gain and CMRR
45
 RC  RC 
......(8.98), (8.99)

Acm  
 
2 REE  re
 2 REE  RC 
Ad
 R 
CMRR 
 2 g m REE   C  ......(8.100)
Acm
 RC 
RC
CMRR is the ratio of differential gain over common-mode gain
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46
8.4.2 Input Offset Voltage
Device mismatches cause a finite dc voltage at the output
VOS smaller than
MOS diff pair
Apply a small voltage of opposite polarity to cancel the offset
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47
List of Problems
MOS Diff Pair
p8.2: input common mode range of PMOS differential amplifier
ex8.4 MOS diff pair: differential gain
ex8.7 (simulate and verify) MOS diff pair: CMRR
p8.15: design of MOS differential amplifier
BJT Diff Pair
p8.34: input common mode range of npn differential amplifier
ex8.13: BJT diff pair: differential gain, CMRR
p8.49 (simulate): design of BJT differential amplifier
p8.62 (simulation only): npn differential amplifier
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