Integrated VLSI Systems I
MNE 21
2101
Laboratory Assignments
(35 % Assessment)
Department of Microelectronics and Nanoelectronics
Faculty of ICT
University of Malta
Department of Microelectronics and Nanoelectronics
Assignment 1: Fundamental Concepts
Figure 1
MOSFET DATA (M1 & M2):
L = 0.9 µm
W = 20 µm
[1]
Determine the D.C. operating points (including VD, ID, VG, VGS, gm1,
gm2) for the above two circuits.
[2]
Suppose that W is increased by a factor of 2, determine the new
operating points.
[3]
(a)
Using W = 20 µm and W = 40 µm , obtain the magnitude and
phase Bode plots using a 1 V peak sinusoidal input. Using
these plots determine the mid-band gain and the low and
high –3 dB points.
(b)
Which circuit components affect the low –3 dB point and the
high –3 dB point?
(c)
Given that the small-signal gain of the circuit in Figure 1 is
given by −gm2R2. Using the D.C. analysis obtained in [1]
determine the small-signal gain of the amplifier and compare
it to the mid-band gain obtained using the frequency
response simulation.
(d)
From the phase/frequency plot how can you determine that
the amplifier is an inverting amplifier?
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[4]
Determine the output waveform for the input square-wave shown
below (Consider pulse rise time and fall time = 10 ns).
Figure 2
[5]
Using a DC sweep simulation obtain the transfer characteristic of
the circuit in Figure 1. Hence:
(a)
Determine the approximate linear input range for the
amplifier.
(b)
Determine the gain of the amplifier and compare it to the
value obtained in [3].
(c)
What indicates that the amplifier is an inverting amplifier?
(Hint: short-circuit C1 and C2 and apply a DC sweep to the input).
[6]
Determine the total harmonic distortion (T.H.D.) obtained when a
50 mV peak sinusoidal signal of frequency 10 kHz is applied to the
input of the amplifier.
[7]
Repeat question [6] for an input of 200 mV peak and comment on the
result, comparing it with that obtained in [6].
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Department of Microelectronics and Nanoelectronics
Assignment 2: Operational Amplifiers
The circuit below shows a 2-stage CMOS op-amp with p-channel input
transistors:
Figure 1
Width/Length Parameters:
[1]
M1: 120µ/8µ
M3: 50µ/10µ
M5: 150µ/10µ
M7: 150µ/10µ
M2: 120µ/8µ
M4: 50µ/10µ
M6: 100µ/10µ
M8: 150µ/10µ
Using the voltage-controlled voltage source (VCVS) method shown
below, perform a balanced differential DC sweep on the input. Plot
the op-amp output node voltage, and hence determine the:
(i)
(ii)
(iii)
linear range
offset
open loop gain
Figure 2
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[2]
By applying a differential AC (sinusoidal) input of 1 V determine
the open loop magnitude and phase response of the op-amp.
[3]
From [2], determine the open loop phase margin and gain margin.
Hence comment on the stability of the op-amp when it is used as a
unity gain non-inverting buffer.
[4]
Repeat [2] and [3], with the frequency compensation network R–CC
disconnected. How does this network affect the frequency response
and stability?
[5]
Connect the op-amp as an inverting adder as shown in the diagram
below:
Figure 3
Apply a 10 kHz 1mV pk input to node 10 and a 30 kHz 1mV pk
input to node 11. Perform TRANSIENT analysis and hence
FOURIER analysis (using a 10 kHz base frequency) on the output
node. Comment on the Fourier results obtained: does the op-amp
show any considerable MULTIPLICATIVE mixing effect due to
non–linearities?
Hint: Recall that: 2 sin (ω1t )sin (ω 2 t ) = cos((ω1 − ω 2 )t ) − cos((ω1 + ω 2 )t )
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Department of Microelectronics and Nanoelectronics
Assignment 3: Applications of Operational Amplifiers
The following circuits use the CMOS op-amp which has been defined as a
sub-circuit in tutorial sheet 2.
Figure 1
[1]
Using the arrangement shown in Figure 1 above examine how the
output voltage varies with the value of the load resistor RL. Hence
determine the output resistance of the op-amp.
[2]
The circuit shown in the Figure 2 shows the input part of a 3-bit
A/D flash converter (encoder part missing). By sweeping the input
voltage source, verify the outputs VD1 to VD7.
Figure 2
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[3]
Figure 3 shows a 4-bit D/A converter utilizing an R-2R ladder
network. Build the DAC and verify its operation.
Figure 3
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Assignment 4: Digital Integrated Circuits
[1]
The diagram below shows a 2-input NAND gate implemented using
CMOS technology:
Figure 1
MOSFET DATA:
M1 & M3:
M2 & M4:
L=5µ, W=30µ (PMOS)
L=5µ, W=15µ (NMOS)
Connect the NAND gate as shown in Figure 2, with CL representing
the load capacitance:
[2]
Figure 2
Apply a fixed 5V to one input and a d.c. sweep (0 to 5V) to the other input.
Hence obtain a plot of the output waveform and the supply current
waveform. Repeat this test, this time interchanging the input connections.
Hence determine:
(a)
(b)
The minimum input voltage VIH which is interpreted as HIGH
by the NAND gate.
The maximum input voltage VIL which is interpreted as LOW by
the NAND gate.
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[3]
Consider the arrangement shown in the Figure below:
Figure 3
Apply a PULSE waveform to one of the inputs and thus obtain the
load capacitor voltage and current.
[4]
VD1
0
0
0
0
0
0
0
1
Consider the 8 to 3 encoder needed by the flash ADC used in
tutorial 3 (Q2). The following partial truth table describes the logic
functions of the encoder:
VD2
0
0
0
0
0
0
1
1
INPUTS
VD3 VD4 VD5
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
VD6
0
0
1
1
1
1
1
1
VD7
0
1
1
1
1
1
1
1
Q0
0
1
0
1
0
1
0
1
OUTPUTS
Q1
Q2
0
0
0
0
1
0
1
0
0
1
0
1
1
1
1
1
Other input combinations are DON’T CARE conditions and may be
ignored. Implement the encoder using 2-input NAND gates (you
need not fully minimise the logic functions involved). Hence define
the encoder in HSPICE format as a sub-circuit with external nodes:
VD1, VD2, VD3, VD4, VD5, VD6, VD7, Vdd, Gnd, Q0, Q1 and Q2.
[5]
Add the encoder to the comparator section of the flash ADC. Hence
using the same procedure described in tutorial 3 (Question 2), verify
the encoded outputs Q0 to Q3.
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Department of Microelectronics and Nanoelectronics
Assignment 5: Differential Amplifier – Design and Analysis
[1]
For the differential pair shown in Figure 1 show that the small
signal differential gain is given by:
Avd =
Vo
W
K PW1 I
= K P 1 VGS1 − VT R = R
Vi
L1
L1
(
)
where W1/L1 = W2/L2 are the dimensions of M1 and M2. Assume that
the MOSFETS operate in the saturation region and neglect the
channel modulation effects.
Figure 1
Hence design the differential pair assuming I = 100 µA and
R = 50 kΩ in order to obtain a differential gain of 50. Also determine
the saturation voltage VDSsat of M1 and M2. The MOSFET
parameters are given in the table below:
Parameter
Kp (µA/V2)
VTO (V)
λ (V-1)
Lmm (µm)
N-Channel
120
0.7
0.06
0.35
P-Channel
40
0.7
0.06
0.35
Use Cadence simulation in order to determine:
(i)
(ii)
the D.C. operating point
the frequency response with regards to gain and phase
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Department of Microelectronics and Nanoelectronics
Figure 2
[2]
The current source I is to be replaced by the current mirror shown
in Figure 2. Calculate the W and L values of the mirror transistors
M3 and M4 and the value of Rbias. Assume that the mirror transistors
should operate with a gate overdrive (Vgs–VT) of 0.3 V. Verify the
circuit operation with regards to D.C. bias conditions using
HSPICE. How does VDS4 affect the common-mode rejection ratio
(CMRR) of the differential pair?
[3]
A common-source output stage is to be cascaded after the
differential pair as shown in Figure 3. The output stage
quiescent current should also be set to 100 µA. Estimate the W
and L values of the output stage transistors. Show that the
small signal voltage gain of the output stage is given by:
Av 2 =
g m5
g ds 5 + g ds 6
Assume that the MOSFETS operate in saturation but take
into account the output a.c. conductance gds.
Figure 3
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Starting from the MOSFET (model 2) equation in saturation:
ID =
K PW
(1 + λVDS )(VGS − VT )2
2L
deduce an expression for gds and hence determine the theoretical
composite small signal of the above arrangement.
[4]
Use correct analyses on the above arrangement in order to
determine:
(i)
(ii)
(iii)
(iv)
(v)
(vi)
the D.C. operating point
the transfer function Vo versus Vin (hence also determine
the gain, linear region and d.c. offset).
Frequency response: Gain and phase.
Slew rate
Common mode rejection ratio
Power supply rejection ratio
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