A 100 µW Decimator for a 16 bit 24 kHz
bandwidth Audio ∆Σ Modulator
Shankar Parameswaran,
Nagendra Krishnapura
Department of Electrical Engineering
Indian Institute of Technology, Madras
Chennai, 600036, India
2010 International Symposium on Circuits and Systems,
Paris, France
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
Outline
Brief overview of ∆Σ Modulators & Decimators
Architectural optimizations in decimator to reduce power
Simulation results
Fabricated chip results
Conclusions
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
Block diagram - Continuous Time ∆Σ Modulator
Vin(t) +
_
Σ
Loop Filter
L(s)
fs
DAC
m bit
Oversampling
Noise shaping
Low resolution internal ADC
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
ADC
m bit
Output
m bits
Spectrum of the ∆Σ Modulator output
60
40
Spectral Magnitude (dB)
10
−20
−50
−80
−110
−140
Inband
−170
−200 2
10
3
10
4
10
Frequency (kHz)
5
10
6
10
3rd order L(s) , 4 bit ADC, fs = 3.072 MHz
Inband Signal to noise ratio (SNR) = 96 dB
Decimator - Low pass filtering & downsampling
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
Decimator requirements
Modulator[1]
Order
3
Sampling rate
Nyquist rate
SNR
Power
3.072 MHz
48 kHz
93 dB
90 µW
Decimation Filter
Downsampling
64
Factor
Passband ripple
0.05 dB
Passband edge
21.6 kHz
SNR
96 dB
Power
< 100 µW
[1] - S. Pavan, N. Krishnapura, R. Pandarinathan, and P. Sankar, "A power optimized continuous-time ∆Σ converter
for audio applications," IEEE Journal of Solid-State Circuits, vol. 43, no. 2, pp. 351 360, 2008
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
Block diagram of the decimator
Input
4
Output
H1(z)
16
H2(z)
20
2
S
H3(z)
H1(z): SINC4
H2(z): First Halfband filter
H3(z): Second Halfband filter
H4(z): Equalizer
S : Scaling block
Multistage decimation
Shankar Parameswaran, Nagendra Krishnapura
H4(z)
24
24
24
2
EE, IITM, India
16
SINC4 filter
SINC, H(z) - 16 tap moving average filter
SINC4, H 4 (z) - Cascade of 4 SINC filters
Removes quantization noise shaping
Downsampling of 16 - Hogenauer structure
H(z) =
1 − z −16
1 − z −1
H(f ) =
sin(16πf )
sin(πf )
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
SINC4 - Hogenauer structure
Input
+Σ
+
+Σ
+
z-1
clk
+
Σ
+
z-1
clk
accumulators
+
Σ
z-1
+
clk
z-1
clk
z-1
clk/16
z-1
-1
z
clk/16
z-1
clk/16
clk/16
_
_
Σ
+
differentiators
+
Σ
z-1
clk/16
_
+
Σ
Retiming, Pipelining save 46% power in SINC4
Optimal Datawidth = Bin + k log2 N = 20
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
_
+
Σ
Output
Frequency response of SINC4
0
Magnitude Response (dB)
−50
−100
−150
−200
−250
0
200
400
600
800
1000
Frequency (kHz)
1200
1400
Shaded Area - Noise aliasing bands
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
1600
Halfband filters
FIR filters
6 dB bandwidth = f4s
Alternate tap weights are 0
Two halfband filters downsample by 2 each
First halfband filter
Initial filtering
10th order
Second halfband filter
Sharper filtering
50th order
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
Halfband filter implementation
Polyphase structure, downsampling by 2 within filter
Tap weights in Canonical Signed Digits (CSD)
Example: 0.875 = 2−1 + 2−2 + 2−3 = 20 − 2−4
(Reduces Multiplication Complexity)
Nested Multiplication, Horners rule
Example: 2−5 − 2−7 = 2−5 (1 − 2−2 )
(Reduces Truncation Error)
2−1 is dropping a bit in the multiplicand
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
Datawidth in halfband filters
Magnitude(dB)
q1 bits
q2 bits
N1 (f ) = 10
N2 (f ) = 10
N1(f)
−6q2
10
N2
N1
R
= q1 +
6
R = 10 log
R dB
N2(f)
0.25fs
−6q1
10
q2
0.5fs
To attenuate a portion of quantization noise floor of a q1 =16 bit
signal by 48 dB in some band needs q2 =24 bit in the filter.
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
Frequency response of halfband filters
20
Magnitude Response (dB)
0
−20
Halfband2
Halfband1
−40
−60
−80
−100
−120
0
20
40
60
Frequency (kHz)
80
Shaded Area - Noise aliasing bands
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
100
Scaling block
∆Σ Modulator - Maximum Stable Amplitude (MSA=85%)
Signal swing at modulator output is MSA × fullscale
96 dB SNR at Nyquist rate only with fullscale amplitude
Scale by MSA−1 after first halfband filter
Lesser number of bits from modulator (4) and high
frequency noise prevents scaling at the initial stages of
decimator
CSD & Nested Multiplication
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
Equalizer
Droop of SINC4 in the passband
Maximum passband ripple = 0.05 dB
Inverse SINC4 designed with Parks McClellan method
48th order filter
CSD & Nested Multiplication
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
Frequency response of the equalizer
Magnitude Response (dB)
0.5
Equalizer Response
Unequalized Response
Equalized Response
0
−0.5
−1
−1.5
−2
0
0.06
0.04
0.02
0
−0.02
−0.04
−0.06
0
4
4
8
12
16
20
8
12
Frequency (kHz)
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
16
20
Synthesis
Technology: 1.8 V standard cells UMC 0.18 µm CMOS
CAD tools
Design Synthesis - Design Compiler
Place & Route - SoC Encounter
Power Consumption - PrimePower
96.7 µW - ∆Σ modulator input is a tone at 1.6 kHz
100 µW - ∆Σ modulator input is a white noise
Active area = 0.46 mm2
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
Layout of the fabricated chip
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
Picture of the test board
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
Measurement results from the chip
Chip works correctly at 1.8 V supply and works reliably
down to 0.9 V at 3.072 MHz
Current consumed with 1.8 V supply = 58 µA (104.4 µW)
Current consumed with 0.9 V supply = 26 µA
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
Decimated output spectrum from the chip
125
Spectral Magnitude (dB)
100
Tone at 4.125 kHz
75
50
25
0
−25
0
4
8
12
16
Frequency (kHz)
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
20
24
Conclusion
100 µW decimator for audio ∆Σ ADC
No handcrafted circuits - completely implemented with
automated CAD tools
Works down to 0.9 V supply
50% power reduction with a linear power regulator
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India
References
S. Pavan, N. Krishnapura, R. Pandarinathan, and P. Sankar, "A power optimized continuous-time ∆Σ
converter for audio applications," IEEE Journal of Solid-State Circuits, vol. 43, no. 2, pp. 351 360, 2008
S. Pavan and P. Sankar, "A 110µW Single Bit Audio Continuous-time Oversampled Converter with 92.5 dB
Dynamic Range" Proceedings of the European Solid State Circuits conference, September 2009.
Ronald E. Crochiere, Lawrence R. Rabiner, "Interpolation and Decimation of Digital Signals - A Tutorial
Review," Proceedings of the IEEE vol. 69, NO. 3, March 1981.
Carol J. Barrett, Low-power decimation filter design for multi-standard transceiver applications, Master of
Science Thesis, University of California, Berkeley.
James C. Candy, "Decimation for Sigma Delta Modulation," IEEE transactions on communications, vol.
com-34, no. 1. January 1986.
Eugene B. Hogenauer, "An economical class of digital filters for decimation and interpolation," IEEE
transactions on acoustics, speech, and signal processing, vol. assp-29, no. 2, April 1981.
Keshab K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, John Wiley & Sons,
1999.
Reid M. Hewlitt, Earl S. Swartzlander, Jr.,"Canonical signed digit representation for fir digital filters," IEEE
Workshop on Signal Processing Systems, 2000,SiPS 2000.
Shankar Parameswaran, Nagendra Krishnapura
EE, IITM, India