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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 12, DECEMBER 2009
CMOS Distributed Amplifiers With Extended Flat
Bandwidth and Improved Input Matching
Using Gate Line With Coupled Inductors
Kamran Entesari, Member, IEEE, Ahmad Reza Tavakoli, and Ahmed Helmy
Abstract—This paper presents a state-of-the-art distributed
amplifier with coupled inductors in the gate line. The proposed
coupled inductors, in conjunction with series-peaking inductors
in cascode gain stages, provide bandwidth extension with flat gain
response for the amplifier without any additional power consumption. On the other hand, gate-inductor coupling improves the input
matching of the amplifier considerably. The detailed analysis and
design methodology for the proposed distributed amplifier are
presented. The new four-stage distributed amplifier, fabricated
using an IBM 0.18- m complementary-metal–oxide–semiconductor process, achieves a power gain of around 10 dB, input and
output return losses better than 16 and 18 dB, respectively, a noise
figure of 3.6–4.9 dB, and a power consumption of 21 mW over a
16-GHz flat 1-dB bandwidth. The measured IIP3 of the amplifier
is between 0.1 and 3.75 dBm across the entire band.
Index Terms—Complementary metal–oxide–semiconductor
(CMOS), coupled inductors, distributed amplifiers, monolithic
microwave integrated circuit.
I. INTRODUCTION
ITH INCREASING interest on commercial wideband
integrated systems such as radars and wireless ultrawideband and optical receivers, there is a demand for wideband
complementary-metal–oxide–semiconductor (CMOS) amplifiers in the front-end section of such systems. Distributed
amplification is one of the well-known methods to provide such
performance by absorbing the parasitic capacitances of parallel
gain stages into an artificial transmission line, which, in return,
guarantees the gain uniformity and input/output matching
within the bandwidth of operation [1].
Various distributed amplifiers have been reported in a
0.18- m CMOS process recently. Liu et al. [2], [3] presented distributed amplifiers with 1-dB bandwidths of 14 and
22 GHz, respectively. The reported amplifiers with cascode
W
Manuscript received June 17, 2009; revised September 17, 2009. First published October 30, 2009; current version published December 09, 2009.
K. Entesari and A. Helmy are with the Department of Electrical and Computer
Engineering, Texas A&M University, College Station, TX 77843 USA (e-mail:
kentesar@ece.tamu.edu; manarman@neo.tamu.edu).
A. R. Tavakoli was with the Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX 77843 USA. He is
now with the Aquantia Corporation, San Jose, CA 95035-7456 USA (e-mail:
tavakoli@ece.tamu.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2009.2034044
gain stages suffer from high power consumption and considerable input mismatch. Shigematsu et al. [4] employed the
resistive-source-degeneration technique for common-source
gain stages to achieve a 1-dB bandwidth of 39 GHz. Although
this technique improves the bandwidth enormously, it results in
low gain, high power consumption, and high input mismatch.
Tsai et al. [5] implemented distributed amplifiers with cascaded
gain stages to achieve high gain–bandwidth product, but the
amplifier consumes a huge amount of power, and the input
matching is poor. High power consumption and poor input
matching have been the important drawbacks of the reported
amplifiers, because bandwidth extension has traditionally been
achieved by reducing the loading capacitance of the gate line
provided by the single-stage amplifier. Therefore, to achieve
similar gain performance, the power consumption of the amplifier has been increased. Also, due to nonuniform loading of the
gate line, the input matching has been degraded, particularly at
higher frequencies. The nonuniform loading appears because
of frequency dependence of the gate-line capacitance, which
comes from the Miller effect of the gain stage.
The proposed three-stage distributed low-noise amplifier
in [6] used standard cascode gain stages, and the power consumption and noise figure (NF) are considerably reduced by
mW ,
optimizing the bias point of the amplifiers
but the achieved 1-dB bandwidth is only around 6.2 GHz.
To increase the gain–bandwidth product while keeping the
power consumption low, the distributed amplifiers in [7] employed a three-stage amplifier with cascode gain cells with
series-peaking inductor and achieved a 1-dB bandwidth of
11 GHz with a power consumption of 21.6 mW. The advantage of peaking inductor is to increase the gain-bandwidth
product of the gain stage without increasing the power consumption. On the other hand, gain peaking does not allow
maximum-flat-bandwidth extension. It also changes the input
Miller capacitance of the gain stage at higher frequencies,
which degrades the uniformity of the gate line and limits the
input matching of the amplifier. The proposed amplifier in [8]
employs inductive peaking with the stagger-tuning technique to
achieve bandwidth enhancement with gain flatness. Since the
gain cells are replaced by cascaded stages to boost the gain, the
total power consumption of the amplifier is considerably high
mW . Also, the input matching of the amplifier
is degraded at high frequencies that are close to cutoff due
to nonuniform loading of the gate line caused by the Miller
capacitance. The proposed weighted amplifier in [9] employs
coupled inductors in both gate and drain lines to minimize
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ENTESARI et al.: CMOS DISTRIBUTED AMPLIFIERS WITH EXTENDED FLAT BANDWIDTH AND IMPROVED INPUT MATCHING
2863
Fig. 2. Simulated power consumption versus 3-dB bandwidth for a cascode
gain stage with and without L for a gain of 4 dB. The value of L is adjusted
for a gain peaking of 1.24 dB.
Fig. 1. (a) Conventional distributed amplifier with artificial transmission lines
and g cells. (b) Common-source gain stage. (c) Cascode gain stage with seriespeaking inductor (L ). (d) Proposed gain stage with coupled inductors in the
gate line.
the size of the amplifier and also allows the transconductance
of different stages to be different to optimize the NF of the
amplifier with an added degree of freedom.
This paper presents a CMOS distributed amplifier that takes
advantage of the gate line with coupled inductors, in conjunction with cascode gain stages with series-peaking inductors
employed in [7]. This approach provides bandwidth extension
with flat gain response and improves the input matching of the
amplifier simultaneously without any additional power consumption. This paper is organized as follows. In Section II, the
proposed amplifier architecture is demonstrated and a design
methodology for flat-bandwidth extension and input-matching
improvement is proposed. Circuit design and implementation
are discussed in Section III, and the simulation and measurement results are presented in Section IV.
II. DISTRIBUTED AMPLIFIER ARCHITECTURE
A. Background
Fig. 1(a) shows a conventional distributed amplifier with artificial transmission lines and
cells, where ,
and ,
are the gate- and drain-line inductors and capacitors, respectively. In order to guarantee a constructive addition of forward path currents at the bandwidth of operation, the signals
cell (
should be in phase at the output of each
or
). For proper input/output matching, the
characteristic impedance of gate/drain lines and the termination
impedance ( ) should be the same
. As a result,
and
in an ideal amplifier.
The cutoff frequencies of the emulated transmission lines are
given by [1]
(1)
is limited by the input capacitance of the
cell,
Usually,
which means that the bandwidth of the distributed amplifier
while keeping
large
can be optimized by optimizing
enough to provide the required gain. Therefore,
in practice, and an additional output parallel capacitance is
to be the same as . Fig. 1(b) shows a
needed to increase
common-source gain stage. The main drawback of this structure
is the Miller capacitance at the gate of each gain stage, which results in bandwidth reduction. To avoid this issue, a cascode stage
). The cascode bandwidth
can be used (Fig. 1(c), where
is primarily limited by the pole associated to the internal node of
,
the cascode cells whose value is
is the output capacitance of
,
is the input
where
, and
is the transconductance of
.
capacitance of
To suppress the cascode-stage dominant pole at higher frein Fig. 1(c)] is
quencies, a bandwidth-enhancing inductor (
added to the amplifier [7]. This compensation method results
if bandwidth
in high-frequency gain peaking at the drain of
extension without power-consumption penalty is desired [8].
To see how much power-consumption improvement is achieved
in the cascode topology, the coscode stage in
by employing
. The simulation is
Fig. 1(c) is simulated with and without
performed for a gain of 4 dB
mS and the
same 3-dB bandwidths using the IBM 0.18- m CMOS process
is adjusted for a gain
design kit in Cadence.1 The value of
peaking of 1.24 dB for maximum-bandwidth extension. Fig. 2
shows the simulated power consumption versus bandwidth
. For a bandwidth of
for a cascode stage with and without
16 GHz, a power-consumption improvement factor of 1.8 is
allows one to increase the transistor
achieved. Employing
size to achieve the same transconductance with lower power
consumption for the same bandwidth.
This gain peaking does not allow flat-bandwidth extension. It
at higher frealso changes the input Miller capacitance of
quencies, which degrades the uniformity of the gate line and,
hence, the input matching of the amplifier. The proposed gain
stage in Fig. 1(d) extends the maximum flat bandwidth and improves the input matching simultaneously by introducing mutual coupling with a coefficient of between two adjacent gate
inductors, as will be discussed later in this section.
B. Gate Line With Coupled Inductors
Fig. 3(a) shows the equivalent circuit of the gate line with
is the effective loading cacoupled inductors, where
pacitance at the input of the
cell and has strong frequency
dependence, particularly for cascode cells with series-peaking
1Online.
Available: www.cadence.com
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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 12, DECEMBER 2009
Fig. 3. Equivalent circuit of the gate line with: (a) coupled inductors,
(b) T-model for the coupled inductors, and (c) effective L and C (!).
inductor. The coupled inductor is substituted by a T-model in
is the mutual inductance between
Fig. 3(b), where
inductors. The negative inductance
is in
two adjacent
. Fig. 3(c) shows the equivalent gate-line cirseries with
cuit with effective inductance
and capacitance
given
by
(2)
Since
,
is always larger than physical inductance . As a result, a gate line with lower physical inductance
(ohmic loss) can be used. Also,
is less sensitive to the
with frequency because of coupling coefvariation of
ficient , which also allows the input-matching improvement,
of the new
as will be discussed later. The cutoff frequency
gate line is found by evaluating
at as follows:
(3)
Hence,
Fig. 4. (a) Schematic of a cascode gain stage with peaking and a gate line with
calculation.
coupled inductors and (b) the small-signal model for G
close to the source impedance ( ) within the band of interest
is achievable, as will be seen in Section II-F.
C. Gain Stage
Fig. 4(a) shows the ac equivalent circuit of the cascode gain
stage with series peaking and the gate line with coupled inductors. Fig. 4(b) shows the high-frequency small-signal model that
is suitable for calculating the total transconductance
as follows:
(6)
where
is the transconductance of the
,
and neglecting
cascode stage. Assuming that
and
, the voltage gain (
) is calcuthe effect of
and
transfer functions
lated by multiplying the
given by
(4)
(7)
The dependence of
on frequency is known for a spe-cell topology, as will be discussed in Section II-C.
cific
, increasing
improves the bandwidth of
Since
with similar
the gate line compared to the case where
physical . Also, the characteristic impedance of the new line
is defined as
(8)
where
is the transconductance of
and
(9)
As a result,
(10)
(5)
Similar to
,
has also less dependence on
,
which means that the gate-line characteristic impedance is less
degraded by the -cell frequency variation. Also, by adjusting
the value of
using
and , an input matching that is
has a pole at
. The inductive behavior
due to
resonates with
at higher frequencies, reof
sulting in gain peaking at in the frequency response [8]. Fig. 5
shows the normalized transconductance of the cascode stage,
, versus frequency
i.e.,
has
for different values of . For a small value of ,
showing a gain roll-off at the
a low-frequency pole
midband. By increasing , decreases, the gain roll-off at the
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ENTESARI et al.: CMOS DISTRIBUTED AMPLIFIERS WITH EXTENDED FLAT BANDWIDTH AND IMPROVED INPUT MATCHING
Fig. 5.
j
G
jf )
(
j
versus frequency for different values of
L
2865
.
Fig. 6. Two different signals passing through the gate and drain lines between
two arbitrary gain stages.
midband disappears, and gain peaking increases. Therefore, the
is selected to achieve the maximum bandwidth with
value of
minimum roll-off at the midband.
The effective loading capacitance of the cascode stage at node
‘ ’ in Fig. 4(b) is calculated using the Miller effect
equivalent circuit of the coupled gate line with effective values
derived in (2) is used as follows:
of and
(11)
(14)
Finally, the transfer function of the gate line is given by
Also, to provide matching at the drain line
(15)
(12)
is a function of frequency itself, as described
Since
in (8) and (11), the transfer function of the gate line is not
simply a second-order low-pass response. The input return loss
of the gain stage is found by calculating the input impedance
in Fig. 4(b) and using the equation
and is given by (13), shown at the bottom of
is the coefficient of
this page. The term
the highest order term in both numerator and denominator polyreduces the value of this coefficient for
nomials. Increasing
at a certain frequency. This means that the
a certain value of
will shift to higher frequencies, and
poles and zeros of
in case
has a small value at low frequencies, increasing
increases the frequency at which
starts to degrade.
Equations (14) and (15) provide the required values of
and
for the given
, , and
to provide phase
matching, as will be seen in Section II-F.
Drain-line inductors can also be coupled similar to the gateline ones with a coupling factor of . Since there is no Miller
effect and nonuniform loading at the drain of
in Fig. 1(d),
reasonable output matching is achievable without coupling the
drain-line inductors. The advantage of coupling the drain-line
inductors is to reduce their effective value by a factor of
to achieve smaller inductors with lower loss. Since reducing the
size of the amplifier has not been the major purpose of this paper,
drain-line inductors are not coupled to each other to simplify the
layout implementation.
E. Number of Stages
D. Drain Line
With the coupled inductor in the gate line, the phase delays
of the gate and drain lines between each gain stage are different.
Fig. 6 shows two different signals passing through the gate
and drain lines between two arbitrary gain stages and adding
up at the output of the second stage. Both signals are passing
does
through equal series-peaking inductors. Therefore,
not generate any phase difference between the two signals.
cell, the
To provide in-phase signals at the output of each
There is no limit on the number of stages in a distributed
amplifier with lossless artificial lines. However, both gate and
have limited
drain artificial lines are lossy in practice ( and
quality factors). Therefore, there is an optimum value for the
number of stages of an amplifier with artificial lines [Fig. 1(a)],
which is given by [1]
(16)
(13)
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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 12, DECEMBER 2009
where
and
are real parts of the gate- and drain-line propagation constants, respectively. Assuming that the losses of
and
are negligible,
and
are approximated by [1]
M
(17)
where
and
are the losses of inductors
and , and
and
are the imaginary parts of the gate- and drain-line
propagation constants, respectively. To find out the optimum
) for the gain stage with coupled inducnumber of stages (
tors in the gate line [Fig. 1(d)], the effective inductance ( )
presented in (2) is employed. By combining (2), (16), and (17),
is given by (18), shown at the bottom of this page, where
and
. The opcells
timum number of stages for the amplifiers with cascode
[Fig. 1(c)] in CMOS technology is calculated to be three in [2],
[3], [6], and [7], considering the loss of the reported inductors
on silicon. For the proposed distributed amplifier, the optimum
number of gain stages can be set higher (four in this design) due
to the lower loss of inductors in artificial gate lines as a result of
mutual coupling. The design procedure presented in Section II-F
shows how
is found using (18), assuming that the loss of
inductors is known.
F. Design Methodology
To achieve an overall flat response for
, the gate-line
cutoff frequency needs to be selected in a way that the transfer
at
function of the line compensates the gain peaking of
, meaning that
(19)
By substituting
in (12), (19) is modified into
(20)
M
Fig. 7. Simulated aspect ratio of transistors
and
in Fig. 1(d) versus the
power consumption of each gain stage for different values of gain per stage.
Solving the aforementioned equation for the given
,
, and
results in the required gate-line cutoff
through (11).
frequency ( ) and the value of
To have a matched gain stage at the input, (5) is evaluated at
to satisfy
or
(21)
and
and solving two
By knowing the values of
nonlinear equations (4) and (21) together, the required values
are found to achieve a flat response and acceptable
of and
input matching. Also, by solving (14) and (15) at , using the
, the values of
and
will be
values of , , and
found.
In conclusion, a design methodology is proposed based on
the derived equations. The purpose of this methodology is to design a distributed amplifier with cascode gain stages and coupled
gate-line inductors to achieve a maximum flat bandwidth and
acceptable input matching for a given total gain and power consumption. A summary of systematic design steps is explained
first, and these steps are then applied to design the desired distributed amplifier in an IBM 0.18- m process, as detailed in the
following.
) to
Step 1) Assume the optimum number of stages (
be a number between three and five. Therefore, it is within
the range of optimum number of stages reported for various distributed amplifiers [1]. The total gain and power
consumption of the amplifier and, thus, for each stage are
given.
Step 2) Find the transistor biasing current and aspect ratios
for a certain gain and power consumption per stage using
Fig. 7. It shows the simulated aspect ratio of transistors
(18)
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ENTESARI et al.: CMOS DISTRIBUTED AMPLIFIERS WITH EXTENDED FLAT BANDWIDTH AND IMPROVED INPUT MATCHING
Fig. 8. Simulated j(V =V )(jf )j , jG
(jf )j , and jS (jf )j
of a single gain stage for L
(jf )j
= 1:24 dB).
different values of k (L = 0:3 nH, f = 16 GHz, and jG
and
in Fig. 1(d) versus the power consumption of
each gain stage for different values of gain per stage using
.
Cadence, assuming that
,
,
, and
using
Step 3) Extract the values of
Cadence and knowing the calculated aspect ratios.
Step 4) Calculate the value of cascode-stage transcon) using (9) and (10) and maximize the
ductance (
by adjusting
bandwidth of the cascode amplifier
to cancel the gain roll-off effect due to the pole
), as shown in Fig. 5.
(
Step 5) Find the effective loading capacitance of the cas) at
using (11).
code stage (
Step 6) Calculate the gate-line cutoff frequency ( ) using
.
(20) to achieve a flat response for
and
by solving (4) and
Step 7) Find the values of
(21), assuming the matching condition at the vicinity of
.
and
and evaluating
Step 8) Knowing the values of
, calculate
,
, and
(14) and (15) at
to provide the required phase matching between the gate and drain lines.
Step 9) By finding the practical values of loss for the calcuand
using the available design kit, calculate the
lated
and the optimum number of
values of , , , and
stages using (18). If this number is the same as what is assumed in Step 1), then the design is finalized. If not, change
, and repeat all the following steps until a
the value of
is achieved from Steps 1) to 9).
similar value of
This design methodology is applied to design a distributed
amplifier in an IBM 0.18- m process as follows.
Step 1) A four-stage amplifier with an overall power gain
of 10 dB and a power budget of around 21 mW is consid-
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=2 values of: (a) 0.1 nH, (b) 0.2 nH, and (c) 0.3 nH and
ered (power gain per stage 4 dB and power consumption
per stage 5.25 mW).
Steps 2) and 3) The appropriate device aspect ratio is then
selected for a given gain and power consumption per stage
m
m.
using Fig. 7
The values of parasitic capacitances are then calculated
using Cadence (
pF,
pF,
pF).
and
Steps 4) and 5) For the selected transistor aspect ratio,
the series-peaking inductor ( ) is adjusted to be around
0.3 nH to maximize the flat bandwidth of the cascode gain
stage
GHz , as shown in Fig. 5. In this case,
dB. Also,
is calculated
from (11).
Step 6) To achieve the flat response within the bandwidth, the cutoff frequency ( ) is calculated to be around
21.7 GHz using (20).
Step 7) By solving (4) and (21) together, the values of
and
are found to be 0.2 and 0.4 nH, respectively.
is calculated to be 0.5 nH through
Step 8) The value of
,
, and
GHz
(14), assuming that
to equalize the gate- and drain-line phase shifts.
Step 9) The losses of inductors
nH and
nH are found to be 3.4 and 4.2 using the IBM
0.18- m CMOS process design kit, and the value of
is found to be close to four using (18) at .
To verify the proposed design methodology, the effect
is investigated on the
of various combinations of
), the total normalized
gate-line insertion loss (
),
transconductance (
and the input return loss (
) of a single gain stage
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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 12, DECEMBER 2009
Fig. 10. Layout of a center-tapped differential inductor.
Fig. 9. Schematic of the entire four-stage amplifier, including bias-Ts.
using (6)–(13) and MATLAB.2 Fig. 8 shows the simulated
,
, and
of the
nH,
gain stage for different values of and , where
GHz, and
dB.
nH [Fig. 8(a)], a peaking in the gateIn case of
on the line,
line response is observed due to the effect of
which adds up to the peaking introduced by the cascode stage.
As a result, the overall peaking of the total transconductance
, this peaking is minimum, but the
is increased. For
input return loss is worse than 10 dB for the 8–16-GHz freimproves the input matching, but
quency range. Increasing
the peaking level in the total response becomes unacceptable.
nH [Fig. 8(b)], the effect of gate-line
In case of
is eliminated by increasing
insertion-loss peaking due to
compared to the previous case. The gate-line inthe value of
sertion loss cancels out the peaking of
at
for
, and a flat transconductance response is achieved with
dB over the band of interest. Increasing to 0.3 improves the gate-line cutoff frequency and input matching, but the
total transconductance shows peaking at because increases
. Therefore, flat-bandand
width extension is not achieved, although input matching shows
, the gate-line cutoff frequency
more improvement. For
drops below . As a result,
does not achieve
maximum-flat-bandwidth extension.
nH [Fig. 8(c)], the cutoff frequency of
In case of
for a lower value of , which limits
the line drops below
the bandwidth extension (
provides the lowest bandwidth extension). To increase the cutoff frequency of the line,
needs to increase considerably ( 0.5–0.8), which results in
at
the total or partial peaking cancellation of
for
or 0.8, respectively. On the other hand, increasing
does not improve the gate-line response at lower frequencies as much as that at frequencies that are close to cutoff (an
insertion loss of 0.8–1 dB is observed for the gate line around
). Therefore,
the 6–8-GHz frequency range for
the overall transconductance response is not completely uniform
within the band of interest, which results in a larger input misnH.
match compared to the previous case where
The results of the aforementioned simulation show a gain stage
nH, and
provides the widest flat rewith
GHz. As shown
sponse with best input matching for
and using the proearlier, similar values are obtained for
posed design methodology.
2Online.
Available: www.matlab.com
Fig. 11. Simulated: (a) inductance, quality factor, and (b) coupling coefficient
of the gate-line coupled inductor versus frequency using Sonnet.
III. CIRCUIT DESIGN AND IMPLEMENTATION
The four-stage amplifier with an of 16 GHz, a power gain
of 10 dB, and an overall power budget of 21 mW is implemented
using the procedure explained in the previous section. Fig. 9
shows the schematic of the entire four-stage amplifier, including
two bias-Ts that were used at the input and output RF terminals
to bias different gain stages during the measurement.
The coupled inductor is implemented differentially, as shown
in Fig. 10 [10]. When the windings of the inductor are designed
properly, the magnetic fields add constructively due to strong
mutual coupling between the two inductors, resulting in an increase in inductance without a corresponding increase in series
at 16 GHz). In order
resistance and a higher inductor (
to consider high-frequency effects in inductor/mutual coupling
realization, electromagnetic simulation is used. The metal/dielectric profile of the process is employed in Sonnet3 to optimize the layout of each inductor. The simulated inductance,
quality factor, and coupling coefficient of the implemented gateline coupled inductor versus frequency are shown in Fig. 11.
In layout implementation, a ground plane is used to shield
the inductors from each other. The distance between the ground
plane and inductors is optimized using full-wave simulation to
40 dB while minimizing
reduce the unwanted coupling to
the extra parasitic capacitance. All the inductors are realized
with the top metal layer, which is the thickest and farthest layer
3Online.
Available: www.sonnet.com
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ENTESARI et al.: CMOS DISTRIBUTED AMPLIFIERS WITH EXTENDED FLAT BANDWIDTH AND IMPROVED INPUT MATCHING
2869
TABLE I
CIRCUIT ELEMENT VALUES AND TRANSISTOR ASPECT RATIOS
FOR THE IMPLEMENTED DISTRIBUTED AMPLIFIER
Fig. 12. Microphotograph of the proposed CMOS distributed amplifier with a
chip size of 1.4 0.85 mm (including the testing pads).
2
Fig. 14. Simulated and measured: (a) input return loss (S ) and (b) output
return loss (S ).
Fig. 15. Measured NF of the distributed amplifier.
Fig. 13. Simulated and measured gains (S ) and reverse isolation (S ).
from the substrate to reduce the substrate loss. The parasitic capacitance of the wide-drain-line inductors is considered at the
output of each gain stage to avoid additional drain capacitances
for phase velocity balance between the gate and drain lines.
are implemented using standard spiral
Both inductors and
structures and optimized using full-wave simulation.
The transistors are laid out with maximum number of fingers
and close to minimum width to minimize the effective series
gate resistance [11]. Tapering is used to connect inductors to
transistors and pads to minimize the parasitic capacitance due
to discontinuities. Capacitance degeneration at the source of
in Fig. 1(d) results in negative input resistance at the gate of
at very low frequencies. To avoid this problem, series resistance
.
( ) and shunt capacitance ( ) are added to the gate of
compensates the gain reduction at higher frequencies because
of
. Table I shows the circuit element values and transistor
aspect ratios for the implemented distributed amplifier. Fig. 12
shows a microphotograph of the fabricated distributed amplifier
with a chip size of 1.4 mm 0.85 mm (including the testing
pads) using an IBM 0.18- m CMOS process.
Fig. 16. Measured third-order intercept point (IIP ) of the distributed amplifier.
IV. SIMULATION AND MEASUREMENT RESULTS
The CMOS distributed amplifier chip was tested via on-wafer
probing using ground–signal-ground coplanar air probes. -parameter measurements of the circuit were carried out using an
Agilent N5230C vector network analyzer. The measurements
V
are performed under operating conditions of
and the overall current consumption of 16 mA. Fig. 13 shows
and reverse
the simulated and measured forward gains
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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 12, DECEMBER 2009
TABLE II
PERFORMANCE COMPARISON OF RECENT DISTRIBUTED AMPLIFIERS IN A 0.18-m CMOS PROCESS
1-dB bandwidth. 3-dB bandwidth.
isolation
, verifying the accuracy of postlayout simulations. The power gain is around 10 dB with 1-dB frequency
band around 16 GHz, and the in-band isolation is less than
30 dB. No gain peaking is observed in the gain response due
to the employment of coupled gate-line inductors. The superior
input–output isolation is partly due to the utilization of cascode
cells in the proposed amplifier. Fig. 14 shows the simulated and
and
, respecmeasured input and output return losses (
and
remain below 16 and 18 dB in the operating
tively).
band, respectively. The improved input return loss is also due to
the employment of coupled gate-line inductors, which results in
a more uniform transmission line, as discussed earlier.
The measured NF of the distributed amplifier is shown in
Fig. 15. The NF is around 3.6–4.9 dB within the band of interest. The linearity measurement was performed using an Agiversus frelent E4446A spectrum analyzer. The measured
quency is shown in Fig. 16 and varies between 0.1 and 3.75 dBm
within the band of interest. Table II shows a comparison among
different performance parameters for recent distributed amplifiers fabricated using a 0.18- m CMOS process and this work.
All the amplifiers listed in Table II were measured using bias-Ts.
V. CONCLUSION
A distributed amplifier with coupled inductors in a gate artificial transmission line has been proposed to extend the flat bandwidth and improve the input matching of the amplifier without
any power-consumption penalty. The detailed analysis of the
distributed amplifier, including the gate line with coupled inductors and the gain stage, has been presented. In addition, a design
methodology for extending the flat bandwidth and improving
the input matching of the amplifier has also been proposed. The
fabricated circuit in a standard 0.18- m CMOS process has exhibited a passband gain of 10 dB and a flat 1-dB bandwidth of
16 GHz. Because of the coupled gate-line inductors, an input
matching that is better than 16 dB has been achieved. Also, the
circuit has consumed a dc power of 21 mW.
ACKNOWLEDGMENT
The authors would like to thank M. El-Nozahi for his help in
measurement.
IIP
= OIP
0 Gainj
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[1] T. T. Y. Wong, Fundamentals of Distributed Amplification. Norwood, MA: Artech House, 1993.
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CMOS cascode distributed amplifier,” in Proc. IEEE VLSI Circuits
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[5] M. Tsai, K. Deng, and H. Wang, “A miniature 25-GHz 9-dB CMOS
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Kamran Entesari (S’03–M’06) received the B.S.
degree in electrical engineering from Sharif University of Technology, Tehran, Iran, in 1995, the
M.S. degree in electrical engineering from Tehran
Polytechnic University, Tehran, in 1999, and the
Ph.D. degree from The University of Michigan at
Ann Arbor, in 2005.
In 2006, he joined the Department of Electrical and
Computer Engineering, Texas A&M University, College Station, where he is currently an Assistant Professor. His research interests include the design of
RF/microwave/millimeter-wave integrated circuits and systems, RF microelectromechanical systems (MEMS), related front-end analog electronic circuits,
and medical electronics.
Dr. Entesari was the recipient of the 2009 Semiconductor Research Corporation Design Contest Second Project Award for his work on dual-band millimeter-wave receivers on silicon.
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ENTESARI et al.: CMOS DISTRIBUTED AMPLIFIERS WITH EXTENDED FLAT BANDWIDTH AND IMPROVED INPUT MATCHING
Ahmad Reza Tavakoli received the B.Sc. degree in electrical engineering from
Sharif University of Technology, Tehran, Iran, in 2006, and the M.Sc. degree in
electrical engineering from Texas A&M University, College Station, in 2008.
Since then, he has been an Integrated Circuit (IC) Design Engineer with the
Aquantia Corporation, San Jose, CA.
2871
Ahmed Helmy was born in Cairo, Egypt, in 1983.
He received the B.Sc. degree (with honors) and M.Sc.
degree in electronics engineering from Cairo University, Giza, Egypt, in 2005 and 2008, respectively, and
is currently working toward the Ph.D. degree in electrical and computer engineering at Texas A&M University, College Station.
From 2005 to 2008, he was a Research Assistant
with the Yousef Jameel Science and Technology
Research Center, The American University, Cairo,
Egypt. His research interests include MEMS, sensors, and RF design.
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