VIP : Various Instruction Paradigms
A novel 12‐bit ISA for introducing novice students to instruction set paradigms, their use and implementation
WESE‐ October 3rd 2013, Montreal, Canada
Dr. David C. Dyer BSc (Hons) PhD (Warwick)
CPhys MInstP CEng FIET CITP MBCS
School of Engineering, University of Warwick, UK
People
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Framework
File: WESE‐Presentation‐20131004B.pptx
Tools
Title: WESE‐2013 ‐ VIP
Mind‐set
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Topics – What comes first? Holistic?
 Why develop VIP ?
• Background – why ‘doing’ is so important
• Some personal experiences
 Comparisons with other ISAs – Hardcore vs Softcore
• Commercial
• Educational – are there any educational ISA softcores?
 Technical characteristics of VIP – with slides from classes
• Why 12 bits?
• Programmer’s Model
• Assembly level, Compilers, Algorithms and HDLs
 Examples of code usage
 Demonstration of simulator – time permitting?
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NXP SmartMX2 – year 2010
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Dale’s Cone of Experience
People (students) generally remember:
People (students) are able to: 10% of what they read
Read
•Define
•Describe
20% of what they hear
Hear
•List
•Explain View Images
30% of what they see
Watch Videos
Attend Exhibit/Sites
50% of what they hear and see
Watch a Demonstration
•Demonstrate
•Apply
•Practice 70% of what they say and write
Participate in Hands‐on Workshop
•Analyze
Design Collaborative Lesson
•Design
90% of what they say, discuss, and do
Simulate or Model Lesson or Experience
•Create
Design/Perform a Presentation – Do the “Real Thing”
Source: Computer Strategies, LLC, 1998
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•Evaluate
Introduced by Edgar Dale (1946) in his textbook on audio‐visual methods in teaching. File: WESE‐Presentation‐20131004B.pptx
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What is there to learn about ISAs?
 Do (novice) students see how much they have learned or
how much they have yet to learn?
• Is the glass half full of half empty?
Half empty ?
Half full ?
Detail %
Principle or Idea %
Unknown %
Unknown
Detail
Principle or Idea
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Why be concerned with ISA encoding ?
 Encoding instructions efficiently can
•
•
•
•
Program
Save memory = increase reliability
Increase ‘performance’
Reduce energy
Reduce costs
Application
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Execute
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Which ISA should we teach?
 Manufacturers often have unique ISAs or licenced them from each other.
• Having multiple suppliers is an important commercial consideration.
 The Intel 8051 (from 1980) and x86 families are multiply sourced and latterly so too the ARM’s Cortex series.
• All are very different. • ARM* and MIPS and PowerISA are non‐trivial
 Many processors have been designed to assist teaching and learning of ISAs. E.g. MARIE, ANT8, XTOY and TinyCPU.
• But which has a ‘carry’ bit ? – None ! ?
• How does ‘carry’ behave during subtract?
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Capabilities of PIC16 Microcontroller
PIC1640 ARCHITECTURAL DESCRIPTION
“... The primary purpose of the Programmable Interface Controller (PlC) is to perform
logical processing, basic code conversions, formatting, and to generate fundamental timing
and control signals for I/O devices. The emphasis is on control and interface functions as
opposed to computing functions.”
(General Instrument MOS Databook 1976 Page 211)
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Capabilities of PIC16 Microcontroller
PIC1650 instruction set is identical to PIC1640. Therefore, no more capable. What did the designers intend?
PIC1650 ARCHITECTURAL DESCRIPTION
“... The primary purpose of the Programmable Interface Controller (PlC) is to perform
logical processing, basic code conversions, formatting, and to generate fundamental timing
and control signals for I/O devices. The instruction set also supports computing
functions as well as these control and interface functions.”
(General Instrument MOS Databook 1976 Page 214)
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Block Diagram vs Programmer’s Model of a CPU
Generic data flow but no information about data width or number of registers. Von‐
Neumann model
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8‐Bit data, 16‐bit address => 216=65536 Bytes
No Register file, named accumulators A and B. Could have been called R0 and R1? It’s a matter of convention. Fundamental interface signals.
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What is ARM* ARM7 vs ARMv7 (includes Thumb‐2)
 ARM7 in 1993 = ‘device’ ‐ ARMv7 (2005) = architecture From “Improving ARM Code Density and Performance New Thumb Extensions to the ARM Architecture by Richard Phelan of ARM June 2003”
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ARM’s big.LITTLE – too much for a novice
 Heterogeneous multi‐processors designed to save power • Dynamic redistribution of software between Cortex‐A7 and A15 cores in real‐time to meet time and energy targets
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ARM’s big.LITTLE – too much for a novice
Note: Cortex‐A7 Core (left) has fewer recourses than the A15 (below) but the net effect of each instruction is identical. The logical outcomes are the same but the physical realisations are different. A15 has more execution units with longer pipelines
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Various Instruction Paradigms – VIP ‐ architecture
 Paradigm means
• “an example that serves as a pattern or model for something, especially one that forms the basis of a methodology or theory” Encarta Dictionary.
 VIP is a 12‐bit processor especially designed for teaching multiple principles in Instruction Set Architectures.
 Its ISA is formed from easy‐to‐read 4‐bit fields.
11
0‐7
8
9‐A
B‐F
10
9
8
Dual operand
Short Move
Unary or Control
JMP
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7
6
5
4
3
2
1
0
d
s
d
n
Operation
s/d or n
2’s complement ‐128 to +127 relative displacement
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Why 12 bits? – a few reasons – refer to full paper
 Not only 12 bits but field boundaries are in 4s
• Desire is to make op‐codes and encoding schemes easy to remember, question and re‐invent
 If processing text in ASCII, memory is wasted but it is efficient for 2 DEC 6‐bit codes as used in credit cards.
• Allows discussion about non‐ASCII representations
 Students/Tutors may consider extensions to 16‐bit op‐
codes
• with, say, 3 operands or more registers etc.
 Not only 12‐bit op‐codes but with a ‘modest’ number of non‐trivial instructions.
• May be managed in subsets for exercises and quizzes.
 Reverse the question – why not 12 bits ?
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Programmer’s Model and Addressing modes
 VIP has registers R0 to R3, AR, SR, SP and PC, but with overlaid names and mnemonics A, B, X, and Y. This enables ‘register‐based’ and ‘accumulator’ models.
Register
Assembler Syntax Meaning
R0 or A
R0 or [R0]
Register or register indirect respectively
R1 or B
R1 or [R1]
Register or register indirect respectively
R2 or X
R3 or Y
R2 or [R2+n]
R3 or [R3+n]
Register or register with offset indirect
Register or register with offset indirect
AR
AR
Auxiliary Register for special instructions
SR
SR
Status Register
SP
SP or [SP+n]
Stack Pointer or Stack Pointer relative
PC
PC or [PC+n]
Program Counter or Program Counter relative
Immediate
#n
Data is in next word
Absolute
[n]
Data is at given memory address
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What does a VIP program look like?
 E.g to compute the first 16 Fibonacci numbers.
• F(0)=0; F(1)=1; F(n)=F(n‐2)+F(n‐1) ‐ Where are these used?
• 0, 1, 1, 2, 3, 5, 8, 13, …
5 instruction types, but how Adr
000
002
003
004
005
006
007
008
00A
00C
00D
Opcodes
01C 100
850
901
851
88E
901
021
006 FFE
406 FFF
050
A88
Mnemonic
MOV R1,#0x100
MOVS [R1],#0
INC R1
MOVS [R1],#1
MOVS AR,#0xE
INC R1
MOV R2,R1
MOV R0,[R2+0xFFE]
ADD R0,[R2+0xFFF]
MOV [R1],R0
JDAR -8
E.g. 0 means MOVe, 4 means ADD
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many does a processor need?
R1 = Address of F(0)
F(0)=0
R1 = Address of F(1)
F(1)=1
Loop counter AR = 14
R1 = Address of F(n)
Copy of current address
R0 = F(n-2)
R0 = R0 + F(n-1)
F(n)= F(n-2) + F(n-1)
Decrement AR and if
non-zero jump back 8
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What does a VIP program look like?
 E.g to compute the first 16 Fibonacci numbers.
• F(0)=0; F(1)=1; F(n)=F(n‐2)+F(n‐1)
• 0, 1, 1, 2, 3, 5, 8, 13, Adr
030
032
033
034
035
036
037
038
03A
Opcodes
00C 100
810
821
041
012
424
900
70C 110
DF9
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Mnemonic
LDA #0x100
LDB #0
LDX #1
STB [A]
LDB X
ADDX [A]
INCA
CMPA #0x110
JNZ -7
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A = Address of F(0)
B = F(0)=0
X = F(1)=1
Store F(n)
?
?
Next address
Limit?
Repeat
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How is MOV R1,#0x100 executed ?
 This slide has animations – see*.pptx ‐ not *.pdf
Memory
Address Content
VIP
Registers
R0
000
R1
000
R2
000
R3
000
AR
000
001
01C MOV
100
002
850
MOVS [R1],#0
003
901
INC
004
851
MOVS [R1],#1
005
88E
SR
000
006
901
SP
000
etc
etc
PC
002
000
001
100
???
101
???
000
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R1,#0x100
R1
Memory
Interface
and Timing
Fetch
Decode
And
Execute
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ALU
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Instructions in Group F1
 VIP’s instructions are encoded in 3 groups. This is F1
Bits
Hex
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
11 to 8
mnemonic
MOV
AND
OR
EOR
ADD
ADDC
SUB
CMP
MOVS
F2
F3
JMP = BRA
JEQ = JZ
JNE = JNZ JHS = JC
JLO = JNC
7 to 4
3 to 0
destination
source
d
s
d
s
d
s
d
s
d
s
d
s
d
s
d
s
d
0 to 15
Op1
s/d or n
Op2
s/d or n
‐128 to +127
‐128 to +127
‐128 to +127
‐128 to +127
‐128 to +127
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File: WESE‐Presentation‐20131004B.pptx
operation
d ← s
d ← d .AND. s
d ← d .OR. s
d ← d .EOR. s
d ← d + s
d ← d + s + carry
d ← d + (.NOT. s) + 1
d + (.NOT. s) + 1
d ← n
Op1 : 0 to 15
Op2 : 0 to 15
PC ← PC ± n
If Z=1, PC ← PC ± n
If Z=0, PC ← PC ± n
If C=1, PC ← PC ± n
If C=0, PC ← PC ± n
Title: WESE‐2013 ‐ VIP
Flags affected
NZ
NZ
NZ
See NZ
VNZC
next VNZC
slide
VNZC
VNZC
See F2 table
See F3 table
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Status Register
 VIP’s Status Register and Flags
State at Description
Reset
SR bit
Name
7
U
*
User flag 6
R
1
Reset occurred
5
M
0
Memory type: 0=Von‐Neumann and 1=Harvard, 4
IE
0
Interrupt Enable
3
V
0
Set if sign of result is incorrect using 2’s complement
For addi on: if msb(s)=msb(d) and msb(result)≠msb(d)
For subtrac on: if msb(s)≠msb(d) and msb(result)≠msb(d)
2
N
0
Corresponds to most significant bit of the result
1
Z
0
Set if result of an operation was zero, otherwise cleared
0
C
0
Set if carry out, otherwise cleared
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Instructions in Group F2 ‐ but not all
 VIP’s monadic operations ‐ Group F2 (=09xy)
Bits
Hex
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
x: 7 to 4
mnemonic
INC
DEC
ROR
ROL
RRC
RLC
RAR
PRSG
INV
NEG
DADD
UMUL
TST
EXEC
BCSR
BSSR
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y: 3 to 0
s/d/n
d
d
d
d
d
d
d
d
d
d
s
s
s
s
n, 0 to 15
n, 0 to 15
operation
d ← d + 1
d ← d + 0xFFF
Rotate d right : msb ← lsb; and C←lsb
Rotate d le : lsb ← msb; and C←msb
Rotate d right including carry
Rotate d left including carry
Rotate d ‘arithmetic’ right preserving msb
Left shift lsb from EOR (bits 11,5,3,0)
d ← .NOT. d
d ← (.NOT. d) + 1
AR ← AR + s + carry (3 BCD coded digits)
R1:R0 ← unsigned R0 mes unsigned s s + 0
Execute s as an instruction
SR (bits 3‐0) ← SR .AND. (.NOT. n) SR (bits 3‐0) ← SR .OR. n
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Title: WESE‐2013 ‐ VIP
Flags
C
NZC
NZC
NZC
NZC
NZC
NZC
NZC
NZ
NZC
ZC
Z
NZ
implied
explicit
explicit
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Instructions in Group F3 ‐ but not all
 Monadic operations and control ‐ Group F3 (=0Axy)
Bits x: 7 to 4
y: 3 to 0
Hex mnemonic
s/d/n
operation
Flags
0
PSH
s
SP ← SP‐1; (SP) ← s
1
POP
d
d ← (SP); SP ← SP+1 4
CALL
s
5
RET
n
Explicit if d=SR.
SP ← SP‐1; (SP) ← Return Address
PC ← Effec ve address from s
PC ← (SP)+n; SP ← SP+1
7
RCN
8
JDAR
Count for next rotate instruction.
Semantics ?
n
if n=0 use bits 3:2:1:0 of AR
n, ‐8 to +7 AR ← AR‐1, if AR != 0, PC ← PC ± n
9
JPE
n, ‐8 to +7 If parity of AR is even, PC ← PC ± n
D
JLT
n, ‐8 to +7 If N != V, PC ← PC ± n
E
JGT
n, ‐8 to +7 If Z = 0 and N = V, PC ← PC ± n
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Signed < after CMP instruction
Signed >
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Atomic operations
 Protected instruction sequences
• From interrupt requests and DMA using LOCK/ULCK
Adr
020
022
024
025
026
027
028
028
029
Opcodes
01C 100
02C 002
A6A
035
252
A6B
132
D??
xxx
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Mnemonic
MOV R1,#0x100
MOV R2,#0x002
LOCK
MOV R3,[R1]
OR
[R1],R2
ULCK
AND R3,R2
JNZ label
???
;
;
;
;
;
;
;
;
;
address
flag
protect
get flag
set flag
unlock
test
busy
available
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Other examples
 Binary to BCD conversion
Convert binary number in R0 to 4-digit BCD number in R3:R2 –
R3 is most significant part. From 000:000 to 004:095
A01
PSH R1
/* save R1
*/
830
MOVS R3,#0
/* initialize high */
820
MOVS R2,#0
/* and low parts
*/
81C
MOVS R1,#12
/* 12 shifts
*/
930
ROL R0
082
MOV AR,R2
/* Decimal double */
9A2
DADD R2
/* with carry in
*/
028
MOV R2,AR
/* and carry out
*/
083
MOV AR,R3
/* repeated for
*/
9A3
DADD R3
/* for high part
*/
038
MOV R3,AR
911
DEC R1
/* loop ?
*/
DF7
JNE R1
A11
POP R1
/* recover R1
*/
A50
RET
RET
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Other examples
 Insertion sort
uint12 index=R0,*pi=[R1],*pj=[R2],*pk=[R3];
pi=a;
pk=a+n;
while(pi++, pi!=pk){
m0:
index = *pi;
pj=pi;
while(pj!=a && *(pj-1) > index){
m1:
*pj = *(pj-1);
pj--;
}
*pj = index;
m3:
}
return a[n>>1];
}
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File: WESE‐Presentation‐20131004B.pptx
m4:
/* Tested */
MOV R1,#start
MOV R3,#start+7
INC R1
CMP R1,R3
JEQ m4
MOV R0,[R1]
MOV R2,R1
CMP R2,#start
JEQ m3
CMP R0,[R2+0xFFF]
JHS m3
MOV [R2+0],[R2+0xFFF]
DEC R2
JMP m1
MOV [R2+0],R0
JMP m0
MOV R0,[start+4]
RET
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VIPID Simulator – emulation of PRSG instruction
Simulator called VIPID : Courtesy School of Computer Engineering, Nanyang Technological University, Singapore
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Thank you for your attention and interest
 Any Questions?
 Contact
• Dr. David C. Dyer
School of Engineering
University of Warwick, Coventry, CV4 7AL, United Kingdom
 e‐mail
• d.c.dyer@warwick.ac.uk
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