Ver 1.0
Radiation-Hardened QUARD
DRIVER
B54LVDS031RH
Datasheet
Beijing Microelectronics Technology Institute
2011.3.20
Beijing Microelectronics Technology Institute
B54LVDS031RH
INDEX
1. Features ........................................................................................................................ 1
2. General Description ....................................................................................................... 1
3. Block Diagram ............................................................................................................... 2
4. Pin Description .............................................................................................................. 2
5. Pin Configurations ......................................................................................................... 3
6. Product Description ....................................................................................................... 4
7．Electrical Characteristic .................................................................................................. 4
7.1
ABSOLUTE MAXIMUM RATINGS ......................................................................................... 4
7.2
RECOMMENDED OPERATING CONDITIONS ......................................................................... 4
7.3
ELECTRICAL CHARACTERISTICS ........................................................................................... 5
8．Typical Application ......................................................................................................... 7
9．Package ......................................................................................................................... 8
10．Naming Rule ................................................................................................................ 9
11．Replaced Product.......................................................................................................... 9
2
Beijing Microelectronics Technology Institute
B54LVDS031RH
1. Features










>155.5 Mbps (77.7 MHz) switching rates
+350mV nominal differential signaling
5 V power supply
TTL compatible inputs
Ultra low power CMOS technology
5.0ns maximum, propagation delay
3.0ns maximum, differential skew
Radiation-hardened design：
- Total-dose: 300 krad(Si)
- Latchup immune (LET > 100MeV-cm2/mg)
Packaging options:
- 16-lead flatpack
Compatible with IEEE 1596.3SCI LVDS
Compatible with ANSI/TIA/EIA 644-1996 LVDS Standard
2. General Description
The B54LVDS031RH Quad Driver is a quad CMOS differential line driver
designed for applications requiring ultra low power dissipation and high data rates.
The device is designed to support data rates in excess of 155.5 Mbps(77.7 MHz)
utilizing Low Voltage Differential Signaling(LVDS) technology.The B54LVDS031RH
accepts TTL input levels and translates them to low voltage (340mV) differential
output signals. In addition, the driver supports a three-state function that may be
used to disable the output stage, disabling the load current, and thus dropping the
device toan ultra low idle power state.The B54LVDS031RH and companion quad line
receiver B54LVDS032RH provide new alternatives to high power pseudo-ECL devices
for high speed point-to-point interface applications. Quad Driver is a quad CMOS
differential line driver designed for applications requiring ultra low power dissipation
and high data rates. The device is designed to support data rates in excess of 155.5
Mbps(77.7 MHz) utilizing Low Voltage Differential Signaling(LVDS) technology.The
B54LVDS031RH accepts TTL input levels and translates them to low voltage (340mV)
differential output signals. In addition, the driver supports a three-state function that
may be used to disable the output stage, disabling the load current, and thus
dropping the device toan ultra low idle power state.The B54LVDS031RH and
1
Beijing Microelectronics Technology Institute
B54LVDS031RH
companion quad line receiver B54LVDS032RH provide new alternatives to high
power pseudo-ECL devices for high speed point-to-point interface applications.
3. Block Diagram
Figure.1. B54LVDS031RH Quad Driver Block Diagram
4. Pin Description
2
B54LVDS031RH
Beijing Microelectronics Technology Institute
Pin No.
1，7，9，
15
Name
DIN
2，6，10，
DOUT+
14
3，5，11，
DOUT13
4
EN
12
EN
16
VDD
8
VSS
Description
Driver input pin, TTL/CMOS
compatible
Non-inverting driver
output pin,
LVDS levels
Inverting driver output pin,
LVDS levels
Active high enable pin,
OR-ed
with EN
Active low enable pin,
OR-ed
with EN
Power supply pin, +5V +
10%
Ground pin
Figure.2. B54LVDS031RH Pinout & PIN DESCRIPTION
5. Pin Configurations
Pin No.
1
2
Symbol
DIN1
DOUT1+
3
DOUT1-
4
EN
5
DOUT2-
6
DOUT2+
7
8
DIN2
VSS
Function
INPUT DATA1
OUTPUT DATA1
POSITIVE
OUTPUT DATA1
NEGATIVE
Active high enable
pin
OUTPUT DATA2
NEGATIVE
OUTPUT DATA2
POSITIVE
INPUT DATA2
GND
Pin No. Symbol
9
DIN3
10
DOUT3+
3
11
DOUT3-
12
EN
13
DOUT4-
14
DOUT4+
15
16
DIN4
VDD
Function
INPUT DATA3
OUTPUT DATA3
POSITIVE
OUTPUT DATA3
NEGATIVE
Active low enable
pin
OUTPUT DATA4
NEGATIVE
OUTPUT DATA4
POSITIVE
INPUT DATA4
POWER
B54LVDS031RH
Beijing Microelectronics Technology Institute
6. Product Description
TRUTH TABLE
Enables
EN
Input
EN
Output
DIN
DOUT+
DOUT-
X
Z
Z
L
L
H
H
H
L
L
H
All other
combinations of
ENABLE inputs
The device is designed to support data rates in excess of 155.5 Mbps(77.7 MHz)
utilizing Low Voltage Differential Signaling(LVDS) technology. The B54LVDS031RH
accepts TTL input levels and translates them to low voltage (340mV) differential
output signals. In addition, the driver supports a three-state function that may be
used to disable the output stage, disabling the load current, and thus dropping the
device to an ultra low idle power state.
7．Electrical Characteristic
7.1 ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
LIMITS
VDD
DC supply voltage
VI/O
Voltage on any pin during
operation
Tstg
Storage temperature
TJ
Rth(J-C)
II
-0.3V ~ 6.0 V
Maximum junction
temperature
Thermal resistance,
junction-to-case3
DC input current
-0.3V ~ （VDD+0.3V）
-65℃ ~ +150℃
+150℃
10℃/W
±10mA
7.2 RECOMMENDED OPERATING CONDITIONS
4
B54LVDS031RH
Beijing Microelectronics Technology Institute
SYMBOL
PARAMETER
LIMITS
VDD
Positive supply voltage
4.5 V ~ 5.5 V
TA
Case temperature range
-55℃ ~ +125℃
VI
DC input voltage
0V ~ VDD
7.3 ELECTRICAL CHARACTERISTICS
PARAMETER
High-level input
voltage
Low-level input
voltage
High-level output
voltage
Low-level output
voltage
Input leakage current
Differential Output
Voltage
Change in Magnitude
of VOD for
Complementary
Output States
Offset Voltage
Change in Magnitude
of VOS for
Complementary
Output States
Input clamp voltage
Output Short Circuit
Currenta
Output Three-State
Current
Loaded supply current
drivers enabled
Loaded supply current
drivers disabled
Function test
SYMBOL
CONDITION
（-55℃≤ TA ≤ 125℃ ，VDD=5.0×
（1±10%）V）
LIMIT
UNIT
MIN
MAX
VIH
2.0
VDD
V
VIL
GND
0.8
V
VOH
RL=100Ω
―
1.6
V
VOL
RL=100Ω
0.9
―
V
IIN
VIN= VDDorVSS，VDD=5.5V
-10
10
μA
VOD
RL=100Ω
250
400
mV
△VOD
RL=100Ω
―
10
mV
1.12
5
1.37
5
V
―
25
mV
ICL =-18 mA
VIN=VDD,VOUT+=0V
或
VIN=0V,VOUT-=0V
VDD=5.5V, EN=0V ， EN =5.5V ，
VOUT-=0V or VDD
RL = 100Ω all channels
VIN = VDD or VSS (all inputs)
-1.5
—
V
-5.0
―
mA
-10
10
μA
―
25.0
mA
EN=0V， EN =VDD， VIN= VDD or 0V
―
10
mA
VOS
△VOS
VCL
IOS
IOZ
ICCL
ICCZ
RL=100Ω，VOS =( VOL+VOH) /2
RL=100Ω
f =77.7MHz
5
Beijing Microelectronics Technology Institute
B54LVDS031RH
Differential
Propagation Delay
tPHLD
Figure 3
―
5.0
ns
High to Low
Differential
Propagation Delay Low
tPLHD
Figure 3
―
5.0
ns
to High
Differential Skew
tSKD
tPLHD -tPHLD
―
3.0
ns
(tPHLD - tPLHD)
Channel-to-Channel
tSK1
―
3.0
ns
Skewb
Chip-to-Chip Skewc
tSK2
―
4.5
ns
Rise Time
tTLH
Figure 3
2.0
ns
Fall Time
tTHL
Figure 3
2.0
ns
Disable Time High to Z
tPHZ
Figure 4
―
10
ns
Disable Time Low to Z
tPLZ
Figure 4
―
10
ns
Enable Time Z to High
tPZH
Figure 4
―
10
ns
Enable Time Z to Low
tPZL
Figure 4
―
10
ns
Notes：
1、Devices are tested Devices are tested @ VDD = 4.5V&5.5V.
2、Current into device pins is defined as positive. Current out of device pins is defined as
negative. All voltages are referenced to ground except differential voltages.
3、Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50, tr < 6 ns,
and tf < 6 ns.
a
Output short circuit current (IOS) is specified as magnitude only, minus sign indicates
direction only.
b
Channel-to-Channel Skew is defined as the difference between the propagation delay of the
channel and the other channels in the same chip with an event on the inputs.
c
Chip to Chip Skew is defined as the difference between the minimum and maximum
specified differential propagation delays.
Figure.3. Driver Propagation Delay and Transition Time Waveforms
6
Beijing Microelectronics Technology Institute
B54LVDS031RH
Figure.4. Driver Three-State Delay Waveform
8．Typical Application
The B54LVDS031RH driver’s intended use is primarily in an uncomplicated
point-to-point configuration as is shown in Figure5. This configuration provides a
clean signaling environment for quick edge rates of the drivers. The receiver is
connected to the driver through a balanced media such as a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic
impedance of the media is in the range of 100Ω. A termination resistor of 100Ω
should be selected to match the media and is located as close to the receiver input
pins as possible. The termination resistor converts the current sourced by the driver
into voltages that are detected by the receiver. Other configurations are possible
such as a multireceiver configuration, but the effects of a mid-stream connector(s),
cable stub(s), and other impedance discontinuities, as well as ground shifting, noise
margin limits, and total termination loading must be taken into account.
Figure.5. Point-to-Point Application
7
Beijing Microelectronics Technology Institute
B54LVDS031RH
The B54LVDS031RH differential line driver is a balanced current source design.
A current mode driver, has a high output impedance and supplies a constant current
for a range of loads (a voltage mode driver on the other hand supplies a constant
voltage for a range of loads). Current is switched through the load in one direction to
produce a logic state and in the other direction to produce the other logic state. The
current mode requires (as discussed above) that a resistive termination be employed
to terminate the signal and to complete the loop as shown in Figure5. AC or
unterminated configurations are not allowed. The 3.5mA loop current will develop a
differential voltage of 350mV across the 100Ω termination resistor which the
receiver detects with a 250mV minimum differential noise margin neglecting
resistive line losses (driven signal minus receiver threshold (350mV - 100mV =
250mV)). The signal is centered around +1.125V (Driver Offset, VOS) with respect to
ground.
9．Package
B54LVDS031RH adopt 16-Lead Ceramic Quad Flat package, as in Figure 6 and
the size is listed in Table 1.
Figure.6. Package Outline
8
Beijing Microelectronics Technology Institute
B54LVDS031RH
Table 1 Package Size
Value（unit：mm）
Symbol
Min
Normal
Max
A
——
——
2.3
b
0.20
——
0.56
c
0.07
——
0.20
e
——
1.27
——
HE
13.72
——
25.4
Z
——
——
0.635
GE
——
——
7.7
LE
3
——
——
Q
0.13
——
0.90
10．Naming Rule
B54LVDS031RH
Design Type:
Radiation-Hardened
Device Type:
LVDS Quad Driver
Company code
11．Replaced Product
Device Type
B54LVDS031RH
Substituted Device Type
Aeroflex UT54LVDS031
9
Beijing Microelectronics Technology Institute
10
B54LVDS031RH