UNIVERSITY OF CALIFORNIA, BERKELEY
College of Engineering
Department of Electrical Engineering and Computer Sciences
Elad Alon
Homework #2 - Solutions
EECS141
Due Thursday, September 10, 5pm, box in 240 Cory
PROBLEM 1: VTC
In this problem we will analyze the noise margins for a chain of gates,
Fig. 1a. The VTC has four segments, where the two curved regions can be approximated
as quarter ellipses.
Figure 1.a.
Figure 1.b.
a) Add the DC voltage sources to Figure 1.a. that you would use for modeling noise
coupling to the input and output of gate M2. You should arrange these voltage
sources so that they would both impact the noise margin in the same way (i.e., if
the voltage source at the input decreases the noise margin, the voltage source at
the output should also decrease the noise margin).
Solution:
b) Determine the noise margins (as defined in lecture) for gate M2 when noise
couples only to its input. We want a numerical answer in Volts, not one based on
just looking at the VTC.
Solution:
To find the noise margin, we need to know VIL, VIH, VOL, and VOH for the
inverters. VOH and VOL are clear from the VTC:
VOH = 1.2V,VOL = 0V
To find VIL and VIH, we need to find the unity-gain points on the VTC. To find
these points, we’ll need the equations for the VTC in the regions 0.2V ≤ Vin ≤
0.6V and 0.6V ≤ Vin ≤ 1.0V.
For 0.2V ≤ Vin ≤ 0.6V, knowing that the curve is part of an ellipse, we have:
(x − 0.2) 2 (y − 0.4) 2
+
= 1.
0.4 2
0.8 2
To find the point of unity gain, we take the derivative (with respect to x) of the
above equation while keeping in mind that at the point we are looking
for ∂y /∂x = −1. Therefore:
2
2
(x − 0.2) −
(y − 0.4) = 0 , or
2
0.4
0.8 2
y = 4 x − 0.4 .
Now we plug this linear equation into the equation for the ellipse and we get the
solution:
x ≈ 0.38 .
So, VIL ≈ 0.38V .
Since the second ellipse is actually just a quarter circle, finding its unity gain
point is much easier. The quarter circle has a radius of 0.4V with its origin at
(Vin=1V, Vout = 0.4V), and so the point on the -135 degree line away from the
origin (which corresponds to the point with ∂y /∂x = −1) is at:
VIH = 1− 0.4 / 2 ≈ 0.72V .
Finally:
NMH = 1.2V – 0.72V = 0.48V
NML = 0.38V – 0.0V = 0.38V
c) Are the gates M4 and M5, whose VTCs are shown below in Figures 1.c and 1.d,
digital? Is the cascade of the two gates (Figure 1.e) digital? Why or why not? As
part of your answer, you should sketch the VTC of the cascade of the two gates.
Figure 1.c.
Figure 1.d.
Figure 1.e.
Solution:
M5 is clearly a digital gate, but M4 is a little trickier. M4 is “marginally” digital:
it has VOL = 0.6V, VOH = 1.2V, VIL = 0.6V, and VIH = 0.9V. In other words, the
circuit has zero NML, but nonetheless the gate is regenerative.
Interestingly, despite the fact that both M4 and M5 are digital, the cascade of the
two gates is not digital. The easiest way to prove this is to notice that for the VTC
traced out by the cascade of the two gates, VM < VIL. This means that the output
of a cascade of two such “gates” (where each gate is composed of the cascade of
M4 and M5) would always be “0” (no matter what the input is). The other way is
to do this is to draw the butterfly curve of the two gates and notice that the only
stable point is Vout(M5) = 0V.
d) [BONUS] If the cascade of M4 and M5 is digital, would any digital VTC for M5
also make the cascade digital? If the cascade is not digital, how would you
modify M5 to make it digital?
Solution:
To make the cascade of M4 and M5 a digital gate, we need to ensure that output
of the cascade reaches at least 0.9V instead of 0.6V. There are many possible
ways to achieve this, and any valid solution will receive full credit. Interestingly,
this can actually be achieved without changing the maximum gain of M5, but
rather by shifting its VM up to 0.7V (as shown on Fig. 1.f.). The VTC of the
cascade is shown on Fig. 1.g.
Figure 1.f.
Figure 1.g.
PROBLEM 2: DELAY
Recall that we have defined the propagation delay tp as the time between the 50%
transition points of the input and output waveforms. In this problem, we will explore how
the way you set up a simulation can affect the results you measure. Please turn in a
single spice deck that performs the simulations for parts b) through d). You can measure
the delays either by using .MEASURE statements in SPICE, or using WaveView.
However, if you use WaveView you should include plots of your waveforms.
a) Create a SPICE subcircuit for the inverter shown above. Use the following line in
your SPICE deck to obtain the correct NMOS and PMOS transistor models:
.LIB '/home/ff/ee141/MODELS/gpdk090_mos.sp' TT_s1v
To help get you started, we have provided the following example which
demonstrates the creation and usage of subcircuits in SPICE. The following input
creates an instance named X1 of the MYRC subcircuit, which consists of a 5kΩ
resistor and 10fF capacitor in parallel.
X1 TOP BOTTOM MYRC
.SUBCKT MYRC A B
R1 A B 5k
C1 A B 10f
.ENDS
Solution:
* Inverter SUBCKT Definition
.SUBCKT inv vdd gnd in out
Mp out in vdd vdd gpdk090_pmos1v W=2u L=0.09u
Mn out in gnd gnd gpdk090_nmos1v W=1u L=0.09u
.ENDS
(a)
(b)
(c)
(d)
Figure 2
b) Measure the average propagation delay of an inverter driving four copies of itself
(Fig. 2a). First apply a step input with a rise/fall time of 1 ns to the first inverter.
Then, repeat this measurement with a rise/fall time of 1 ps. Note: Use the M
(Multiply) parameter in the subcircuit instantiation to replicate the inverter.
Solution:
(See part e) for the spice deck)
1 ns: tpHL = 46.8ps, tpLH = 96.1ps, tpavg = 71.4ps
1 ps: tpHL = 18.2ps, tpLH = 18.9ps, tpavg = 18.6ps
c) Now create a chain of four inverters, each with a fanout of 4 (Fig. 2b). Measure
the average propagation delay of the second inverter in the chain when applying a
step input to the first inverter. Is the delay from part b) or part c) more realistic in
terms of what you might see on an actual IC? Explain the role of the first inverter
in the chain.
Solution:
(See part e) for the spice deck)
tpHL = 23.7ps, tpLH = 25.3ps, tpavg = 24.5ps
The delay from part c) is more realistic because the input is provided by the
output of the previous gate (first inverter in the chain) instead of a step function
with an arbitrary (i.e., unrealistic) rise/fall time.
d) Repeat part c) with the chain of four inverters, each with the fanout of 4 (Fig. 2c),
but this time add a 10 fF capacitor (which could be from a wire) between the
second and the third inverter. Compare this delay with the result from part c).
Solution:
(See part e) for the spice deck)
tpHL = 25.5ps, tpLH = 27.2ps, tpavg = 26.3ps
e) Now let’s use the circuit from Fig. 2d to see how connecting the capacitor in a
different way may have more or less impact on the delay. What value of C do
you need to use to make the delay of the circuit from Fig. 2d match the delay you
measured in part d)? Why might this capacitor be larger or smaller than the 10fF
used in part d)?
Solution:
To match the average delay of the two chains, C≈4.7fF. This capacitor is smaller
than the one in part d) because the two nodes that the capacitor is tied to are
switching in the opposite directions at approximately the same time. This means
that the total voltage swing across the capacitor is roughly twice what was in part
d) – i.e., the “Miller effect” is making this C look larger than it would if one of the
terminals was grounded (i.e., not moving).
tpHL = 25.5ps, tpLH = 27.2ps, tpavg = 26.3ps
SPICE Deck:
*** HW2 Problem 2 ***
.LIB '/home/ff/ee141/MODELS/gpdk090_mos.sp' TT_s1v
.PARAM vddval=1.2
* Inverter SUBCKT Definition
.SUBCKT inv vdd gnd in out
Mp out in vdd vdd gpdk090_pmos1v W=2u L=0.09u
Mn out in gnd gnd gpdk090_nmos1v W=1u L=0.09u
.ENDS
* Voltage Sources
V1 vdd 0 'vddval'
V2 vstep 0 PWL 0 0V 10p 0V 1010p 'vddval' 1210p 'vddval' 2210p 0V
V3 vstep2 0 PWL 0 0V 10p 0V 11p 'vddval' 211p 'vddval' 212p 0V
* Part B
Xinv1b vdd 0 vstep vout1b inv M=1
Xinv2b vdd 0 vout1b vout2b inv M=4
Xinv1b2 vdd 0 vstep2 vout1b2 inv M=1
Xinv2b2 vdd 0 vout1b2 vout2b2 inv M=4
* Part C
Xinv1c vdd 0 vstep2 vout1c inv M=1
Xinv2c vdd 0 vout1c vout2c inv M=4
Xinv3c vdd 0 vout2c vout3c inv M=16
Xinv4c vdd 0 vout3c vout4c inv M=64
* Part D
Xinv1d vdd 0 vstep2 vout1d inv M=1
Xinv2d vdd 0 vout1d vout2d inv M=4
Xinv3d vdd 0 vout2d vout3d inv M=16
Xinv4d vdd 0 vout3d vout4d inv M=64
C2 vout2d 0 10f
* Part E
Xinv1e vdd 0 vstep2 vout1e inv M=1
Xinv2e vdd 0 vout1e vout2e inv M=4
Xinv3e vdd 0 vout2e vout3e inv M=16
Xinv4e vdd 0 vout3e vout4e inv M=64
C vout2e vout1e1 4.7f
Xinv1e1 vdd 0 vstep2 vout1e1 inv M=1
Xinv2e1 vdd 0 vout1e1 vout2e1 inv M=4
Xinv3e1 vdd 0 vout2e1 vout3e1 inv M=16
Xinv4e1 vdd 0 vout3e1 vout4e1 inv M=64
* options
.option post=2 nomod
* analysis
.TRAN 0.1PS 20NS
* Part B Measurement
.MEASURE TRAN tpHLb TRIG V(vstep) VAL='vddval/2' RISE=1 TARG V(vout1b) VAL='vddval/2' FALL=1
.MEASURE TRAN tpLHb TRIG V(vstep) VAL='vddval/2' FALL=1 TARG V(vout1b) VAL='vddval/2' RISE=1
.MEASURE TRAN tpavgb PARAM='(tpHLb+tpLHb)/2'
.MEASURE TRAN tpHLb2 TRIG V(vstep2) VAL='vddval/2' RISE=1 TARG V(vout1b2) VAL='vddval/2' FALL=1
.MEASURE TRAN tpLHb2 TRIG V(vstep2) VAL='vddval/2' FALL=1 TARG V(vout1b2) VAL='vddval/2' RISE=1
.MEASURE TRAN tpavgb2 PARAM='(tpHLb2+tpLHb2)/2'
* Part C measurement
.MEASURE TRAN tpHLc TRIG V(vout1c) VAL='vddval/2' RISE=1 TARG V(vout2c) VAL='vddval/2' FALL=1
.MEASURE TRAN tpLHc TRIG V(vout1c) VAL='vddval/2' FALL=1 TARG V(vout2c) VAL='vddval/2' RISE=1
.MEASURE TRAN tpavgc PARAM='(tpHLc+tpLHc)/2'
* Part D measurement
.MEASURE TRAN tpHLd TRIG V(vout1d) VAL='vddval/2' RISE=1 TARG V(vout2d) VAL='vddval/2' FALL=1
.MEASURE TRAN tpLHd TRIG V(vout1d) VAL='vddval/2' FALL=1 TARG V(vout2d) VAL='vddval/2' RISE=1
.MEASURE TRAN tpavgd PARAM='(tpHLd+tpLHd)/2'
* Part E measurement
.MEASURE TRAN tpHLe TRIG V(vout1e) VAL='vddval/2' RISE=1 TARG V(vout2e) VAL='vddval/2' FALL=1
.MEASURE TRAN tpLHe TRIG V(vout1e) VAL='vddval/2' FALL=1 TARG V(vout2e) VAL='vddval/2' RISE=1
.MEASURE TRAN tpavge PARAM='(tpHLe+tpLHe)/2'
.END
PROBLEM 3: SWITCH MODEL
Figure 3
In this problem, you should use the simple switch model for MOSFETs with the
following characteristics: |VTP| = Vdd/3, VTN = Vdd/3, RNMOS = RPMOS.
a) Sketch the VTC of the circuit shown in Figure 3a where In is swept from 0V to
Vdd with R = 2*RNMOS.
Solution:
b) What happens if R is a lot bigger, say R = 10*RNMOS? Explain your answer!
Solution:
If the resistance in series with the PMOS is large, the switch model results in
neither of the possible states of the PMOS switch having a self-consistent
solution. Namely, for Vin > (2/3)*Vdd, if we assume that the PMOS in series with
the resistance R is on, we get that its |Vgs| is less than |VTP| because the output
would be very nearly 0V. This is a contradiction since the |Vgs| would need to be
greater than |VTP| for the switch to be on. Similarly, if you assume that the PMOS
switch is off, we once again get a contradiction since the source of that switch
would eventually go up to Vdd (with the output still at 0V). The good news is that
in both cases the output is very nearly 0V; any answer that explains the above
situation and gives Vout ≈ 0V will receive full credit.
For those interested in using the switch model to come up with a somewhat more
accurate (but still crude) estimate, a reasonable approach to take is to notice that
the voltage at the source of the PMOS has to basically be pinned at |VTP| = Vdd/3.
At this point the switch would hover right between being on and off, so we can
imagine that the switch would be on just long enough to pass the same average
current as flows through the large resistor. As an example, if R=10*RNMOS, then
the current flowing through that resistor is (Vdd-|VTP|)/10*RNMOS =
(1/15)*Vdd/RNMOS. This would imply that Vout = Vdd/15 (i.e., very nearly 0V).
a) For the input signal In given below, what amount of energy is pulled from the
power supply Vdd for the circuits shown in Figs. 3b and 3c respectively? Assume
RNMOS = RPMOS =2.5kΩ and R = 7.5kΩ.
Solution:
Circuit from Fig. 3b:
When In rises to 1V, the NMOS transistor in the inverter turns on and the PMOS
transistor turns off (the |VGS| of the PMOS is 0.2V, which is less than |VTP|).
Therefore, the capacitance at the output of the inverter is being discharged
through
the
NMOS
transistor,
and
the
time
constant
is τ1 = RN C = 2.5kΩ⋅10 fF = 25ps . Since In is 1V for 1ns, the load capacitance has
enough time to discharge completely. The same thing happens when In goes low
again – the capacitor gets completely charged back to Vdd. Therefore, the total
energy pulled out of Vdd due to charging the load capacitance is:
E1 = C ⋅ Vsw ⋅Vdd = C ⋅Vdd2 = 10 fF ⋅1.44V 2 = 14.4 fJ
Circuit from Fig. 3c:
In this case the time constants are also on the order of 10-100ps – i.e., still much
less than the input pulse length. However, the capacitance is not discharged
completely since there is a resistive divider when the NMOS is on. In other
words, when the NMOS is on, the capacitor only gets discharged to RN/(RN+R)
(instead of to 0V). Thus, the energy due to charging the load capacitance is:
⎛
RN ⎞
2
E1c = C ⋅ Vsw ⋅ Vdd = C ⋅ Vdd2 ⎜ 1 −
⎟ = 10 fF ⋅1.44V ⋅ 0.75 = 10.8 fJ
R
+
R
N
⎝
⎠
In addition to the energy required to charge the capacitor, during the time the
NMOS transistor is on we have current continuously flowing out of Vdd – i.e.,
there is static power dissipation. The power dissipation due to this current is
constant as long as the NMOS is on, and therefore the energy pulled from the
power supply is:
E 2 = Pdd ⋅1ns = Vdd
Vdd
⋅1ns = 144 fJ
RN + R
Therefore, the total energy for the circuit from Fig. 3c is:
E 3 c = E1c + E 2 = 154.8 fJ ,
which is clearly much greater than the CMOS inverter that doesn’t dissipate static
power to drive its output.