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Birck Nanotechnology Center
6-2014
Bulk-Like Laminated Nitride Metal/
Semiconductor Superlattices for Thermoelectric
Devices
Jeremy L. Schroeder
Birck Nanotechnology Center, Purdue University, jlschroe@purdue.edu
David A. Ewoldt
Purdue University
Reja Amatya
Massachusetts Institute of Technology
Rajeev J. Ram
Massachusetts Institute of Technology
Ali Shakouri
University of California - Santa Cruz; Birck Nanotechnology Center, Purdue University, shakouri@purdue.edu
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Schroeder, Jeremy L.; Ewoldt, David A.; Amatya, Reja; Ram, Rajeev J.; Shakouri, Ali; and Sands, Timothy D., "Bulk-Like Laminated
Nitride Metal/Semiconductor Superlattices for Thermoelectric Devices" (2014). Birck and NCN Publications. Paper 1637.
http://dx.doi.org/10.1109/JMEMS.2013.2282743
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Authors
Jeremy L. Schroeder, David A. Ewoldt, Reja Amatya, Rajeev J. Ram, Ali Shakouri, and Timothy D. Sands
This article is available at Purdue e-Pubs: http://docs.lib.purdue.edu/nanopub/1637
672
JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 23, NO. 3, JUNE 2014
Bulk-Like Laminated Nitride Metal/Semiconductor
Superlattices for Thermoelectric Devices
Jeremy L. Schroeder, David A. Ewoldt, Reja Amatya, Rajeev J. Ram, Member, IEEE,
Ali Shakouri, Member, IEEE, and Timothy D. Sands, Fellow, IEEE
Abstract— Bulk-like
thermionic
energy
conversion
devices have been fabricated from nanostructured nitride
metal/semiconductor superlattices using a novel lamination
process. 5-μm thick (Hf0.5 Zr0.5 )N (6-nm)/ScN (6-nm)
metal/semiconductor superlattices with a 12 nm period
were deposited on 100-silicon substrates by reactive magnetron
sputtering followed by a selective tetra methyl ammonium
hydroxide substrate etching and a gold-gold lamination process
to yield 300 μm × 300 μm × 290 μm microscale thermionic
energy conversion elements with 16,640 superlattice periods.
The thermionic element had a Seebeck coefficient of −120 μV/K
at 800 K, an electrical conductivity of ∼2500 −1 m−1 at 800 K,
and a thermal conductivity of 2.9 and 4.3 W/m-K at 300 and
625 K, respectively. The temperature dependence of the Seebeck
coefficient from 300 to 800 K suggests a parallel parasitic
conduction path that is dominant at low temperature, and the
temperature independent electrical conductivity indicates that
the (Hf0.5 Zr0.5 )N/gold interface contact resistivity currently
dominates the device. The thermal conductivity of the laminate
was significantly lower than the thermal conductivity of
the individual metal or semiconductor layers, indicating the
beneficial effect of the metal/semiconductor interfaces toward
lowering the thermal conductivity. The described lamination
process effectively bridges the gap between the nanoscale
requirements needed to enhance the thermoelectric figure
of merit ZT and the microscale requirements of real-world
devices.
[2013-0158]
Index Terms— Laminates, superlattices, thermionic energy
conversion, thermoelectric devices.
I. I NTRODUCTION
T
HERMOELECTRIC devices have been a promising approach for refrigeration and power generation applications since the 1950s. However, mainstream
Manuscript received May 21, 2013; revised August 12, 2013; accepted
September 15, 2013. Date of publication October 9, 2013; date of current
version May 29, 2014. This work was supported in part by the Office of Naval
Research under Contract N00014-09-0513 and in part by the DARPA/Army
Research Office under Contract W911NF0810347. Subject Editor D. Elata.
J. L. Schroeder was with the Birck Nanotechnology Center, Purdue University, West Lafayette, IN 47907 USA. He is now with Linköping University,
581 83 Linköping, Sweden (e-mail: jersc@ifm.liu.se).
D. A. Ewoldt was with Purdue University, West Lafayette, IN 47907
USA. He is now with Dow Corning, Midland, MI 48640 USA (e-mail:
david.ewoldt@dowcorning.com).
R. Amatya was with the Electrical Engineering Department, Massachusetts
Institute of Technology, Cambridge, MA 02139 USA. She is now with the
Massachusetts Institute of Technology Energy Initiative, Cambridge, MA
02139 USA (e-mail: ramatya@mit.edu).
R. J. Ram is with the Electrical Engineering Department, Massachusetts Institute of Technology, Cambridge, MA 02139 USA (e-mail:
rajeev@mit.edu).
A. Shakouri and T. D. Sands are with the Birck Nanotechnology Center, Purdue University, West Lafayette, IN 47907 USA (e-mail: shakouri@purdue.edu;
tsands@purdue.edu).
Digital Object Identifier 10.1109/JMEMS.2013.2282743
implementation of thermoelectric devices has been hindered by their low efficiency, which is related to the
dimensionless thermoelectric figure of merit ZT. The figure of merit ZT for a thermoelectric material is defined as
ZT = (S2 σ /κ)T, where S is the Seebeck coefficient (V/K),
σ is the electrical conductivity (−1 m−1 ), κ is the thermal conductivity (W/m-K), and T is the temperature (K).
Designing high-ZT materials requires manipulation of the
microstructure to achieve high S and σ while maintaining a
low κ, where κ = κelectronic + κlattice . Unfortunately, S, σ ,
and κ are coupled parameters that cannot be independently
altered, so despite decades of research the maximum ZT of
commercially available thermoelectric materials has remained
at ZT ≈ 1 [1]. Since the 1990s, nanoscale engineering of
thermoelectric materials has renewed interest in the field of
thermoelectric materials owing to nanotechnology’s promise
to enhance ZT. Nanotechnology allows partial decoupling of
the lattice thermal conductivity (κlattice ) from S and σ , with
reduced lattice thermal conductivity being the major reason for
reported ZT-enhancements in nanostructured thermoelectric
materials [2]. Nanostructures may also alter the trade-off
between S and σ in a beneficial way so as to enhance the
power factor (S2 σ ) [2].
One area of nanoengineered thermoelectric materials that
has been explored is heterostructures for thermionic refrigeration and power generation, most notably by Mahan [3],
Shakouri and Bowers [4], and Mahan and Woods [5].
The use of thermionic emission for thermoelectric applications allows for partial decoupling of κlattice , alters the
S-σ trade-off, and promises a new class of high ZT materials. Zebarjadi et al. demonstrated the potential of the
thermionic approach for creating thermionic power generators through experimental and theoretical work on ZrN/ScN
superlattices [6]. Zebarjadi et al.’s modeling results, which
were based on experimental results, demonstrated that ZT
values greater than 1 should be possible for high temperature (>1000K) applications. Besides the specific case of
ZrN/ScN superlattices, the broad class of transition metal
nitride materials is a promising materials system for high
temperature thermionic devices given their range of electrical and structural properties. Metallic (e.g. ZrN, HfN,
TiN), semiconducting (e.g. ScN, YN, LaN), and insulating (e.g. (Sc,Al)N) transition metal nitrides are all possible
within the class of materials adopting the rocksalt crystal
structure, readily allowing heterointegration of these materials. The transition metal nitrides also display high melting temperatures and excellent corrosion resistance, both
1057-7157 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
SCHROEDER et al.: BULK-LIKE LAMINATED NITRIDE METAL/SEMICONDUCTOR SUPERLATTICES
673
Fig. 1. Schematic process flow for the fabrication of laminated superlattice devices. The final laminate thickness is determined by the total number of bilayers
laminated in the final step.
properties advantageous for high-temperature waste heat
harvesting.
Assuming that the transition metal nitride metal/semiconductor thermionic emission approach proves feasible for
producing high ZT materials systems, the question arises: how
does one make a practical device from these thin film superlattices? The ZrN/ScN superlattices measured by Zebarjadi et al.
were only 1 μm thick, an impractical size for device applications. The optimum leg length for thin film power generators
is in the range of hundreds of micrometers due to the fact
that thin film thermoelectric devices operate in a heat sinklimited regime [7]. Unfortunately, the upper limit thickness
of as-deposited thin film thermoelectric materials by physical
vapor deposition (PVD) or chemical vapor deposition (CVD)
is practically determined by film stress and is usually less than
ten micrometers. In order to achieve a leg length of hundreds
of micrometers additional processing steps must be performed
to increase the overall leg length. Mayer and Ram [7] discuss
the possibility of stacking thin-film elements vertically with
the awareness that the stacking process will introduce thermal
and electrical parasitics. This paper discusses just such a
vertical stacking process, specifically a lamination process
flow for fabricating bulk-like thermoelectric legs from thin
film superlattices, and evaluates the parasitics introduced by
the lamination process.
The described lamination process offers the additional
advantage of creating segmented thermoelectric devices for
improved performance over an applied temperature gradient
[8]. The entire segmented leg could possibly be fabricated
from the same material system (i.e. transition metal nitride
metal/semiconductor multilayers) by alloying the metal and
semiconductor layers to change the barrier height, effectively
altering the optimal operating temperature of the superlattice
along the length of the element. Using the same materials system mitigates concerns related to thermal expansion mismatch
of dissimilar materials.
II. E XPERIMENTAL M ETHODS
All fabrication steps were conducted in the Birck Nanotechnology Center at Purdue University while device characterization was performed with collaborators at the Massachusetts
Institute of Technology, the University of California, Berkeley,
and the University of California, Santa Cruz.
This paper focuses on metal/semiconductor superlattices employing (Hf,Zr)N and ScN for the metal and
semiconductor layers, respectively. 5 μm thick nitride
metal/semiconductor superlattices of varying compositions
(i.e. HfN/ScN, (Hf0.5 Zr0.5 )N/ScN, and ZrN/ScN) with a nominal period of 12 nm (6nm metal/6nm semiconductor) were
deposited onto 500 μm thick 2” (100)-silicon substrates in a
DC reactive magnetron sputtering system (PVD Products, Inc.)
in a 5 mTorr argon (4 sccm) and nitrogen (6 sccm) ambient.
Targets of Hf (99.99%), Zr (99.99%), and Sc (99.999%)
were used with a target to substrate distance of 9 cm. The
base pressure was <1·10−7 Torr. It should be mentioned that
the nitride metal/semiconductor multilayer films deposited on
silicon substrates exhibited a uniaxial-textured polycrystalline
crystal structure with a superlattice structure within each grain.
We therefore refer to these structures as poly-superlattices.
Prior to deposition, the silicon substrates were cleaned by
sequential soaking steps in acetone and methanol followed
by a nitrogen drying step. The native oxide of silicon was
not removed prior to sputtering. After ramping under vacuum
to a growth temperature of 850 °C, all targets were presputtered under superlattice growth conditions for 3 minutes
prior to deposition. A 500 nm buffer layer with the same
composition as the metal layers in the superlattice (e.g. HfN,
(Hf0.5 Zr0.5 )N, or ZrN) was first deposited on the silicon
to reduce defect densities in the poly-superlattice structure.
Then, a 417 period (i.e. 5 μm) poly-superlattice structure was
deposited on the buffer layer. Target powers of Hf (200W),
Zr (200W), and Sc (100W) corresponded to deposition rates of
HfN (6nm/min), (Hf0.5 Zr0.5 )N (12 nm/min), ZrN (6 nm/min),
and ScN (3.3 nm/min). The poly-superlattice film was capped
with a 50 nm thick HfN or ZrN film to provide ample material
for ohmic contact deposition as well as to create an oxygen
diffusion barrier. The films were subsequently cooled under
vacuum to room temperature at 30 °C/min. Two identical polysuperlattice heterostructures deposited on 2” (100)-Si wafers
under identical growth parameters were then subsequently
used for the lamination process.
Fig. 1 shows the basic steps of the lamination process. First,
a 1.2 μm thick gold film with a 6 nm titanium adhesion
674
JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 23, NO. 3, JUNE 2014
Fig. 2. Scanning electron microscope images of a 25 μm superlattice bilayer after partial etching of the silicon substrates; (a) tilted low-magnification SEM
image and (b) side view SEM image of a 380 μm freestanding bilayer extending from partially etched silicon substrates; (c) close-up image of the freestanding
superlattice bilayer shown in image (b).
layer was deposited on the poly-superlattice films by magnetron sputtering in an argon ambient. The surfaces of the
poly-superlattice films were not pretreated prior to depositing
the gold bonding layers, which led to high electrical contact
resistivity values as discussed in the results section. Two
2” silicon wafers with 5 μm poly-superlattice films and
1.2 μm gold bonding layers were joined by face-to-face goldgold thermocompression bonding to create a stress-balanced
bilayer supported by rigid silicon substrates. Thermocompression bonding was conducted inside a class 100 cleanroom
using a Süss Sb6e bonder at 350 °C under a pressure of
3.3 MPa for 30 minutes. The bonded bilayer was then diced
into 5 mm × 5 mm samples via a DiscoDad H6 dicing
saw with a nickel/diamond composite blade. Samples that
remained bonded after the dicing procedure were qualitatively
determined to be well-bonded [9].
The 5 mm × 5 mm samples were dipped in buffered oxide
etch (6:1) for a few seconds to remove the native oxide layer
on the exposed surface of the silicon wafers. After rinsing in
water, the samples were placed in a bath of 25% tetra methyl
ammonium hydroxide (TMAH) at 80 °C to selectively etch
the silicon wafers. The etch rate of silicon was approximately
40 μm/hr, which corresponds to a total process time of
12.5 hours for a 500 μm thick silicon wafer [10]. (Hf,Zr)N thin
films act as an effective etch stop for TMAH so the samples
can be left in the TMAH solution for an extended period of
time after the silicon is fully removed without any detrimental
effects to the superlattice. It should be noted that ScN films
are etched by TMAH, but the (Hf,Zr)N layers effectively
protect the ScN. After removal of the silicon substrates, the
12 μm thick freestanding bilayer films were rinsed in water
followed by drying on a 70 °C hotplate. The freestanding
bilayers were subsequently handled with vacuum tweezers to
minimize mechanical damage. Fig. 2 depicts a representative
bilayer structure after the silicon has been partially removed.
Ti (6nm)/Au (1.2 μm) films were deposited on both sides of
each bilayer via two sequential sputter deposition steps. The
samples were laid flat on a horizontal platen, which facilitated
deposition across the entire bilayer surface. The metallized
bilayers were then ready for the final step of the lamination
process.
Twenty metallized bilayers were stacked on top of one
another using a custom designed alignment plate and joined
via gold-gold thermocompression bonding in a Süss Sb6e
bonder at 350 °C under a pressure of 14 MPa for 30 min.
A higher pressure was utilized for the 5 mm × 5 mm
freestanding bilayers compared to the 2” samples (14 MPa
vs. 3.3 MPa) due to equipment limitations of the bonder
(i.e. minimum force requirement due to small sample dimensions). The twenty bilayers were sandwiched between Pyrex
wafers during the bonding process so as to avoid any reactions
between the outer gold metallization and the silicon carbide
bonder chucks. The final laminated structure was 5 mm ×
5 mm × 290 μm thick and consisted of 200 μm of active
nanostructured thermoelectric material (16,640 periods) and
90 μm of gold bonding medium.
The 5 mm × 5 mm laminate was subsequently diced into
multiple 500 μm × 500 μm × 290 μm elements. The dicing
process smears gold across the poly-superlattice layers. The
excess Au on the sidewalls was removed via a polishing
process to prevent shorting between layers. Fig. 3 shows cross
sectional SEM images of a laminate before and after polishing.
The polishing procedure involved mounting a 500 μm ×
500 μm × 290 μm laminate between glass cover slips with a
thermoplastic polymer mounting adhesive (Crystalbond 509).
Two sides of the laminate were diced with a DiscoDad H6
dicing saw with a resin/diamond composite blade to reveal two
cross sectional surfaces that were sequentially polished with
9 μm, 3 μm, and 0.5 μm diamond pastes. The laminate was
remounted between glass cover slips and the two remaining
unpolished sides were diced and polished following the same
procedure. The final device was a 300 μm × 300 μm ×
290 μm polished laminate (Fig. 4), a thermoelectric element with dimensions approaching conventional bulk thermoelectrics. Electrical and thermal characterization of the final
device was conducted at MIT using a custom designed test
apparatus (i.e. Z-meter) [11].
III. PARASITIC E LECTRICAL AND T HERMAL
C ONTACT R ESISTANCE
Besides the proof of principle gold-gold laminate process
described in this paper, copper-copper bonding is being
explored as an alternative process due to copper’s lower
cost and ease of deposition. The parasitic electrical and
thermal resistances introduced by the bonding layers were
analyzed for a copper-copper bonding process. In order for
SCHROEDER et al.: BULK-LIKE LAMINATED NITRIDE METAL/SEMICONDUCTOR SUPERLATTICES
675
thickness for the implementation of copper bonding layers in
laminate devices. The similar electrical and thermal properties
of copper and gold make the parasitic analysis of copper
bonding layers relevant to the gold bonding layers used for
the laminates discussed herein.
Fig. 5 shows the linear relationship between electrical
contact resistivity and copper bonding layer thickness for
10% electrical and thermal parasitic resistances. The calculations for Fig. 5 assumed a 5 μm superlattice with an
electrical resistivity of 1 m-cm at an operating temperature
of 1000K (1 m-cm is a typical resistivity value for bulk
thermoelectrics), a Lorenz constant of 2.44·10−8 W-/K2 ,
a copper electrical resistivity of 1.7 μ-cm, and thermal
conductivities of the superlattice and copper of 3 W/m-K
and 350 W/m-K, respectively. The thermal interface resistance
was calculated from the electrical contact resistivity using the
Wiedemann-Franz law.
κ = σ LT
(1)
1
=
LT
(2)
Rt hermal
ρc
where κ = thermal conductivity (W/m-K), σ = electrical conductivity (−1 m−1 ), L= Lorenz constant (2.44·
10−8 W-/K2 ), T = temperature (K), Rthermal = thermal contact resistance (K/W), and ρc = electrical contact resistivity
(-m2). The lattice contribution to the thermal contact resistance was neglected; therefore the calculated thermal contact
resistance due to the electronic contribution provides an upper
bound on the parasitic thermal resistance. Since the electronic
and lattice contributions to the thermal contact resistance act in
parallel, the addition of the lattice contribution would simply
cause the parasitic thermal resistance to decrease.
Fig. 5 indicates that the electrical contact resistivity must
be <2·10−8-cm2 with a maximum copper bonding layer
thickness of ≈10 μm, which is a suitable thickness for accommodating surface particulates during the bonding process and
is a reasonable thickness to deposit via electrodeposition. The
electrical contact resistivity of <2·10−8 -cm2 is in the range
of a metal-metal contact. Since the superlattice structure begins
and ends with a metal nitride, it is possible to make a low
contact resistivity interface between the superlattice and metal
bonding layer (contact resistivity measurements are described
in the following section).
The superlattice of Fig. 5 was assumed to have a thermal
conductivity of 3 W/m-K. It should be noted that lower
superlattice thermal conductivity values, which are ultimately
desired for high-ZT thermoelectric materials, will relax the
thermal parasitic constraints, making the electrical parasitics
the limiting criteria when it comes to selecting a copper
bonding layer thickness. When the electrical parasitics dictate
the copper bonding layer thickness, much thicker copper
bonding layers are possible as long as the electrical contact
resistivity value is maintained <2·10−8-cm2 .
1
Fig. 3. Cross-sectional scanning electron microscope images of a superlattice
laminate (a) after dicing showing a smeared surface and (b) after polishing
with diamond lapping films. (c) high-magnification image of the white box
shown in (b) showing the gold-gold bond, the buffer layers, and part of the
superlattice films.
the metal/semiconductor superlattice laminate approach to be
viable, the parasitic electrical and thermal resistances must
be minimized. The parasitic resistance of the bonding layer
consists of both the bonding layer/superlattice interface and the
bulk properties of the bonding layer material. A rough estimate
for the maximum tolerable parasitic electrical and thermal
resistances is 10% of the total electrical and thermal resistances. The following discussion provides realistic boundaries
on the electrical contact resistivity and copper bonding layer
IV. R ESULTS AND D ISCUSSION
5 μm HfN/ScN, (Hf,Zr)N/ScN, and ZrN/ScN multilayers
have been deposited on both 100-Si and 100-MgO substrates.
The thickness of the multilayers was practically limited to
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JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 23, NO. 3, JUNE 2014
Fig. 4. Scanning electron microscope images of a diced and polished 300 μm × 300 μm × 290 μm (Hf0.5 Zr0.5 )N/ScN metal/semiconductor thermoelectric
element; (a) the laminate mounted on the end of a sewing pin and (b) higher magnification image resolving individual lamellae.
Fig. 5. Required electrical contact resistivity of the superlattice/bonding layer
contact as a function of copper bonding layer thickness for 10% allowable
electrical and thermal parasitics. Electrical contact resistivity values must
be equal to or less than the plotted values. The plot indicates that contact
resistivity values must be <2· 10−8 -cm2 and the copper bonding layer can
be relatively thick (i.e. 10-30 μm).
5 μm due to the effects of film stress with increasing film
thickness. XRD analysis indicates that these multilayers are
epitaxial on MgO whereas the multilayers deposited on silicon
can be described as uniaxial-textured polycrystalline superlattices, whereby the superlattice structure is within each grain.
This paper focuses mainly on silicon substrates for laminate
devices with brief mention of MgO as a suitable growth
substrate.
Fig. 6a shows representative 2θ -ω x-ray diffraction (XRD)
scans for 2 μm thick HfN/ScN, (Hf0.3 Zr0.7 )N/ScN, and
ZrN/ScN superlattices deposited on silicon substrates. Superlattice films used for laminate fabrication were not characterized by XRD so as to reduce the potential for surface
contamination prior to metallization and bonding. All three
films exhibit 200 uniaxial texture (100 metal nitride || 100 Si)
with 200 rocking curve full-width-at-half-maximum (FWHM)
values between 6° and 7° (not pictured). A small peak from
111-oriented grains is present in the HfN-based samples,
which is attributed to the initial growth of HfN on the silicon
surface. The intensity of the 111-reflection is only 6% and 2%
of the intensity of the 200-reflections for the HfN/ScN and
(Hf0.3 Zr0.7 )N/ScN superlattices, respectively. Asymmetric phi
scans of the 111-HfN reflection for the HfN/ScN superlattice
(Fig. 6b) indicate that the films are not epitaxial on silicon
(i.e. no in-plane relationship to substrate). Nitride superlattices
deposited on MgO substrates are of higher quality (rocking
curve FWHM values <1.4°) and are epitaxial [(100 HfN)
|| (100 MgO) and <010> HfN || <010 >MgO] as indicated by
asymmetric phi scans (Fig. 6c). The epitaxial growth on MgO
is due to the rocksalt crystal structure of both the MgO
substrate and nitride films despite the lattice mismatch between
the MgO substrate and HfN and ZrN films being relatively
large at 7.5% and 8.3%, respectively.
The 200 reflections of polycrystalline HfN, ZrN, and
ScN were expected at 39.818° (JCPDS file # 33-0592),
39.328° (JCPDS file # 35-0753), and 40.605° (JCPDS
file # 74-1215), respectively, while the 200 reflections
SCHROEDER et al.: BULK-LIKE LAMINATED NITRIDE METAL/SEMICONDUCTOR SUPERLATTICES
Fig. 6. (a) Normal 2θ -ω scan showing the preferred 200-orientation of
nitride superlattices deposited on 100-silicon substrates; asymmetric phi scans
show that nitride superlattices are (b) not epitaxial on 100-silicon [4 sharp
peaks are from silicon substrate] and (c) epitaxial on 100-MgO [4 peaks from
superlattice straddle the 4 sharp peaks from MgO substrate].
for the HfN/ScN, (Hf0.3 Zr0.7 )N/ScN, and ZrN/ScN
superlattices in Fig. 6a were at 39.900° 39.860° and
39.833° respectively. The single peak position for
the superlattices indicates that the ScN layers were
constrained by the metal nitride buffer layer and the
200-reflection position of the superlattice was close to the 200
reflections of HfN, (Hf0.3 Zr0.7 )N, and ZrN, not the position
of the 200-reflection for ScN. The lattice mismatches between
ScN and HfN and ZrN are 0.7% and 1.3%, respectively.
It should be noted that the additional peaks present in the
2θ -ω XRD scan (Fig. 6a) for the ZrN/ScN film are superlattice
reflections, whereby a period of 10.7 nm was calculated,
corresponding closely to the period measured by SEM images
(11.3 nm) and the nominal deposited superlattice period of
12 nm.
As described in the experimental methods section, the
lamination process involved complete removal of the substrate,
which required a selective substrate etching process. For silicon substrates, tetra methyl ammonium hydroxide (TMAH),
a common silicon etchant in the microelectronics industry,
was employed as the selective etchant. Etching tests on HfN,
ZrN, and ScN showed that HfN and ZrN are resistant to
etching in TMAH while ScN is etched. Given that ScN is
sandwiched between either HfN or ZrN layers, ScN layers are
not exposed to TMAH except along the edges, which has a
negligible effect. Therefore, HfN and ZrN were determined to
be effective etch stops for silicon substrate etching.
In the case of MgO substrates, sulfuric acid (1:1 H2 SO4 :
H2 O at 70 °C) was used to etch MgO (15 μm/hr). However,
677
HfN was discovered to etch in the sulfuric acid solution at a
rate >300 nm/hr, making it difficult to stop the etching process
before reaching the superlattice. TiN thin films, though, were
found to etch at a much slower rate of <4 nm/hr, making TiN
an effective etch stop. Therefore, employing a TiN buffer layer
prior to superlattice deposition allows MgO to be selectively
removed in sulfuric acid without affecting the superlattice
structure.
It was not until after the laminates had been fabricated and
characterized that the (metal nitride)/(bonding layer) interfaces
were determined to exhibit high electrical contact resistivity. The cause of the high electrical contact resistivity was
the formation of a thin 3-4 nm transition metal oxide and
oxynitride layer on the surface of the metal nitride [12]. XPS
analysis of ZrN and HfN thin films exposed to air revealed
the presence of oxygen at the surface. The oxide/oxynitride
layer was effectively removed via a short dip (2-3 seconds)
in buffered oxide etch (6:1). ZrN and HfN are both etched in
BOE at a rate of ∼1-2 nm/sec so extended exposure to BOE
is not recommended. XPS analysis of 3 second BOE-etched
ZrN and HfN films showed that the oxygen concentration was
reduced and the contact resistivity subsequently improved by
orders of magnitude.
In order to maintain electrical and thermal parasitics to a
minimum it is critical to have extremely low electrical contact
resistivity between the superlattice and bonding layers. Fig. 5
showed that the contact resistivity must be <2·10−8 -cm2 .
Low contact resistivity values are possible with metal-metal
contacts, but as described by the analytical model of Ueng
et al. characterizing such low contact resistivity values via the
transfer length method (TLM) is difficult due to the higher
relative measurement uncertainty associated with contacts
with extremely low contact resistivity [13]. Nonetheless, the
transfer length method was used to characterize the contact
resistivity of 10nm Ti/ 250nm Au contacts deposited on a
160 nm HfN thin film and a 160 nm ZrN thin film. The TLM
pattern consisted of a 300 μm wide thin film mesa with nine
100 μm × 285 μm contacts with gap spacings of 10, 20,
50, 100, 200, 500, 750, and 1000 μm. The HfN and ZrN
thin films were dipped in buffered oxide etch (BOE) for ten
seconds prior to contact deposition. The Ti/Au contacts on
HfN and ZrN exhibited electrical contact resistivity values
of 3.2·10−7 -cm2 and 5.1·10−8 -cm2, respectively. These
contact resistivity values are approaching the required value
of 2·10−8 -cm2 and are well within the large measurement
uncertainty for these TLM contact pattern dimensions. The
large uncertainty in the TLM measurements is due to the low
sheet resistance of the 160nm HfN (2.2 /) and 160nm
ZrN (1.0 /) films, the low actual contact resistivity, and
the large contact pads. Using the analytical model of Ueng
et al. the uncertainty can be reduced by optimizing the sheet
resistance (i.e. depositing thinner films) and the contact pad
geometry.
For example, the HfN thin film described above, with a
sheet resistance of 2.2 /, a 285 μm contact pad width,
and an assumed actual contact resistivity of 1·10−8 -cm2 ,
has a relative measurement uncertainty of almost 4000% due
to systematic errors (equation (40) from ref [13]). A true
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contact resistivity of 1·10−8 -cm2 could therefore be falsely
measured up to 4·10−7 -cm2 . This large relative uncertainty
for 2·10−8 -cm2 contacts can be reduced to 155% by
reducing the contact pad width to 10 μm and increasing the
sheet resistance to 10 /, which can be achieved with a 43
nm HfN thin film. Contact resistivity characterization of HfN
and ZrN films with optimized TLM patterns will be published
elsewhere, but initial results for 10 / HfN thin films with 10
μm contact pads indicate a contact resistivity of 1.3·10−7 cm2 . Further reduction of the contact resistivity will be
necessary, which requires additional studies of other contact
compositions (e.g. Cr/Au, Ti/Pt/Au, and in-situ copper).
The thermoelectric properties of the polished 300 μm ×
300 μm × 290 μm (Hf0.5 Zr0.5 )N/ScN laminate shown in
Fig. 5 as well as a polished 300 μm × 377 μm × 110 μm
HfN/ScN laminate (not pictured here) were characterized in
a Z-meter. Fig. 7 shows the Seebeck coefficient, electrical
conductivity, and thermal conductivity as a function of temperature for the two laminates (note: the temperature dependent
thermal conductivity of the 290 μm laminate could not be
measured due to apparatus changes that allowed the sample
to be measured up to 800K). The Seebeck coefficient at
room temperature is significantly lower than expected when
compared to the Seebeck of ≈−800 μV/K reported by
Zebarjadi et al. for a ZrN/ScN superlattice [6]. However,
the Seebeck coefficient rises with temperature to a value of
−120 μV/K at 800K, which is roughly the value of a good
thermoelectric material. The low Seebeck coefficient at room
temperature is likely caused by a metallic-like parallel parasitic
conduction path that is dominant at room temperature when
the superlattice is not in the thermionic regime. The parasitic
conduction path becomes negligible at higher temperatures
once the superlattice begins exhibiting thermionic behavior
with a resultant exponential rise in the electrical conductivity.
However, the electrical conductivity shown in Fig. 7b does
not exhibit an exponential rise with temperature; rather, it
is essentially independent of temperature, indicating that the
electrical resistivity of the laminate is dominated by the contact
resistance of the interfaces. It should be noted that the constant
electrical resistance is not the result of the parasitic resistance
of the Z-meter, which was independently measured and was
small compared to the laminate resistance.
The low electrical conductivity of the 290 μm laminate
can be attributed to the high contact resistivity at the eighty
ZrN/Au interfaces since the ZrN surfaces were not etched
in BOE prior to Ti/Au metallization (note: this sample was
fabricated prior to utilizing BOE etching to improve the
contact resistance). The resistance of the 290 μm laminate
was ≈1 , which can be related to 80 interfaces each with
a contact resistivity of 1·10−5 -cm2 , a reasonable contact
resistivity for a contact with a thin oxide layer at the interface.
The 110 μm laminate involved an in-situ Cu bonding layer
so only half of the layers had an interface oxide layer. The
resistance of the 110 μm laminate was ≈75 m, which can
be related to 17 interfaces each with a contact resistivity of
5·10−6 -cm2 . Processing is currently underway to fabricate
similar laminates with the BOE etching process in order to
reduce the interface parasitics.
Fig. 7. Temperature dependent measurements of (a) Seebeck coefficient;
(b) electrical conductivity; and (c) thermal conductivity for both a 290 μm
(Hf0.5 Zr0.5 )N/ScN and 110 μm HfN/ScN laminate. The temperature dependence of the Seebeck coefficient indicates a parasitic parallel conduction path
that is dominant at low temperature; the temperature independent electrical
conductivity indicates that the interface contact resistance is dominant; and
the thermal conductivity of the superlattice is significantly lower than the
constituent layer materials due to the large number of metal/semiconductor
interfaces.
Finally, Fig. 7c highlights the thermal conductivity of
the laminates since low thermal conductivity elements are
critical for high-efficiency thermoelectric devices. The thermal conductivity of the 110 μm laminate increases from
SCHROEDER et al.: BULK-LIKE LAMINATED NITRIDE METAL/SEMICONDUCTOR SUPERLATTICES
2.4 W/m-K at 300K to 4.3 W/m-K at 625K, an expected result
due to the additional electronic contribution from thermionic
emission. The 2.4 W/m-K room temperature thermal conductivity of the HfN/ScN superlattice is much lower than the constituent layer materials (HfN = 34 W/m-K; ScN = 22 W/m-K)
due to scattering at the metal/semiconductor interfaces [14].
The 300K thermal conductivity of the laminate as measured by the Z-meter matches well with other 300K thermal conductivity measurements. The thermal conductivity of
the 290 μm (Hf0.5 Zr0.5 )N/ScN laminate measured by DC
measurement and thermoreflectance was 2.88 W/m-K and
2.94 W/m-K, respectively. In addition, room temperature 3-ω thermal conductivity measurements of separate
2 μm ZrN/ScN, (Hf0.3 Zr0.7 )N/ScN, and HfN/ScN superlattices showed thermal conductivity values of 5.2 W/m-K,
4.8 W/m-K, and 3.5 W/m-K, respectively. The comparable
thermal conductivity values of the 2 μm superlattice films
and the 290 μm laminate with 80 interfaces indicate that the
laminate structure is not dominated by thermal parasitics, but
the non-BOE-etched laminate interfaces do currently reduce
the thermal conductivity by ≈33-40%. Implementing lower
contact resistivity BOE-etched interfaces will lower the thermal parasitic of the interface with a concomitant rise in the
overall thermal conductivity of the laminate (i.e. the thermal
conductivity of laminates should closely match the thermal
conductivity of superlattice thin films).
V. C ONCLUSION
A process flow for fabricating bulk-like thermoelectric
elements
from
nanostructured
thin
film
nitride
metal/semiconductor superlattices was demonstrated. The
process bridges the gap between nanoscale dimensions
required for novel high-ZT materials and microscale
dimensions required for real-world devices. The demonstrated
lamination process is promising for future characterization
of metal/semiconductor superlattices as well as scale-up
potential. The nitride metal/semiconductor superlattices
also utilize earth-abundant materials, a distinct advantage
compared to thermoelectric materials based on earth-scarce
tellurium.
ACKNOWLEDGMENT
The authors would like to acknowledge J. P. Feser for
3-ω thermal conductivity measurements conducted at the University of California, Berkeley, and D. Zemlyanov for XPS
analysis conducted at Purdue University. Laminate fabrication
was conducted at the Birck Nanotechnology Center at Purdue
University.
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Jeremy L. Schroeder received the B.S. degree in
materials science and engineering from The Ohio
State University, Columbus, OH, in 1998, the M.S.
degree in materials science and engineering from
the University of California, Berkeley, CA, in 2002,
and the Ph.D. degree in materials engineering from
Purdue University, West Lafayette, IN, in 2012.
He was a Senior Research Associate at Purdue
University from 2003 to 2012 and he is currently
a postdoctoral researcher at Linköping University,
Linköping, Sweden. His current research interests
are in nitride-based thin film coatings for high temperature thermoelectrics
and hard coating applications.
David A. Ewoldt received the Ph.D. degree in
materials engineering from Purdue University, West
Lafayette, IN, in 2011.
He is currently an Epitaxy Specialist at Dow Corning in Midland, MI. His research interests include
thin film nucleation and growth and metrology.
Reja Amatya received the B.S. degree in engineering science from Smith College, Northampton,
MA in 2005, and the M.S. and the Ph.D. degrees
in electrical engineering from the Massachusetts
Institute of Technology, Cambridge, MA in 2008 and
2012, respectively.
She was a Graduate Student Researcher at MIT
from 2005 to 2012, and she is currently a Postdoctoral Associate at the MIT Energy Initiative,
Cambridge, MA. Her research interests are in heat
transfer analysis and characterization for power generation utilizing solar based thermoelectrics for remote applications mainly in
emerging economies, and power systems involving renewable energy within
micro-grid settings.
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Rajeev J. Ram received the B.S. degree in applied
physics from the California Institute of Technology,
Pasadena, CA, in 1991 and the Ph.D. degree in electrical engineering from the University of California,
Santa Barbara, CA, in 1997.
He is currently a Professor at the Massachusetts
Institute of Technology, Cambridge, MA. His
research focuses on physical optics and electronics,
including the development of novel components and
systems for communications and sensing, microscale biotechnology hardware, and studies of fundamental interactions between electronic materials and light.
Ali Shakouri received the Ph.D. degree from the
California Institute of Technology, Pasadena, CA, in
1995.
He is currently a Professor of electrical engineering and the Mary Jo and Robert L. Kirk Director of
the Birck Nanotechnology Center at Purdue University, West Lafayette, IN. His current research is on
nanoscale heat and current transport in semiconductor devices, high resolution thermal imaging, micro
refrigerators on a chip, and waste heat recovery. He
is also working on a new sustainability curriculum
in collaboration with colleagues in engineering and social sciences. He has
initiated an international summer school on renewable energy sources in
practice. He is the director of the Thermionic Energy Conversion center, a
multi-university collaboration aiming to improve direct thermal to electric
energy conversion technologies.
Prof. Shakouri received the Packard Fellowship in Science and Engineering
in 1999, the NSF Career award in 2000, and the UCSC School of Engineering
FIRST Professor Award in 2004.
Timothy D. Sands (M’02–SM’08–F’10) received
the B.S. degree in engineering physics at the University of California, Berkeley, CA, in 1980, and
the M.S. degree and the Ph.D. degree in materials
science at the University of California, Berkeley,
CA, in 1981 and 1984, respectively.
He was a Member of Technical Staff and a
Research Group Director at Bell Communications
Research, Inc. in Red Bank, New Jersey from 1984
until 1993 when he joined the faculty of the Department of Materials Science & Engineering at UC
Berkeley. In 2002, he joined the faculty at Purdue University in West
Lafayette, Indiana, USA as the Basil S. Turner Professor of Materials
Engineering and Electrical & Computer Engineering. He was the Mary Jo
and Robert L. Kirk Director of the Birck Nanotechnology Center in Purdue’s
Discovery Park from 2006 until 2010, when he became Provost, his current
position. From July of 2012 until January 2013, he served as Acting President
of Purdue University. He has published over 250 papers and is an inventor
on 16 patents in the fields of semiconductor processing and nanostructured
energy conversion materials and devices.
Prof. Sands is also a Fellow of the Materials Research Society (MRS) and
a Charter Fellow of the National Academy of Inventors (NAI).