IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 8, AUGUST 2008
923
Abstract —This letter proposes the use of a simplified single-step thru deembedding method for the multiport characterization of
MOSFETs. Compared with other methods, it takes up less chip area and requires less measurement steps, both particularly important factors for multiport characterization. The thru method is compared with the multiport open–short method. Measurements of a four-port MOSFET, with corresponding deembedding structures, are used to extract the MOSFET equivalent circuit elements over bias. These results show the validity and usefulness of multiport measurements and the thru deembedding method for
MOSFET characterization.
Index Terms —Deembedding, equivalent circuits, MOSFETs, multiport measurements.
M
I. I
NTRODUCTION
ULTIPORT measurements have facilitated the characterization of the multiterminal devices commonly used in RFICs, with accuracy and efficiency that could not be provided by two-port measurements. MOSFETs are an example of a multiterminal device, with gate, drain, source, and body terminals. Two-port measurements render the determination of parameters related to the body node very difficult, because it is usually tied to the source (in the case of common-source test structures). Recently, four-port measurements have been used to extract a complete substrate network model [1] and to directly extract equivalent circuit models accurate to beyond
50 GHz [2].
In order for these devices to be characterized, they need to be embedded within pads and interconnects. Therefore, one critical step in device characterization is deembedding, which is the process of removing the influence of the pads and interconnects from measurements [3]. This moves the measurement reference plane from the probe tips to the device terminals.
Deembedding methods for two-port structures are now well established. A multiport deembedding method, which uses pad and thru dummy structures, was applied to transformer characterization [4]. This method allows deembedding that is scalable with interconnect length, provided that the interconnects are straight (which may not be the case in multiport test structures,
Fig. 1.
Example four-port MOSFET and corresponding thru test structures.
The drain, gate, source, and body connections to the MOSFET are labeled.
see Fig. 1). The open–short deembedding method [3], which also uses two dummy structures, can be easily applied to multiport measurements. More advanced methods, such as the threestep method, could be used for greater accuracy but require even more dummy structures [5]. However, test structures with more than two ports use significant silicon estate. In addition, multiport measurements are more sensitive to probe placement and other measurement errors; thus, each probe placement increases the chances of measurement error. For these two reasons, it is desirable to reduce the number of required deembedding dummy structures.
This letter extends the use of the thru deembedding method
[6], which uses only one dummy structure, to multiport measurements. This method, along with multiport open–short, is introduced in Section II. Section III describes the structures and measurements used to verify the deembedding procedure. The residual coupling capacitances between the interconnects near the device are not accounted for in the thru method; therefore, the significance of these residual components was determined.
A MOSFET was characterized, including a determination of the extrinsic parasitics and the capacitances and conductances over bias using four-port measurements. The open–short and thru deembedding methods are compared. Finally, the conclusion is drawn in Section IV.
Manuscript received January 22, 2008. This work was supported by the
TSRP Project 0421140045, sponsored by A
∗
STAR, Singapore. The review of this letter was arranged by Editor E. Sangiorgi.
The authors are with the Institute of Microelectronics, Agency for Science,
Technology and Research (A
∗
STAR), Singapore 117685 (e-mail: james_b@ ieee.org; issaoun@yahoo.com; subhash@ime.a-star.edu.sg; linfj@ime.a-star.
edu.sg).
Digital Object Identifier 10.1109/LED.2008.2001175
II. M ULTIPORT D EEMBEDDING
An example MOSFET four-port test structure is shown in
Fig. 1. A common two-port deembedding method, which is also easily applicable to multiport measurements, is the open–short
0741-3106/$25.00 © 2008 IEEE

924 IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 8, AUGUST 2008 method [3]. Two dummy structures are fabricated—an open and a short. Each of these takes up the same area as the device test structure. The three structures are measured, and the device under test (DUT)
Y dut
Y -parameters are then calculated using
= ( Y meas
−
Y open
)
−
1 −
( Y short
−
Y open
)
−
1
− 1
.
(1)
The dimension of each of the Y -matrices in (1) corresponds to the number of ports.
Another deembedding method that is suitable for application to multiport measurements is the one-step thru method [6].
It was proved to be useful for two-port noise modeling [7] because of its simplicity and its requirement of only one dummy structure. This leads to the following two advantages:
1) reduction of wafer space required for dummy structures;
2) reduction in the number of measurements required to characterize and deembed each device.
These two factors are particularly important for multiport measurements, because the structures are a lot larger due to the larger number of pads, and the measurement errors are more severe due to the increased number of contacts required.
The thru deembedding structure uses two of the interconnects used in the device test structure connected back-to-back as in
Fig. 1. The assumed parasitic model is similar to the open–short model, consisting of a shunt admittance cascaded with a series impedance. If the Y -parameters of the two-port thru are Y t
, the
DUT Y -parameters may be found by [6] y shunt z series
= − 1 / ( Y t
( 1 , 2 ) + Y t
( 2 , 1 ))
Y dut
= ( Y meas
− y shunt
I )
−
1 − z series
I
− 1 where is the identity matrix with dimensions corresponding to the number of ports, and scalars.
I
= ( Y t
( 1 , 1 ) + Y t
( 1 , 2 ) + Y t
( 2 , 1 ) + Y t
( 2 , 2 )) / 2 (2)
Only one two-port thru is needed for a multiport structure if all the interconnects from the pads to the device terminals are identical, because y shunt and z series are the same for each port. This is not difficult to achieve in most cases and is true for the test structure in Fig. 1. If the interconnects or pads are not identical, multiple thru structures can be used to characterize and then deembed the shunt and series parasitics introduced at each respective port. However, the advantages of this thru deembedding method (reduced wafer usage and measurement steps) will no longer hold if more than two thru structures are required.
If the DUT is very wide ( > 10 µ m), the thru arrangement used in Fig. 1 will not be suitable. The thru would need to be shorter than allowed by the GSGSG probe pitch. In this case, the bottom half of the thru could be mirrored about the y -axis and connected between two east–west GSG probes, with minimal impact on the results for ground-shielded structures.
III. M y shunt and z series
EASUREMENTS
(3)
(4) are the complex
A set of test structures was fabricated using a 0.18µ m
CMOS process with six metal layers. The test structures had a ground plane at the bottom metal layer, minimizing coupling to the lossy substrate [8]. The DUT was a 64 finger nMOS device with a finger width of 5 µ m. The device was floating, with the drain, gate, source, and bulk terminals connected to four pads using identical interconnects. The thru test structure consisted of two of these identical interconnects connected back-to-back with a pad on each end. These two test structures are shown in
Fig. 1. Short and open dummy structures were also fabricated so that multiport thru deembedding could be compared with the open–short method.
A. Deembedding
After the thru was measured, y shunt and z series were computed from (2) and (3). The shunt admittance y shunt had negligible conductance because the ground plane isolates the interconnects from the substrate [8]. The shunt capacitance was relatively frequency independent, approximately 18 fF up to
50 GHz. The series resistance (calculated from the real part of z series
) increased with frequency and was less than 1 Ω up to
50 GHz. The series inductance decreased from approximately
50 pH at low frequencies to 45 pH at 50 GHz.
In contrast to open–short, the thru deembedding method ignores the coupling between the interconnects near the device.
In order to assess the coupling, the open structure was measured. The open layout consisted of the complete structure in
Fig. 1 with only the DUT removed; thus, it included the vias to connect the interconnects (on metal 6) to the MOSFET terminals (on metals 1 and 2). By deembedding the shunt and series parasitics from the Y -parameters of this open structure using
(4), the residual coupling capacitances at the device end of the interconnects can be found. All the capacitances were found to be less than 4 fF up to 50 GHz and can be considered negligible compared with the MOSFET capacitances. The magnitudes of the coupling capacitances were consistent with the device layout in Fig. 1, increasing confidence in the measurements and deembedding method. Note that if the device is small, and the corresponding gaps between the interconnects are small, the parasitic coupling capacitances will be more significant compared with the device capacitances. In this case, the extra open deembedding structure may be needed to deembed the effect of the capacitances.
To verify the deembedding method, the Y -parameters of the zero-biased MOSFET were computed from the four-port measurements. Due to space limitations, all of the four-port
Y -parameters cannot be shown here. The imaginary parts of
Y
11 and Y
12 are shown in Fig. 2. Similar results were obtained for the other Y -parameters.
In Fig. 2, the raw and deembedded data are compared. There is a significant resonance in the raw data near 25 GHz due to the series inductance of the interconnects. This resonance is removed after deembedding. The results from open–short and the new thru deembedding method are very similar up to
30 GHz, following the expected straight line behavior, corresponding to the cold FET device capacitances. There is still a resonance in the deembedded data at higher frequencies at around 40 GHz, due to the device wiring inductances. This is removed after the extrinsic parasitics of the device are removed,

BRINKHOFF et al.
: MULTIPORT THRU DEEMBEDDING FOR MOSFET CHARACTERIZATION 925
Fig. 2.
Imaginary part of Y
11 and Y
12 of the MOSFET at zero bias. The lines are the raw measured results. The square symbols are the open–short deembedding results. The cross symbols are the results using thru deembedding.
Fig. 4.
MOSFET capacitances, extracted from measurements over gate bias with a drain voltage of 1.2 V. The results use (points) open–short and (lines) thru deembedding.
Fig. 3.
Body resistance of the MOSFET extracted from measurement. The results for no deembedding, open–short deembedding, and thru deembedding are compared. The solid line is the average of the thru deembedding results.
as explained in Section III-B. The resonance of the open–short deembedded data has a higher Q than the thru deembedded data.
The reason for this is that the open–short deembeds an artificially higher series resistance than that extracted by the thru method, because of the extra ground plane and via resistance included in the open–short series parasitics. The series resistance deembedded by the thru method only includes that of the line, as desired.
resistance and cause it to be frequency dependent. The results from open–short and thru deembedding are very close. The thru deembedding results are flat from 30 to 50 GHz. This result further increases confidence in the multiport deembedding.
The other extrinsic resistances and inductances were extracted, using [2], with similar results.
The four-port S -parameters of the MOSFET were measured over a grid of biases. After the extrinsic resistances and inductances have been removed by subtracting their Z -parameters from the device Z -parameters, the device capacitances and conductances can be determined [2]. The capacitances and conductances were relatively flat over frequency up to 10 GHz.
The average over that frequency range was taken to determine the values for each component. Finally, a table of the component values in the MOSFET equivalent circuit over the grid of drain and gate biases was obtained. This equivalent circuit extraction method allows accurate prediction of the device
S -parameters up to 50 GHz, even before any optimization is used [2]. Having four-port data allowed all of the components to be independently and easily extracted, including components associated with the body terminal.
An example of the extracted device capacitances is shown in
Fig. 4. The capacitances are shown as a function of the gate voltage with a drain voltage of 1.2 V. The capacitances follow the expected trends. The results from thru and open–short deembedding are compared and are very similar.
B. MOSFET Characterization
Following the procedure in [2], the equivalent circuit of the
MOSFET can be found from its four-port Y -parameters. First, the bias-independent series extrinsic parasitics are determined from measurements of the MOSFET at zero bias. These parasitics are related to the interconnect wiring and the diffusions.
An example of one of these components, the body resistance, is shown in Fig. 3. The extraction is carried out at high frequencies, where the series impedances become significant and measurable in the presence of the MOSFET capacitances. The average value of the measurements across frequency gives the extracted value.
In Fig. 3, the results with no deembedding, open–short deembedding, and thru deembedding are shown. It can be seen that it is difficult to extract the resistance if no deembedding is used, because the pad and interconnect parasitics add to the
IV. C ONCLUSION
This letter discussed the extension of thru deembedding to multiport measurements. The method was verified by comparison with the open–short method. The thru method allows accurate deembedding to be achieved using only one dummy structure, which leads to reduced wafer space and requires less measurements. Good results for MOSFET equivalent circuit characterization have been achieved.
CKNOWLEDGMENT
The authors would like to thank Dr. J. Shi and Dr. Y. Z. Xiong for their support.
A

926 IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 8, AUGUST 2008
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