1
Graph theoretical algorithms for index reduction for
charge/flux oriented Modified Nodal Analysis
Simone Bächle, Falk Ebert
Abstract— The numerical simulation of very large scale integrated circuits is an important tool in the development of
new industrial circuits. A problem in circuit simulation is that
the model equations lead to differential algebraic equations
(DAEs), that may have an index larger than one, i.e., they may
contain so-called hidden constraints. The increased index has
numerous disadvantages for the numerical treatment of circuit
DAEs. The determination of the hidden constraints can be done
by investigating the circuit topology. Until now, this information
has only been used for the consistent initialization of the circuit
equations. A recent suggestion has been to reduce the index of
the circuit DAE in order to improve its numerical behaviour.
This paper will describes graph theoretical methods that lead to
constraints in a favorable formulation. Furthermore, the index
reduction via minimal extension will be performed for circuit
DAEs, using these constraints.
IMULATION of electrical circuits is a commonly used
tool to test new electrical circuits prior to producing an
actual prototype. Especially in chip design it is important to
be able to have a quick and reliable method for simulating
the behaviour of a circuit. But the respective circuits tend to
contain millions of elements, thus making simulation difficult,
just because of the sheer size of the problem.
The main methods for the simulation of circuits are the
Modified Nodal Analysis (MNA), the charge-/flux-oriented
MNA (MNA c/f) and the Sparse Tableau Approach (STA),
cf. [1]. Kirchhoff’s Laws and branch constitutive relations
(BCR) are set up to form a system of equations describing the
important properties of the circuit, e.g., voltages and currents.
As this system contains differential relations as well as algebraic ones, it is a ’Differential-Algebraic-Equation’ (DAE). A
well known problem of DAEs is that besides obvious algebraic
relations, they may contain so-called hidden constraints that
are revealed only by differentiating certain equations or parts
thereof. The number of differentiations is closely related to a
concept called the ’index’ of a DAE, cf. [2]–[4]. There exist
many different concepts to assign an index to a DAE, like the
tractability index, see [3], and the strangeness index [4], which
have been shown to be strongly related for linear time-varying
systems of t-index ≤ 3 (or s-index ≤ 2), cf. [5]. In the course
of this paper, the differential index (d-index) [2] will be used.
The hidden constraints in the case of the MNA and the MNA
c/f have been determined, see [6], and in [7] it has been shown,
how they can be obtained without algebraic transformations of
the circuit equations by only using information contained in
S
Manuscript created January 23, 2006.
Institute of Mathematics, Technical University of Berlin, MA 4-5 Straße
des 17. Juni 136, 10623 Berlin, Germany, email: baechle@math.tu-berlin.de
Institute of Mathematics, Technical University of Berlin, MA 3-3 Straße
des 17. Juni 136, 10623 Berlin, Germany, email: ebert@math.tu-berlin.de
Supported by the DFG Research Center M ATHEON ”Mathematics for key
technologies” in Berlin.
the topology of the circuit. The information obtained in this
way until now has mainly been used to determine consistent
initial values. Recently, a concept called minimal extension,
see [8], has been suggested to include the hidden constraints
into the process of integration, see [9]. The DAE obtained in
this way is of d-index 1, while typically large scale systems are
of index 2. For DAEs of d-index higher than 1, the numerical
solution leads to difficulties, i.e., they are usually more costly
to solve, while accuracy might suffer as well.
The algorithms proposed here are based on the results of
the topological index analysis. As the topological structures
leading to a d-higher index are in general not unique, we will
use the additional freedom to determine the arising hidden
constraints in a ’favorable’ way. This aims at determining
equations that can be incorporated into the circuit DAE without
additional expensive algebraic transformations. This approach
has several advantages. First, the involved algebraic transformations are mainly permutations that do not incur roundoff
errors. Second, the resulting DAE is of d-index 1 and thus
better suited for numerical integration. Moreover, the resulting
constraints can be incorporated into the original DAE in a way
that preserves the special structures of the DAE.
The paper is organized as follows. In Section I a brief
introduction to circuit modeling will be given. Necessary
graph theoretical notions will be defined. Section II will deal
with the concept of index reduction by minimal extension.
Algorithms will be presented to determine hidden constraints
from the circuit topology. It will be proved that the constraints
determined in this way can effectively be used to reduce the
index of the circuit DAE. In Section III, the properties of the
new algorithms will be demonstrated using two examples.
I. M ODELING
OF A CIRCUIT
A. Description of the circuit topology
The behaviour of an electrical circuit is defined by the
elements which it contains and the way in which the elements
are connected with each other. This relation of the elements
can best be described in terms of graph theory. Thus, some
basic definitions concerning the description of general graphs
will be given here. These concepts will be linked to the
description of the topology of a circuit.
Definition 1.1 (Oriented graph): An oriented graph G is a
pair (N, B), where N = {n1 . . . nN } is a finite set and B a
binary relation on N. The elements nk , k = 1, . . . N of N are
called nodes. The elements bk1 ,k2 = < nk1 , nk2 >, k1 , k2 ∈
{1, . . . N } of B are called branches. We also denote G as
G(N, B).
2
Definition 1.2 (Subgraph): Consider a connected graph
e = G(
e N,
e B)
e of G is a graph
G = G(N, B). A subgraph G
e
e
such that N ⊆ N and B ⊆ B.
Circuits can be interpreted as oriented graphs when the
elements are considered as the branches. The orientation of
a branch is given by the direction of the branch current. The
nodes are placed at the ends of the branches.
Consider the branch bk1 ,k2 = < nk1 , nk2 >. The branch is
incident with the nodes nk1 and nk2 . bk1 ,k2 leaves node nk1
and enters node nk2 .
Definition 1.3 (Incidence matrix): Consider an oriented
graph G and let the branches be numbered arbitrarily, e.g.
B = {b1 , . . . , bB }. The incidence matrix A ∈ RN ×B of G
is given by

 1
akl = −1

0
and it is well
if branch l leaves node k,
if branch l enters node k,
if branch l is not incident with node k,
known that rank A = N − 1. [10]
If the incidence matrix of a circuit is formed considering
all branches of the circuit and all its nodes except a reference
node, this results in a reduced incidence matrix which has full
row rank. In the following section, we will only consider this
reduced incidence matrix and denote it by A.
Even though the incidence matrix is the most common way
to describe the topology of a circuit, it is not the only one. In
view of section II, two more possibilities to represent a graph
in terms of matrices are presented. But at first, we need some
more definitions.
Definition 1.4 (Path, simple path, connected graph): A
path of length p between two nodes nj1 , njp+1 of a graph
G is a sequence of nodes nj1 , . . . , njp+1 such that for every
two consecutive nodes njk 6= njk+1 , k = 1, . . . , p in this
sequence either bjk ,jk+1 ∈ B or bjk+1 ,jk ∈ B. If in addition,
njk 6= njl , k, l ∈ {1, . . . , jp }, then the path is simple. G
is connected if for every pair of nodes there exists a path
between them.
If a graph G is not connected, it consists of at least two
separate subgraphs. These subgraphs are connected graphs and
are usually called components of G.
Definition 1.5 (Loop, cutset): Let G be an oriented graph.
A loop is a simple path such that nk1 = nkp+1 . A cutset is a
set Bc of branches of G such that the graph Gc that results
when the branches in Bc are deleted from G has one more
component then G, but adding any branch in Bc to Gc would
result in a graph with the same number of components as G.
Apart from the incidence matrix, there are two possibilities
to represent a graph as a matrix which are of interest in this
paper. One is based on the relations between loops and the
branches that form them. The other one is based on cutsets
and the branches that form these cutsets.
Definition 1.6 (Loop matrix): Let G be an oriented graph.
Consider all loops m1 , . . . , mM in G. Choose one branch in
each loop to define the orientation of the loops. The loop
f ∈ RM ×B is given by
matrix M

1 if branch l belongs to loop k and




is oriented in the same way,


m
e kl = −1 if branch l belongs to loop k and



is oriented in the opposite way,



0 if branch l does not belong to loop k.
Definition 1.7 (Cutset matrix): Let G be an oriented graph.
Consider all cutsets s1 , . . . , sS . Choose one branch in each
cutset to define the orientation of the cutsets. The cutset matrix
e ∈ RS×B is then given by
S

1 if branch l belongs to cutset k and




is oriented in the same way,


sekl = −1 if branch l belongs to cutset k and



is oriented in the opposite way,



0 if branch l does not belong to cutset k.
f and S
e defined in Definitions 1.6 and 1.7 in
The matrices M
general do not have full rank. So, it is interesting to identify
those sets of loops and cutsets that yield full rank matrices.
Definition 1.8 (Tree, forest): Consider a connected graph
G = G(N, B). A tree T = T(NT , BT ) of G is a subgraph
with NT = N which is connected but does not contain any
loops. If G is not connected and consists of F components,
then the trees T1 , . . . , TF of the components of G form a
forest T = T(NT , BT ). In this case, NT and BT are given
by
NT = NT1 ∪ · · · ∪ NTF ,
BT = BT1 ∪ · · · ∪ BTF .
The branches e
b1 , . . . , e
bBt of T are referred to as tree
branches. Those branches b
b1 , . . . , b
bBc of G that are not
contained in T are called connecting branches.
Lemma 1.1: Let G be a connected graph and T a tree of
G. Then
1) every connecting branch closes a unique loop that consists of that connecting branch and tree branches only.
These loops are called independent loops.
2) every tree branch defines a unique cutset that consists
of that tree branch and connecting branches only. These
cutsets are called independent cutsets.
Every loop and cutset can be combined by the independent
loops or cutsets that are defined by the tree T.
Proof: Cf. [11].
It can be shown that Lemma 1.1 is also valid for graphs
which are not connected [11].
Definition 1.9 (Reduced loop matrix): Let G be an oriented
graph and T a tree of G. Consider the independent loops that
are defined by T. Let the loops be oriented the same way as
the connecting branches that define them. The coefficients mkl
of the reduced loop matrix M ∈ RB↔ ×B are then defined in
analogy to Definition 1.6.
Definition 1.10 (Reduced cutset matrix): Let G be an oriented graph and T a tree of G. Consider the independent
cutsets that are defined by T. Let the cutsets be oriented
3
the same way as the tree branches that define them. The
coefficients skl of the reduced cutset matrix S ∈ RBt ×B are
then defined in analogy to Definition 1.7.
Lemma 1.2: Let G be a graph and T a tree of G. The
matrices M and S as defined in Definitions 1.6 and 1.7 have
full rank. Moreover, if the branches of G are ordered such that
B = {b
b1 , . . . , b
bBc , e
b1 , . . . , e
bBt } then
M =
S =
[ IB G ] ,
c T
−G IBt ,
where Ik denotes the k × k identity matrix and G ∈ RBc ×Bt .
Proof: Cf. [10], [11].
B. The circuit equations
We will consider circuits with general nonlinear capacitances, resistances, inductances and voltage and current
sources that satisfy the restrictions given in [12]. We will
shortly present the charge and flux oriented modified nodal
analysis as modeling method. For a more detailed introduction
to circuit modeling methods see [10].
Consider a circuit. Its topology is completely described by
its reduced incidence matrix A. Let i be the vector of all
branch currents, v the vector of all branch voltages and e the
vector of node potentials in the circuit. These terms are related
by Kirchhoff’s Current Law (KCL) and Kirchhoff’s Voltage
Law (KVL). The KCL states that the sum of all currents that
enter a node is equal to zero, or for the whole circuit,
Ai = 0.
(1)
The KVL on the other hand states that the sum of the
voltages over branches that form a loop in the circuit is equal
to zero. This translates into a relation between the branch
voltages and the node potentials of the circuit
v = AT e.
(2)
We now split the circuit into its capacitive, resistive and
inductive subgraphs and into those subgraphs that are defined
by voltage and current sources. For these subgraphs, we define
the vectors of branch currents i∗ , branch voltages v∗ and the
incidence matrix A∗ , ∗ ∈ {C, R, L, V, I} for the capacitive,
resistive and inductive part and the parts that are defined by
voltage and current sources.
Combining the branch constitutive relations for resistances,
capacitances and inductances with (1) and (2) and the functions that describe the voltage and current sources
iI = is (AT e,
d
q, iL , iV , t) =: is (∗, t)
dt
(3)
d
q, iL , iV , t) =: vs (∗, t),
dt
(4)
and
vV = vs (AT e,
yields the following system
AC
d
q + AR g(ATR e, t) + AL iL
dt
+ AV iV + AI is (∗, t)
d
ATL e − Φ
dt
ATV e − vs (∗, t)
q − qC (ATC e, t)
= 0,
(5a)
= 0,
(5b)
= 0,
= 0,
(5c)
(5d)
Φ − φL (iL , t)
= 0.
(5e)
Here, q is the vector of charges of the capacitances and Φ is
the vector of magnetic fluxes in the inductances of the circuit.
The last two equations (5d) and (5e) are the charge and flux
conservation laws for capacitances and inductances.
The procedure outlined above is the charge and flux oriented
modified nodal analysis (MNA c/f). It yields a mixed system
of differential and algebraic equations (DAE).
C. Index and topology
The numerical integration of general DAEs
f (ẋ, x, t) = 0,
∂
f singular
∂ ẋ
(6)
may be a difficult task. Due to the coupling of differential and
algebraic equations, even the choice of an initial value x0 can
be a challenge, since it will have to fulfill the given algebraic
constraints. What makes matters worse is the observation that
even though x0 fulfills these constraints, it may happen that
there is nevertheless no solution for (6) with initial value x0 .
Apart from this fact, other numerical problems like instabilities
or reduction of the order of the chosen integration method may
occur.
To classify DAEs and give some measure of the difficulty
of their numerical treatment, several index concepts have been
introduced, for example the differentiation index of Campbell
and Gear [13], the strangeness index of Kunkel and Mehrmann
[14] or the tractability index of Griepentrog and März [3].
Here, we will use the differentiation index (d-index).
Roughly speaking, the d-index of (6) is the minimum
number of times that all or part of (6) must be differentiated
with respect to t in order to determine ẋ as a continuous
function of x and t [13].
If the d-index of (6) is greater than 1, there are additional
algebraic constraints which are not explicitly given in (6) but
can be derived by differentiation and algebraic transformations
of (6) [3], [14]–[16].
Consider a circuit that fulfills the restrictions listed in [12].
The d-index of the DAE (5) that arise from this circuit is linked
to its topology. Thus in this case, we may speak of the d-index
of the circuit. To state the relation between the topology and
the d-index of a circuit, we give the following definitions.
Definition 1.11: Consider the oriented graph G of a circuit.
1) An LI-cutset is a cutset consisting of inductances or both
inductances and current sources.
2) A CV-loop is a loop consisting of both capacitances and
voltage sources.
4
Note, that there are no loops that only contain voltage sources
and no cutsets that only consist of current sources, as these
are excluded by the restrictions in [12].
Theorem 1.3: Consider a circuit with circuit equations as
in (5). Let the controlled sources of the circuit fulfill the
conditions in [12].
1) If the circuit does neither contain CV-loops nor LIcutsets, then the d-index of the DAE (5) is equal to
1.
2) If the circuit contains CV-loops, LI-cutsets or both CVloops and LI-cutsets, then the d-index is equal to 2.
Proof: Cf. [7].
It is possible to compute the additional algebraic constraints
of (5) with help of the topology of the circuit, as we will show
in the next section.
II. I NDEX
REDUCTION BY MINIMAL EXTENSION
A. Constraints arising form CV-loops
Consider a RC network, i.e. a circuit that neither contains
inductances nor current sources. If the MNA c/f is used to
model the circuit, then this leads to the following DAE
AC
d
q + AR g(ATR e, t) + AV iV = 0,
dt
d
ATV e − vs (AT e, q, iV , t) = 0,
dt
q − qC (ATC e, t) = 0.
(7a)
(7b)
(7c)
If the sources fulfill the conditions given in [12] and the circuit
contains CV-loops, then (7) has d-index 2. This, in turn, means
that there are some additional constraints that are not explicitly
given in (7).
1) Find a CV-loop in the given network graph. If no loop is found, then
end.
2) Write the equation resulting from the sum of the derivatives of the
characteristic equations of the voltage sources contained in the CVloop, taking into account the orientation of the loop and the reference
direction of the considered branches. For instance, if the voltage
sources v1 , . . . , vk form a part of the CV-loop and we define

1, if the orientation of the loop coincides with that of vi ,
αi =
−1, else
then the equation we write in this step is
k
X
i=1
αi
„
«
d “ T ”
d
AV e − vs,i (∗, t) = 0 .
i
dt
dt
3) Form a new network graph by deleting the branch of one voltage source
that forms a part of the loop, leaving the nodes unchanged.
4) Return to 1, considering the new network graph.
ALGORITHM I
C OMPUTATION
OF THE HIDDEN CONSTRAINTS ARISING FORM
CV- LOOPS
( C . F. [12])
In [12], the hidden constraints are computed by Algorithm
I. The coefficients αi that are computed by the algorithm are
related to the coefficients of a loop matrix. To show this
connection, the definition of the αi is changed to include
all voltage sources in the circuit and all the loops that are
determined by the algorithm. Thus, let v1 , . . . , vNV be the
voltage sources and let m1 , . . . , mM CV be those CV-loops
Algorithm I detects. Let the CV-loops be oriented in an
arbitrary way. Then, define for each loop mj , j = 1, . . . , M CV
and each voltage source vk , k = 1, . . . , NV
 1, if v belongs to m and
k
j




is
oriented
in
the
same
way as mj ,


αjk = −1, if vk belongs to mj and



is oriented in the opposite way as mj .



0, if vk does not belong to mj .
In addition, the capacitances that are part of the considered
CV-loops are taken into account by defining
 1, if c belongs to m and
k
j




is
oriented
in
the
same
way as mj ,


α
ejk = −1, if ck belongs to mj and



is oriented in the opposite way as mj .



0, if ck does not belong to mj ,
where c1 , . . . , cNC are the capacitances of the circuit. Hence,
with MV := [αjk ] ∈ RM CV ×NV , the hidden constraints the
algorithm computes can be rewritten as
0=
d
MV (vV − vs (∗, t)) ,
dt
(8)
or alternatively as
0 = MV
d
ATV e − vs (∗, t) ,
dt
(9)
if the facts that vV = ATV e and that MV does not depend
on t are taken into account. Note that MV has full row rank
T
and that it is equivalent to the matrix QV −C from [12]. If
(9) together with the derivative of the charge conservation law
(7c) is added to the DAE (7) and new variables are added as
proposed in [8], then the d-index of(7) is reduced from 2 to 1.
The matrix MCV := MC MV ∈ RM CV ×(NC +NV ) with
MC := (e
αjk ) ∈ RM CV ×NC is part of the reduced loop matrix
MCV the subgraph GCV which is defined as follows.
Definition 2.1 (CV-subgraph): A CV-subgraph is a connected subgraph of the network that consists only of both
capacitive branches and branches with voltage sources and
nodes incident with these branches. GCV denotes the union
of all CV-subgraphs.
1) Initialize TCV with the branches of voltage sources in GCV .
2) For all capacitances c1 , . . . , cBG
of GCV do
CV
a) Check, if ck closes a loop.
i) If ck does not close a loop, add it to TCV .
ii) If ck closes a CV-loop, identify the branches that form this
loop and save them along with k.
F IND
ALGORITHM II
CV- LOOPS
THE INDEPENDENT
Algorithm II builds a tree TCV in GCV and determines a set
of independent loops. If the coefficients of the reduced loop
matrix MCV of GCV that is associated to the tree TCV are
5
defined analogously to the coefficients αjk and α
ejk of MCV ,
then
MCV = [MC MV ] .
(10)
Note that MV does not need to have full row rank in this
case. However, MC has full row rank due to the fact that
loops of voltage sources have been excluded in the conditions
in [12]. From Lemma 1.1 it follows that the CV-loops detected
by Algorithm I can be obtained as linear combinations of
the independent loops determined by Algorithm II. Hence the
equations in (8) are linear combinations of the equations
d T
d
MV
AV e − vs (∗, t) = 0.
(11)
dt
dt
If (11) instead of (9) together with the derivative of the charge
conservation law (7c) is added to the DAE (7) and new
variables are introduce as described in [8], then this still lowers
the d-index of (7).
Now, (11) is reformulated such that the hidden constraints
can be incorporated in a way that preserves the special
structure of the DAE (7). Due to KVL, MC vC + MV vV = 0
holds and with vV = ATV e, equation (11) may be rewritten
as
d
d
MC vC + MV vs (∗, t) = 0.
(12)
dt
dt
Since MCV is a reduced loop matrix of GCV and because
of Lemma 1.2, there exists a permutation of the capacitive
branches and the branches of voltage sources such that


bC
v
v
V,ind


vC = v
.
(13)
e C , vV =
vV,contr
vC
bC is the vector of branch voltages across those caHere, v
pacitive branches that close the independent CV-loops that
eC is the vector of branch voltages
Algorithm II detects. v
across capacitive branches that belong to TCV . The vector
vC denotes the vector of branch voltages across capacitive
branches that do not belong to GCV . The vector vV,ind denotes
the voltages across independent voltage sources and vV,contr
the voltages across controlled voltage sources. Since controlled
voltage sources are not allowed in CV-loops (cf. [7]) and due
to Lemma 1.2, the reduced loop matrix MCV with respect to
all capacitive branches and all branches of voltage sources has
the form
MCV = [ IMCV GCe OC MV,ind OV,contr ] ,
(14)
where MCV is the number of independent loops in GCV .
Thus, with (13) and (14) equation (12) can be transformed
into
d
d
d
bC + GCe v
eC + MV,ind vs,ind (t) = 0.
v
(15)
dt
dt
dt
Assuming now that the capacitive charges depend only
on the voltages across the respective capacitive branch, it is
possible to write


 
qbC (b
vC )
b
q



vC )  =: q
q = qC (vC , t) =:  qeC (e
(16)
e.
q C (vC )
q
Remark 2.1: This is a minor restriction since for most
nonlinear capacitances the charges only depend on the voltages
at the incident nodes.
b and q
e are equal to
The derivatives of the capacitive charges q
the capacitive currents biC and eiC and given by
∂
d
biC = d q
b vC ) d vC , (17a)
b =
qbC (b
vC ) vC =: C(b
dt
∂v
dt
dt
d
d
∂
eiC = d q
e
e =
qeC (e
vC ) vC =: C(e
vC ) vC . (17b)
dt
∂v
dt
dt
b vC ) and C(e
e vC ) are assumed to be
Since the Jacobians C(b
positive definite, the respective inverses exist (cf. [12]). Thus,
(17) can be used to express the derivatives of the voltages
bC and v
eC in terms of the currents biC and eiC , respectively.
v
b vC )
To obtain this expression, (12) is first multiplied with C(b
which yields
biC = C(b
b vC ) d vC
dt
d
d
b
eC + MV,ind vs,ind (t) .
= −C(b
vC ) GCe v
dt
dt
d
d
e −1 (e
eC = C
e finally leads to
v
vC )eiC and eiC = dt
q
dt
d
biC = biC (b
e, t)
eC , q
(18)
vC , v
dt
d
d
e −1 (e
b vC ) G e C
e + MV,ind vs,ind (t) .
vC ) q
= −C(b
C
dt
dt
Using
Hence, the currents through those capacitances in GCV that
close the CV-loops, that have been found by using Algorithm
II, are determined by the derivatives of the functions of
the voltage sources in GCV and the currents through the
capacitances in TCV . If the incidence matrix AC is partitioned
according to the partitioning of q, (18) can be inserted into
the DAE (7) directly. The DAE that is obtained in this way
now takes the form
d
eC d q
e + AR g(ATR e, t) + AV iV
AC q + A
dt
dt
b CbiC (A
b T e, A
e T e, d q
e, t) = 0, (19a)
+A
C
C
dt
ATV e − vs (∗, t) = 0, (19b)
b TC e) = 0, (19c)
b − qbC (A
q
e T e) = 0, (19d)
e − qeC (A
q
C
T
q − q C (AC e) = 0. (19e)
bC and v
eC do not occur as unknows
Since the branch voltages v
b T e and A
e T e, respectively
in (7), they have been replaced by A
C
C
to yield (19).
B. Constraints arising from LI-cutsets
A situation similar to the one described in Section II-A
occurs in a RL network, i.e. a circuit that does contain neither
capacitances nor voltage sources. The flux oriented MNA
yields the DAE
AR g(ATR e, t) + AL iL + AI is (∗, t) = 0,
d
ATL e − Φ = 0,
dt
Φ − φL (iL , t) = 0.
(20a)
(20b)
(20c)
6
If the controlled current sources fulfill the conditions given
in [12], then the d-index of (20) is equal to 2, if and only
if the circuit contains LI-cutsets. Again, there exist hidden
constraints that are caused by the LI-cutsets. According to
[12], these constraints can be computed by Algorithm III.
1) Find an LI-cutset. If one is found, then pick out an arbitrary inductance
of this cutset. Note that we can always find such an inductance because
cutsets of current sources only are forbidden. If no cutset is found, then
end.
2) Write a new equation resulting by differentiation of the cutset equation
arising from 1. For instance, if the current sources i1 , . . . , ikI and the
inductances l1 , . . . , lkL form a part of the LI-cutset and we define

1, if the orientation of the cutset coincides with that of ij ,
αj =
−1, otherwise,

1, if the orientation of the cutset coincides with that of lj ,
α
ej =
−1, otherwise,
If (21) together with the derivative of the flux conservation
law (20c) is added to (20) and new variables are introduced to
this extended system as proposed in [8], the d-index of (20)
is reduced from 2 to 1.
1) Consider a graph that is derived from the network graph by removing
all current sources and inductances. The components of this graph
are the nodes of a new graph GLI . Assume that GLI has at least
two different nodes. The branches of GLI are defined by the current
sources and inductances of the circuit.
2) Remove from GLI all self-loops, i.e. branches that leave and enter the
same node.
3) Construct a tree TLI of inductive branches in GLI . Denote the tree
branches by elk1 , . . . ,elkS , kl ∈ {1, . . . , NL }. Each tree branch
LI
defines a cutset which is oriented in the same way as the tree branch.
4) Find the independent loops in GLI . If a connecting branch zk closes
a loop that contains the tree branches bk1 , . . . bkj , then zk belongs
to every cutset that is defined by bk1 , . . . bkj . If the orientation of
the loop was defined by the orientation of zk , then zk will always be
reversed to the orientation of the cutsets.
then the equation obtained in this step reads
kI
X
αj
j=1
kL
X
d
d
is,j (∗, t) +
α
ej iL,j = 0.
dt
dt
j=1
F IND
3) Delete the chosen inductance from the network contracting its incident
nodes.
4) Return to 1, considering the new network graph.
ALGORITHM III
C OMPUTATION
THE HIDDEN CONSTRAINTS ARISING FROM
LI- CUTSETS
( CF. [12])
Again, the definitions of the coefficients αj and α
ej are extended such that all inductances and current sources in the circuit are covered. Let the independent LI-cutsets s1 , . . . , sSLI ,
that Algorithm III has determined, be oriented in an arbitrary
way and let the current sources of the circuit be denoted
by i1 , . . . , iNI and the inductances by l1 , . . . , lNL . Then, the
coefficients αjk for the current sources are defined by

1, if ik belongs to sj and




is oriented in the same way as sj ,


αjk = −1, if ik belongs to sj and



is oriented in the opposite way as sj ,



0, if ik does not belong to sj ,
and SI := [αjk ] ∈ RSLI ×NI . Analogously, the coefficients
α
ejk for the inductances are defined by

1, if lk belongs to sj and




is oriented in the same way as sj ,


α
ejk = −1, if lk belongs to sj and



is oriented in the opposite way as sj ,



0, if lk does not belong to sj ,
and SL := [e
αjk ] ∈ RSLI ×NL . The matrix SLI := [SI SL ] is
part of a reduced cutset matrix of the circuit graph restricted
to independent LI-cutsets. The hidden constraints can be
rewritten as
0=
d
(SI is (∗, t) + SL iL ) .
dt
(21)
ALGORITHM IV
LI- CUTSETS
THE INDEPENDENT
It is possible to define the independent LI-cutsets in a more
favorable way by using Algorithm IV. If this is done, then
there exists a permutation of the inductive branch currents and
the branch currents of current sources such that
 
biL
iI,ind
 
iL =  eiL  , iI =
.
(22)
iI,contr
iL
Here, biL is the vector of currents through those inductive
branches that define the independent LI-cutsets that Algorithm
IV detects. eiL is the vector of currents through inductive
branches that do not belong to TCV but are part of LI-cutsets.
vC denotes the vector of currents through inductive branches
that do not belong to LI-cutsets. iI,ind denotes the vector of
currents through independent current sources and iI,contr the
vector of currents through controlled current sources. Since
controlled current sources are not allowed in LI-cutsets (cf.
[7]) and due to Lemma 1.2, the reduced cutset matrix SLI with
respect to all inductive branches and all branches of current
sources has the form
SLI = [ ISLI GLe OL SI,ind OI,contr ]
(23)
and with (22), the hidden constraints (21) can be written as
d
d
db
iL + GLe eiL + SI,ind is,ind (t) = 0.
dt
dt
dt
(24)
Assuming that the inductive fluxes only depend on the current
through the respective inductance, (20c) can be split into


b
φbL (biL )
Φ


e .
Φ = φL (iL , t) =:  φeL (eiL )  =:  Φ
(25)
φC (iL )
Φ
Remark 2.2: Again, this is only a minor restriction since
for most nonlinear inductances the fluxes only depend on the
respective branch currents.
7
bL and v
eL are given by
The inductive branch voltages v
db
∂ b b d
b biL ) d iL , (26a)
bL = − Φ = − φL (iL ) iL =: −L(
v
dt
∂i
dt
dt
de
∂ e e d
d
e
e
eL = − Φ = − φL (iL ) iL =: −L(iL ) iL (26b)
v
dt
∂i
dt
dt
b biL ) and L(
e eiL ) are again assumed to be
and the Jacobians L(
positive definite. Hence, the relations (26) can be use in much
the same way as the relations (17) to transform (24) into
bL = vbL (biL , eiL , v
eL , t)
v
(27)
d
b biL ) G e L
e −1 (eiL )e
= L(
vL − SI,ind is,ind (t) .
L
dt
If the incidence matrix AL is partitioned according to the
e T e can be used
eL = A
partitioning of iL , then the relation v
L
eL in (27). The equation obtained in this way can
to replace v
now be inserted into (20). The new system has the form
b LbiL + A
e LeiL + AL iL + AI is (∗, t) = 0,
AR g(AT e, t) + A
d
d
d
vC = vC2 + vs (t).
dt 1
dt
dt
d
d
d
d
With iC1 = qC1 = 2vC1 vC1 and iC2 = qC2 = vC2
dt
dt
dt
dt
this is rewritten as
d
qC + 2 cos(t) .
(29)
iC1 = 2vC1
dt 2
= 0,
To insert (29) into (28), vC1 is replaced by e1 . This leads to
the DAE (30).
d
qC2 + 2 cos(t) + e1 + is (iV , t) + iV ,(30a)
0 = 2e1
dt
d
0 = qC2 − iV ,
(30b)
dt
0 = e1 − e2 − 2 sin(t),
(30c)
2
(30d)
0 = qC1 − e1 ,
0 = qC2 − e2 .
(30e)
= 0,
The analytical solution to (28) and (30) is given by (31).
R
b T e − vbL (biL , eiL , A
e T e, t)
A
L
L
de
T
e
AL e − Φ
dt
d
T
AL e − Φ
dt
b − φbL (biL )
Φ
e − φeL (eiL )
Φ
The CV-loop yields the constraint
qC1 (t)
qC2 (t)
e1 (t)
e2 (t)
iV (t)
= 0,
= 0,
= 0,
Φ − φL (iL ) = 0.
III. N UMERICAL EXAMPLE
The simple circuit shown in Figure 1 is taken from [17].
2
It contains a nonlinear capacitance C1 with qC1 = vC
and a
1
current controlled current source with is (iV , t) = −2−sin(t)+
(2 sin(t) + 3)iV . The capacitance C2 is a linear capacitance
given by qC2 = vC2 = e2 and the independent voltage source
is given by vs (t) = 2 sin(t).
=
=
=
=
=
(2 + sin(t))2 ,
2 − sin(t),
2 + sin(t),
2 − sin(t),
− cos(t).
(31a)
(31b)
(31c)
(31d)
(31e)
−2
10
−3
10
−4
10
−5
10
iv
−6
10
2
1
−7
10
−8
10
C2
is(iv)
C1
Fig. 2.
Fig. 1.
source
Circuit with nonlinear capacitance and current controlled current
System (28) describes the corresponding charge oriented
MNA equations. Due to the CV-loop which consists of both
the capacitances and the voltage source, (28) has d-index 2.
d
0 =
qC + e1 + is (iV , t) + iV ,
(28a)
dt 1
d
0 =
qC − iV ,
(28b)
dt 2
0 = e1 − e2 − 2 sin(t),
(28c)
(28d)
0 = qC1 − e21 ,
0 = qC2 − e2 .
(28e)
0
2
4
6
8
10
time [sec]
R1
Relative error for d-index 1 (dashed) and d-index 2 (solid) in e1
Both (28) and (30) were integrated using DASPK3.1 [18]
with absolute and relative tolerances of 10−3 . Figures 2, 3
and 4 show the errors in e1 , e2 and the index 2 variable iV .
Figure 5 shows the development of the step sizes for both
formulations during the numerical integration.
DASPK was able to solve the DAE for all components to the
desired accuracy for both the d-index 2 formulation (28) and
the d-index 1 formulation (30). To do so, however, DASPK
needed 353 steps to integrate (28), but only 91 steps for (30).
IV. S UMMARY
We have adapted existing graph theoretical algorithms to
find those configurations in circuits which give rise to hidden
constraints in the circuit’s DAE. The algorithms have been
8
2
0.25
0
0.2
10
10
step size
−2
10
0.15
0.1
−4
10
0.05
−6
10
0
0
−8
10
0
2
4
6
8
2
4
6
8
10
time [sec]
10
time [sec]
Fig. 5.
Fig. 3.
Step sizes for d-index 1 (dashed) and d-index 2 (solid)
Relative error for d-index 1 (dashed) and d-index 2 (solid) in e2
2
10
0
10
−2
10
−4
10
−6
10
−8
10
0
2
4
6
8
10
time [sec]
Fig. 4.
Relative error for d-index 1 (dashed) and d-index 2 (solid) in iV
devised to produce constraints favorable for the use in index
reduction. The main advantage of these algorithms is that they
eliminate the need for expensive algebraic transformations.
All computation needed for the index reduction method can
be done in fast integer arithmetic. The topological analysis
necessary for the presented index reduction method needs to be
performed only once prior to the actual numerical intergration
of the circuit equations.
ACKNOWLEDGMENT
We would like to thank Caren Tischendorf and Volker
Mehrmann for their help with circuits and the corresponding DAEs. Also, Matthias Bollhöfer for encouragement and
Ekkehard Köhler for his help with graph theory. Last but not
least, we want to thank Achim Basermann and Ingo Naumann
from CCRLE for most fruitful discussions.
R EFERENCES
[1] M. Günther and U. Feldmann, “CAD-based electric-circuit modeling
in industry. I. Mathematical structure and index of network equations,”
Surv. Math. Ind., vol. 8, pp. 97–129, 1999.
[2] C. W. Gear, “Differential-algebraic equation index transformation,”
SIAM J. Sci. Statist. Comput., vol. 9, no. 1, 1988.
[3] E. Griepentrog and R. März, Differential-Algebraic Equations and Their
Numerical Treatment, ser. Teubner-Texte zur Mathematik. Teubner
Verlagsgesellschaft, Leipzig, 1986, no. 88.
[4] P. Kunkel and V. Mehrmann, “Analysis und Numerik linearer
differentiell-algebraischer Gleichungen,” Preprint TU-Chemnitz Fakultät
für Mathematik, Tech. Rep., 1994.
[5] I. Schumilina, “Charakterisierung der algebro-differentialgleichungen
mit traktabilitätsindex 3,” Dissertationsschrift, in German, HumboldtUniversität zu Berlin, Mathematisch-Naturwissenschaftliche Fakultät
II,Institut für Mathematik, D-10099 Berlin, Germany, 2004.
[6] R. März and C. Tischendorf, “Recent results in solving index-2
differential-algebraic equations in circuit simulation,” SIAM J. Sci.
Comput., vol. 18, no. 1, pp. 139–159, 1997.
[7] D. Estévez Schwarz and C. Tischendorf, “Structural analysis for electric
circuits and consequences for MNA,” Int. J. Circ. Theor. Appl., vol. 28,
pp. 139–159, 1997.
[8] P. Kunkel and V. Mehrmann, “Index reduction for differential-algebraic
equations by minimal extension,” Z. Angew. Math. Mech., vol. 84, pp.
579–597, 2004.
[9] S. Bächle, “Index reduction for differential-algebraic equations in circuit
simulation,” TU Berlin, Germany, Tech. Rep. M ATHEON 141, 2004.
[10] C. Desoer and E. Kuh, Basic Circuit Theory. McGraw-Hill, 1969.
[11] B. Korte and J. Vygen, Combinatorial Optimization - Theory and
Algorithms, 2nd ed. Springer-Verlag, 2002.
[12] D. Estévez Schwarz, “A step-by-step approach to compute a consistent
initialization for the MNA,” Int. J. Circ. Theor. Appl., no. 30, pp. 1–16,
2002.
[13] S. L. Campbell and C. W. Gear, “The index of general nonlinear DAEs,”
Numer. Math., vol. 72, no. 2, pp. 173–196, 1995.
[14] P. Kunkel and V. Mehrmann, “Local and global invariants of linear
differential-algebraic equations and their relations,” Electr. Trans. Num.
Anal., vol. 4, pp. 138–157, 1996.
[15] E. Hairer and G. Wanner, Solving Ordinary Differential Equations II,
2nd ed. Springer-Verlag, March 1996.
[16] K. E. Brenan, S. L. Campbell, and L. R. Petzold, The Numerical Solution
of Initial-Value Problems in Ordinary Differential-Algebraic Equations.
New York, N. Y.: Elsevier, North Holland, 1989.
[17] D. E. Schwarz and C. Tischendorf, “Mathematical problems in circuit
simulation,” Math. Comput. Model. Dyn. Syst., vol. 7, no. 2, pp. 215–
223, 2001.
[18] P. Brown, A. Hindmarsh, and L. Petzold, “Using krylov methods in
the solution of large-scale differential- algebraic systems,” SIAM J. Sci.
Comput., vol. 15, no. 6, pp. 1467–1488, 1994.