CAD and Circuit Simulators

' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ Spice-37 CAD and Circuit Simulators _ × õ > ¦ »Á ‫כ‬ É þ Ù Kyungpook National University & Integrated Systems Lab, Kyungpook National University ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design % $ Spice-1 Computer Aided Design (CAD) ❏ Design = key word ❏ A working chip NOT just a working program ❏ Evolutionary not revolutionary ❏ Close coupling with designers ❏ 20 lines of bug-free code per day & Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design CAD Areas for Integrated Circuits $ Spice-2 ❏ Design verification – Simulation: circuit, logic, mixed – Functional verification – Timing verification – Physical verification ❏ Circuit synthesis – High-level synthesis – Combinational logic optimization – Sequential logic optimization – Layout synthesis – Analog circuit synthesis & Integrated Systems Lab, Kyungpook National University ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design % $ Spice-3 ❏ Circuit testing – Fault simulation – Automatic test pattern generation – Sequential test – Buil-in self test (BIST) – Analog test ❏ Design representation – Domain: behavioral, structural, physical – Digital HDL: VHDL, ELLA, Verilog HDL, Hardware C – Analog HDL: VHDL-AMS, AnaVHDL, AHDL, Verilog-A – Design database & Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ Spice-4 Circuit Simulators ❏ Spice: Simulation Program with Integrated Circuit Emphasis – a general-purpose circuit simulator – de facto industrial standard for computer-aided circuit analysis – Spice2g6 (1980), Spice3f5 (1994), PSpice (1984), HSpice ❏ Simulation flow *.cir *.out Spice Circuit file Output file ❏ Output postprocessing using probe & Integrated Systems Lab, Kyungpook National University ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design Analysis Types of Spice % $ Spice-5 ❏ DC analysis – operating point (.op) – dc sweep (.dc) – small-signal transfer function (.tf) – small-signal sensitivity (.sens) ❏ Transient analysis – time domain response (.tran) – Fourier analysis (.four) ❏ AC analysis – small-signal frequency response (.ac) – noise analysis (.noise) & Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design Spice Input File $ Spice-6 ❏ Circuit file format Title statement Analysis requests Output requests Circuit description Power supplies Signal sources Element descriptions Model statements + Continued line * Comment line .end & Integrated Systems Lab, Kyungpook National University ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design % $ Spice-7 A Diode Circuit ❏ Circuit diagram 1 + 2 D1 + vD − + RL vI − vO − 0 ❏ Node number: 0 for the ground node, 1 to 9999 & Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design Example of Circuit File $ Spice-8 ❏ diode.cir A diode circuit .options reltol=0.001, abstol=1pA, vntol=1uV .dc vI 0 1v 0.01v .print dc v(2) (.probe) * step stop start max *.tran 0.01m 4m 0m 0.001m vI 1 0 dc 1v ac 1v 0 + sin (0v 5v 1kHz 0s 0) D1 1 2 D1N4184 RL 2 0 1k .model D1N4184 D (Is=0.1p Rs=16 Cjo=2p Tt=12n Bv=100) .end ❏ PSpice: File->Open, File->Run Probe, Trace->Add & ' Integrated Systems Lab, Kyungpook National University ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design Basic Concepts of Circuit Simulators % $ Spice-9 ❏ Reliable device models ❏ Systematic formulation ❏ Solution by Newton-Raphson method ❏ Sparse matrix techniques ❏ Circuit analysis methods – Sparse Tableau Analysis (STA): ASTAP – Modified Nodal Analysis (MNA): SPICE ❏ Stable integration formulae ❏ Automatic stepsize control & Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ Spice-10 Sparse Tableau Analysis ❏ KCL equations Ai = 0, aij +1 if node i is the positive node of branch j = i = A = incidence matrix branch current vector ❏ KVL equations e − At v = 0 e = branch voltage vector v = node voltage vector ❏ Branch equations & Zb i − Yb e % = S = source vector Integrated Systems Lab, Kyungpook National University ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design ❏ STA equations  A 0   0  Zb 1 −Yb 0  i   $ Spice-11  0     t    = −A   e   0   0 v S ❏ Features – Application to any circuit – Assembly by inspection – Sparse coefficient matrix – Sophisticated programing – Solutions to all node voltages, all branch voltages, and all branch currents → large matrix size & Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / $ Analog Integrated Circuit Design Spice-12 ❏ Example: a linear resistive circuit 1 e3 + R3 R1 G2 e 3 2 3 − −+ ES6 + e4 − R4 IS5 R8 E7 e3 −+ 0 4 ❏ STA equations & ' Integrated Systems Lab, Kyungpook National University ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design 3 3 2 i1 0 7 6 i2 7 6 0 7 6 1 −1 −1 7 76 7 6 6 7 6 i3 7 6 0 7 6 10 1 7 76 7 6 6 7 6 i4 7 6 0 7 6 1 −1 7 76 7 6 6 7 6 i5 7 6 0 7 6 1 −1 7 76 7 6 6 7 6 i6 7 6 0 7 6 1 −1 7 76 7 6 6 7 6 i7 7 6 0 7 6 1 −1 1 7 76 7 6 6 76i 7 6 0 7 6 1 −1 7 76 8 7 6 6 7 6e 7 6 0 7 6 1 1 7 76 17 6 6 7 76 7 6 6 1 1 −1 7 6 e2 7 6 0 7 6 7 76 7 = 6 6 1 0 −1 7 6 e3 7 6 0 7 6 7 76 7 6 6 6 1 −1 1 7 6 e4 7 6 0 7 7 76 7 6 6 7 6 e5 7 6 0 7 6 R1 −1 7 76 7 6 6 7 6 e6 7 6 0 7 6 1 −G2 7 76 7 6 6 7 6 e7 7 6 0 7 6 R −1 3 7 76 7 6 6 7 6 e8 7 6 0 7 6 R4 −1 7 76 7 6 6 7 6 v1 7 6 I 7 6 1 S5 7 76 7 6 6 7 6v 7 6E 7 6 1 7 6 2 7 6 S6 7 6 5 4v 5 4 0 5 4 E7 −1 3 0 v4 R8 −1 2 11 & 1 −1 32 Integrated Systems Lab, Kyungpook National University % $ Spice-13 % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ Spice-14 Modified Nodal Analysis ❏ KCL equations: node equations Yv = Is = current source vector Y = node admittance matrix v = node voltage vector ❏ KVL equations for voltage sources ❏ MNA equations   & Y C B D   v i   = J E   % Integrated Systems Lab, Kyungpook National University ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ Spice-15 ❏ Features – Application to any circuit – Assembly by inspection – Sparse coefficient matrix – Closeness to Y of nodal analysis: most nonzero diagonal entries – Solutions to all node voltages and currents of voltage sources ❏ Example: the linear resistive circuit 1. Write KCL at the nodes ①: i1 + i2 + i3 = 0, ②: −i3 + i4 − i5 − i6 = 0 ③: i6 + i8 = 0, ④: i7 − i8 = 0 2. Substitute branch currents and voltages with node voltages & Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / $ Analog Integrated Circuit Design Spice-16 ①: v1 /R1 + G2 (v1 − v2 ) + (v1 − v2 )/R3 = 0 ②: −(v1 − v2 )/R3 + v2 /R4 − i6 = IS5 ③: i6 + (v3 − v4 )/R8 = 0, ④: i7 − (v3 − v4 )/R8 = 0 3. Append the branch equations of branch voltage sources – Branch 6: v3 − v2 = ES6 – Branch 7: v4 − E7 (v1 − v2 ) = 0 4. MNA equations 1 1 + G2 + 6 R1 R3 6 1 6 − 6 6 R3 6 6 0 6 6 6 6 0 6 6 4 0 −E7 2 & ' 1 R3 1 1 + R3 R4 −G2 − 0 0 0 −1 E7 0 0 0 1 R8 1 − R8 1 0 1 − R8 1 R8 0 1 0 0 −1 0 1 0 0 1 0 0 0 0 3 72 7 7 76 76 76 76 76 76 76 74 7 7 5 v1 v2 v3 v4 i6 i7 3 2 0 6 IS5 7 6 7 6 7 6 0 7 7=6 6 0 7 6 7 4 ES6 5 0 Integrated Systems Lab, Kyungpook National University ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design MN Formulation by Inspection 3 7 7 7 7 7 7 7 5 % $ Spice-17 ❏ Node-by-node (person), element-by-element (computer) basis ❏ KCL equations for a conductance element vj vk i j k y node j : · · · + i · · · = · · · + yvj − yvk · · · = · · · node k : · · · − i · · · = · · · − yvj + yvk · · · = · · · ❏ Element stamps: row (node current), column (node voltage) j & k   y −y −y y   Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Element Analog Integrated Circuit Design Symbol Matrix Equation # ij = I ik = −I $ Spice-18 j Current source " j k I −I I Source vector k j i Voltage source j k 2 j 6 k4 m 1 −1 + E − k l 32 1 76 −1 5 4 j & j k g Admittance k# ij = gvjk ik = −gvjk 7 Source 5 vector g −g −g g k % Integrated Systems Lab, Kyungpook National University ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Element Analog Integrated Circuit Design Symbol j Matrix k j VCVS k i l m l " j k# g −g −g g j k l m v − m l z k m + av − j i CCCS gv − + Equation $ Spice-19 l + v VCCS & ij = i ik = −i vj − vk = E E j " 3 ai m 2 l 6 m 4 −a a 1 −1 p il = gvjk im = −gvjk n 3 1 7 −1 5 2 j k l m n3 j 1 k 6 −1 7 l 6 a7 4 5 m −a p 1 −1 −z il = i im = −i vlm = avjk ij = −ik = i il = −im = ai vj − vk = zi Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ Spice-20 Algorithms for Solving Linear Equations ❏ Equation Ax = b ❏ Methods – Iterative methods: Gauss-Jacobi, Gauss-Seidel, SOR – Direct methods: Gaussian elimination, LU decomposition ❏ Gauss-Jacobi method Ax = (L + D + U)x = b k Dxk+1 = b − (L + U)x & % Integrated Systems Lab, Kyungpook National University ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ Spice-21 ❏ Example for solving a matrix equation  4   1  1 1 2     16 x1         = 3 1   x2   10   x3 2 5 12 x0 = [ 0 0 0 ]t x1 = [ 4 10/3 12/5 ]t x2 = [ 59/30 18/15 4/15 ]t x3 = [ 107/30 233/90 229/150 ]t (1) ❏ Gauss-Seidel method & (L + D)x k+1 = b − Uxk Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / $ Analog Integrated Circuit Design Spice-22 ❏ Gaussian elimination: backward substitution  a  11   a21   ..  .  an1 a12  a  11   0   ..  .  0 ··· a1n  a22 .. . ··· .. . a2n .. . an2 ··· ann        a1n  a12 ··· a22 .. . ··· .. . a2n .. . 0 ··· ann          xn       =       x1   x1 x2 .. .     x2     ..  =   .    xn b1    b2   ..  .   bn b′1      ..  .   ′ bn b′2 ❏ LU decomposition: forward, backward substitution & Integrated Systems Lab, Kyungpook National University ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © /         % Ax = LUx ≡ Ly = b a11 a12 · · · a1n a21 a22 .. .. . . an1 an2 $ Analog Integrated Circuit Design       · · · a2n     ..  =  .. . .     · · · ann l11 0 ··· l21 l22 · · · .. .. . . . . . 0 0 .. . ln1 ln2 · · · lnn  Spice-23 u11 u12 · · · u1n        0 .. . u22 .. . 0 0    · · · u2n   ..  .. . .   · · · unn ❏ Pivoting: interchanging rows and/or columns to bring a nonzero element in diagonal element for solution accuracy ❏ Exploiting sparsity & CPU time : O(n3 ) → O(n1.2 ) Memory : O(n2 ) → O(n) Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / /* * * * * * * * * * * */ Analog Integrated Circuit Design Sparse Matrix Package $ Spice-24 sparse.c Test routine for the sparse matrix package Author: Prof. Yu Sang Dae Kyungpook National University Emphasis is on demonstrating how to use the basic capability of the matrix routines. #include #include #include #include & <stdio.h> <math.h> <sys/types.h> "spconfig.h" Integrated Systems Lab, Kyungpook National University ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design #include "spmatrix.h" #include "spdefs.h" #include "sperror.h" % $ Spice-25 main( argc, argv ) int argc; char *argv[]; { char *Matrix; int i, last, size, complex, error; double RHS[10], Solution[10], iRHS[10], iSolution[10]; RealNumber *pElement; size = 3; complex = 1; Matrix = spCreate( size, complex, &error ); spErrorMessage( Matrix, stdout, NULL ); spClear( Matrix ); & Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design error = spAddComplexElement( Matrix, error = spAddComplexElement( Matrix, error = spAddComplexElement( Matrix, spErrorMessage( Matrix, stdout, NULL 1, 1, 1.0, 1.0 ); 2, 2, 1.0, 2.0 ); 3, 3, 2.0, 2.0 ); ); $ Spice-26 /* spPrint( Matrix, PrintReordered, Data, Header ) */ spPrint( Matrix, 0, 1, 0 ); error = spFactor( Matrix ); /* spPrint( Matrix, 1, 1, 0 ); */ spErrorMessage( Matrix, stdout, NULL ); RHS[1] = 1.0; RHS[2] = 1.0; RHS[3] = 1.0; iRHS[1] = 0.0; iRHS[2] = 0.0; iRHS[3] = 0.0; spSolve( Matrix, RHS, Solution, iRHS, iSolution ); & ' Integrated Systems Lab, Kyungpook National University ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design printf( "Solution\n" ); if ( complex ) for (i = 1; i <= size; i++) printf( "%-16.9g %-16.9gj\n", Solution[i], iSolution[i]); else for (i = 1; i <= size; i++) printf( "%-16.9g\n", Solution[i]); spDestroy( Matrix ); % $ Spice-27 } spAddComplexElement( Matrix, Row, Col, Real, Imag ) char *Matrix; int Row, Col; double Real, Imag; { register RealNumber *pElement; pElement = spGetElement( Matrix, Row, Col ); *pElement += Real; *(pElement + 1) += Imag; return spError( Matrix ); } & Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ Spice-28 Solution of Nonlinear Algebraic Equations ❏ Equation f (x) = 0 ❏ Taylor expansion f (x∗ ) = 0 = f (xk ) + f ′ (xk )(x∗ − xk ) + R(x∗ − xk ) ❏ Newton method: Newton-Raphson method f ′ (xk )∆xk = −f (xk ) xk+1 = xk + ∆xk = xk − f (xk )/f ′ (xk ) ❏ Convergency: if xk is sufficiently close to the solution, the NR method has quadratic convergence. & ǫk+1 = |xk+1 − x∗ | ≤ βǫ2k % Integrated Systems Lab, Kyungpook National University ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ Spice-29 ❏ Convergence criteria: relative error tolerence ER , absolute error tolerence EA |∆xk | = |xk+1 − xk | < ǫ = ER |xk+1 | + EA ❏ Global methods: convergence from almost any starting point – Controlled NR method xk+1 = xk + αk ∆xk , 0<α≤1 – Charge-up method: capacitor k nonlinear current source, inductor + nonlinear voltage source xn+1 − xn dxn+1 = dt ∆t – Optimization-based method & Minimize f = 1 F·F 2 Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design – Damping: avoiding overflow due to exponential dependency ∆x = sign(∆x) $ Spice-30 ln(1 + a|∆x|) a – Source stepping algorithm – Gmin stepping algorithm ❏ Multidimensional NR method: Jacobian matrix J J∆x = −F, Jij ≡ ∂Fi ∂xj ❏ Convergency of MNR method – J is nonsingular – J is Lipschitz continuous & ' k J(x∗ )−1 [J(x) − J(x∗ )] k ≤ βk x − x∗ k Integrated Systems Lab, Kyungpook National University ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design Stamps of Nonlinear Elements % $ Spice-31 ❏ ∆x : x formulation J∆x = −F : Jk xk+1 = Jk xk − Fk ❏ Companion models: linearized equivalent circuits for nonlinear and charge-storage elements f1 (i, v) = i − iD (v) = 0, Is & f2 (i, v) = i + R i v − Is = 0 R + v D − Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / $ Analog Integrated Circuit Design Spice-32 Companion Model of Diodes ❏ A linearized circuit for the nonlinear diode equation  1  −gk 1 1/R   ik+1 vk+1   = 1 −gk 1 1/R   ik vk   − f1k f2k   ik+1 = gk vk+1 + ik − gk vk − f1k ≡ gk vk+1 + Ik = −vk+1 /R + Is iD ik+1 Is + ik+1 ik vk vk+1 Ik & gk vk+1 Ik − RIs v D % Integrated Systems Lab, Kyungpook National University ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / $ Analog Integrated Circuit Design Spice-33 Stamps of Nonlinear Current Sources ❏ i is not part of x : fj = · · · + i(x) · · · , fk = · · · − i(x) · · · j k x1 ∂i/∂x1 −∂i/∂x1 x2 ∂i/∂x2 −∂i/∂x2 ··· ··· ··· xn ∂i/∂xn −∂i/∂xn ··· ··· ··· RHS −i(x) +i(x) ❏ i is part of x : fj = · · · + il (x), fk = · · · − il (x), fl (x) = i(x) − il = 0 j k l x1 x2 ··· xn ··· ∂i/∂x1 ∂i/∂x2 ··· ∂i/∂xn ··· il +1 −1 −1 ··· RHS ··· −fl (x) ❏ AC analysis & YV = (G + sC)V = I Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / /* * * * * * * * */ Analog Integrated Circuit Design $ Spice-34 main.c iCADs Integrated Circuit Analysis and Design by Simulation Written by Prof. Yu Sang Dae Copyright (C) 1996 Kyungpook National University. 1996. 04. 17. - 1996. 08. 18 initial version. main( argc, argv ) int argc; char *argv[]; { Circuit *Ckt; if ( argc < 2 ) { printf( "Usage: icads file\n" ); exit( 1 ); } & Integrated Systems Lab, Kyungpook National University ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design % $ Spice-35 Ckt = Malloc( Circuit ); InitSystem( Ckt ); ReadFile( argv[1], Ckt ); ParseCommand( Ckt ); MakeModelTable( Ckt ); MakeSubcktTable( Ckt ); MakeFlatCircuit( Ckt ); ParseDevice( Ckt ); SetupMatrix( Ckt ); Analysis( Ckt ); FreeCircuit( Ckt ); Free( Ckt ); return( 0 ); } & Integrated Systems Lab, Kyungpook National University % ' ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design $ Spice-36 Homework (1) Write MNA equations for the linear resistive circuit using element stamps. (2) Solve the matrix equation (1) using the given sparse matrix package. (3) Derive a damping equation for the diode current i = Is (ev/VT − 1). ∆v = VT ln(1 + ∆v/VT ) (∆v > 0) (4) Find the element stamp of nMOS transistors. References [1] F. H. Branin et al., “ECAP II – A new electronic circuit analysis program”, IEEE J. Solid-State Circuits, vol. SC-6, no. 4, pp. 146–166, 1971. [2] L. W. Nagel and R. A. Rohrer, “Computer analysis of nonlinear circuits excluding radiation (CANCER)”, IEEE J. Solid-State Circuits, vol. SC-6, no. 4, pp. 166–182, 1971. & ' Integrated Systems Lab, Kyungpook National University ♣ IsLab | & 9 r h Û ¼% 7 ½ ¨z ´ Ä » @ © / Analog Integrated Circuit Design % $ Spice-37 [3] G. D. Hachtel et al., “The sparse tableau approach to network analysis and design”, IEEE Trans. on Circuit Theory, vol. CT-18, pp. 101–108, 1971. [4] C. W. Ho et al., “The modified nodal approach to network analysis”, IEEE Trans. on Circuits and Systems, vol. CAS-22, No. 6, pp. 504–509, 1975. [5] D. A. Zein, “Solution of a set of nonlinear algebraic equations for general-purpose CAD programs”, IEEE Circuits and Devices Magazine, vol. 1, pp. 7–20, 1985. [6] E. Ngoya, J. Rousset, and J. J. Obregon, “Newton-Raphson iteration speed-up algorithm for the solution of nonlinear circuit equations in general-purpose CAD programs”, IEEE Tran. on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, pp. 638–644, 1997. [7] J. Vlach and K. Singhal, Computer Methods for Circuit Analysis and Design, Van Nostrand Reinhold, 1983. [8] W. J. McCalla, Fundamentals of Computer-Aided Circuit Simulation, Kluwer Academic Publishers, 1988. & Integrated Systems Lab, Kyungpook National University %

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