EE4800 Spring 2010
Computer Aided Design of VLSI System
Lecture 9 Modified Nodal Analysis
Zhuo Feng
7.1
7.
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
■ SPICE overview
► N equations in terms of N unknown Node voltages
► More generally using modified nodal analysis
v2 i  G(v) v1


v
R

C

v3
7.2
7.
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
v4

Time Domain Equations at node 1:
d ( v1  v 3 ) ( v1  v 4 )
C

 G ( v 2  v1 )  0
dt
R

If we do this for all N nodes:
  
F(x(t), x(t),u(t))  0


x ( 0)  X

x (t )  N dimensional vector of unknown

u (t ) 
node voltages
vector of independent sources
F  nonlinear operator
7.3
7.
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
■ Closed form solution is not possible for
arbitrary
bit
order
d off differential
diff
ti l equations
ti
■ We must approximate the solution of:
  
F(x(t), x(t),u(t))  0


x (0)  X
■ This is facilitated in SPICE via numerical solutions
7.4
7.
4
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
■ Basic circuit analyses
► (Nonlinear) DC analysis
▼ Finds the DC operating point of the circuit
▼ Solves a set of nonlinear algebraic
g
eqns
q
► AC analysis
▼ Performs frequency
frequency-domain
domain small
small-signal
signal analysis
▼ Require a preceding DC analysis
▼ Solves a set of complex linear eqns
► (Nonlinear) transient analysis
▼ Computes the time-domain circuit transient response
▼ Solves a set of nonlinear different eqns
▼ Converts to a set nonlinear algebraic of eqns using
numerical integration
7.5
7.
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
■ SPICE offers practical techniques to solve circuit
problems in time & freq.
freq domains
► Interface to device models
▼ Transistors,
Transistors diodes,
diodes nonlinear caps etc
► Sparse linear solver
► Nonlinear solver – Newton-Raphson method
► Numerical
N merical integration
► Convergence & time-step control
7.6
7.
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
■ Circuit equations are usually formulated
using
i
► Nodal analysis
y
▼ N equations in N nodal voltages
► Modified analysis
▼ Circuit unknowns are nodal voltages & some branch
currents
▼ Branch current variables are added to handle
– Voltages sources
– Inductors
– Current controlled voltage source etc
■ Formulations can be done in both time
and
d frequency
f
7.7
7.
7
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
How do we set up a matrix problem given a list of
linear(ized) circuit elements?
Similar to reading a netlist for a linear circuit:
*
Element Name
From
To
Value
1
R1
0
1
R2
1
0
2
1mA
10
5
R3
2
0
100
I1
7.8
7.
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
1
I1
1mA
R2 5
R1
10
2
R3
100
0
The nodal analysis matrix equations are
easily constructed via KCL at each node:
 
Yv  J
7.9
7.
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
■ Naïve approach
► a)) Write down the KCL
C eqn ffor each node
► b) Combine all of them to a get N eqns in N node voltages
■ Intuitive for hand analysis
■ Computer
p
programs
p g
use a more convenient
“element” centric approach
► Element stamps
7.10
7.
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Instead of converting
g the netlist into a g
graph
p and
writing KCL eqns, stamp in elements one at a time:
Stamps: add to existing matrix entries
Y
 1
 R
 1

 R
1
 
R
1 

R 
From
col.
i
7.11
7.
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To
col.
From
row
i
To
row
j
j
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
i
R
j

 RHS J of equations are stamped in a similar way:
 I 
 I 
 
7.12
7.
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i
i
I
j
j
From
row
To
row
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis

Stamping our simple example one
element
l
t att a time:
ti
I1
0
R1
1
R2
1
R3
2
G1  G2
 G
2

7.13
7.
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1
1 mA
0
2
10 
5
0
100 
 G2  V1   I1 
    

G2  G3  V2   0 
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis

We know that nonlinear elements are first
converted to linear components, then stamped
I EQQ
7.14
7.
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
GEQQ
For 3 & 4 terminal elements we know that the
linearized models have linear controlled sources
D

G
G
v gs
S
D


g m v gs
rds
vds

S
We can stamp in MOSFETs in terms of a complete
stamp or in terms of simpler element stamps
stamp,
7.15
7.
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Voltage controlled current source

vk
p
k
i  g m vk
I 0

q

Voltmeter
 gm  gm
 g

 m gm
col k col 
row p
row q
Large value that does not fall on diagonal of Y!
7.16
7.
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis

All other types of controlled sources include
voltage sources

Voltage sources are inherently incompatible
with nodal analysis

Grounded voltages sources are easily accommodated
1
2v
0
7.17
7.
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1   v1 2

 v   

  2  

     
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis

But a voltage
g source in between nodes is
more difficult

k

7.18
7.
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Node voltages
k
and

are not independent
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis

We no longer
g have N independent
p
node voltage
g
variables

So we can p
potentially
y eliminate one equation
q
and one variable (section 2.3 of reference [1])

But
ut the more popular solution is modified nodal
analysis (MNA)
V
k

i
Create one extra variable and one extra equation
7.19
7.
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis

Extra variable: voltage source current

Allows us to write KCL at nodes

Extra equation
k
and

vk  v  V

7.20
7.
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Advantage: now have an easy way of printing
current results - - ammeter
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Voltage source stamp:
1    







row 
1
1


   
row N  1
1 1 0  i  V
row
k
col col col
k
 N 1
7.21
7.
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis

Current-controlled current source (e.g.
(e g BJT) has to
stamp in an ammeter and a controlled current source
i1
7.22
7.
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i2   i1
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
In general
general, we would not blindly build the matrix
from an input netlist and then attempt to solve it
Various illegal ckts are possible:
Cutsets of current sources
7.23
7.
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
Loops of voltage sources
Dangling nodes
7.24
7.
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
■ Once we efficiently
 formulate MNA equations, an efficient
solution to

Yv  J
is even more important
■ For large ckts the matrix is really sparse
► Number of entries in Y is a function of number of elements
connected to the corresponding node
■ Inverting a sparse matrix is never a good idea since the
inverse is not sparse!
■ Instead direct solution methods employ Gaussian
Elimination or LU factorization
7.25
7.
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis
■ We need to solve a linear matrix problem for the
simple DC circuit
■ Linear system solutions are also basic routines for
many other analyses
► Transient analysis,
y , nonlinear iterations etc
■ Sounds quite easy but can become nontrivial for
large analysis problems
► O(n3) – general dense matrices
► O(n1.1~ n1.5) -- sparse circuit problems
1 5) – 2D mesh
► O(n
O( 1.5
h O(n
O( 2) – 3D mesh
h
7.26
7.
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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis