a
Three Phase Active Energy
Metering IC with Serial Port
AD7754*
Preliminary Technical Data
FEATURES
High Accuracy, supports IEC 687/1036
Compatible with 3-phase/3-wire and 3-phase/4-wire
configuration
Less than 0.1% error over a dynamic
range of 500 to 1
An On-Chip user Programmable threshold for line
voltage SAG detection and PSU supervisory.
The AD7754 supplies Sampled Waveform Data
and Active Energy .
Digital Power, Phase & Input Offset Calibration.
An On-Chip temperature sensor (±3°C typical after calibration)
A SPI compatible Serial Interface.
A pulse output with programmable frequency
An Interrupt Request line (IRQ) and Status register
provide early warning of register overflow
Proprietary ADCs and DSP provide high accuracy over
large variations in environmental conditions and time.
Reference 2.5V±8% (30 ppm/°C typical)
with external overdrive capability
Single 5V Supply, Low power (15mW typical)
all the signal processing required to perform active power
and energy measurement.
The AD7754 contains an Active Energy register capable
of holding at least 5 seconds of accumulated power at full
load. Data is read from the AD7754 via the serial interface. The AD7754 also provides a pulse output (CF) with
a frequency which is proportional to the active power.
Besides real power information the AD7754 also provides
system calibration features for each phase, i.e., channel
offset correction, phase calibration and power calibration.
The AD7754 has a waveform sample register which enables access to ADC outputs. The part also incorporates a
detection circuit for short duration low voltage variations
or sags. The voltage threshold level and the duration (no.
of half line cycles) of the variation are user programmable.
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GENERAL DESCRIPTION
The AD7754 is a high accuracy three-phase electrical
energy measurement IC with a serial interface and a pulse
output. The AD7754 incorporates second order sigmadelta ADCs, reference circuitry, temperature sensor, and
A zero crossing detection is synchronized to the zero
crossing point of the line voltage in any of the threephase. The signal is used internally to the chip in the
calibration mode to produce accurate and repeatable calibration result. This permits faster and more accurate
calibration of the active power calculation. This signal is
also useful for synchronization of relay switching, thus
improving the relay life by reducing the risk of arcing.
The interrupt request output is an open drain, active low
logic output. The IRQ output will become active low
when the accumulated real power register is half full and
also when it over flows. A status register will indicate the
nature of the interrupt.
The AD7754 is available in 24 lead SOIC packages.
FUNCTIONAL BLOCK DIAGRAM
RESET
PGA
IAP
IAN
VAP
APGAIN[11:0]
HPF
LPF
AD7754
Σ
ADC
ADC
AVDD
APOS[11:0]
POWER
SUPPLY
MONITOR
Φ
CFNUM[11:0]
APHCAL[7:0]
PGA
IBP
IBN
VBP
BPGAIN[11:0]
HPF
LPF
BPOS[11:0]
ADC
Σ
Σ
ADC
Φ
DFC
CF
CFDEN[11:0]
BPHCAL[7:0]
PGA
ICP
ICN
VCP
VN
CPGAIN[11:0]
LPF
Σ
ADC
ADC
AGND
DGND
DVDD
Φ
CPHCAL[7:0]
2.5V 4kΩ
REF
* Patents pending.
CPOS[11:0]
HPF
TEMP
SENSOR
REF IN/OUT
ADC
AD7754 REGISTERS &
SERIAL INTERFACE
CLKIN
CLKOUT
DIN DOUT SCLK CS IRQ
REV. PrA 8/2000
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
(AVDD = DVDD = 5V±5%, AGND = DGND = 0V, On-Chip Reference,
CLKIN=10MHz, TMIN to TMAX = -40ºC to +85ºC)
AD7754–SPECIFICATIONS
Parameters
ACCURACY
Measurement Error (per phase)
Phase Error Between Channels
(PF=0.8 capacitive)
(PF=0.5 inductive)
ac Power Supply Rejection1
Output Frequency Variation
dc Power Supply Rejection1
Output Frequency Variation
ANALOG INPUTS
Maximum Signal Levels
Input Impedance (dc)
Bandwidth
ADC Offset Error 1
Gain Error 1
Gain Error Match 1
REFERENCE INPUT
REFIN/OUT Input Voltage Range
Input Impedance
Input Capacitance
TEMPERATURE SENSOR
ON-CHIP REFERENCE
Reference Error
Temperature Coefficient
CLKIN
Input Clock Frequency
A Version
B Version
Test Conditions/Comments
0.1% typ
0.2% max
±0.05º max
±0.05º max
±0.05º max
±0.05º max
Over a dynamic range of 500 to 1
Line Frequency = 45Hz to 65Hz
Phase Lead 37º
Phase Lag 60º
0.01% typ
0.01% typ
V1P = V2P = V3P = ±100mV rms
0.01% typ
0.01% typ
V1P = V2P = V3P = ±100mV
0.5 V max
400kΩmin
3.5kHz typ
10mV max
±4% typ
±3% typ
0.5 V max
400kΩmin
3.5kHz typ
10mV max
±4% typ
±3% typ
Wide selection of lower ranges
CLKIN = 10MHz
Uncalibrated error, see Terminology for detail
External 2.5V reference
External 2.5V reference
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2.7V max
2.3V min
4kΩ min
10pF max
±2ºC
2.7V max
2.3V min
4k Ω min
10pF max
±2ºC
2.5V +8%
2.5% -8%
Calibrated dc offset
Note all specifications for CLKIN 10MHZ
±200mV max ±200mV max
30ppm/°C typ 50ppm/°C max
15MHz max
5MHz min
15MHz max
5MHz min
2.4V min
0.8V max
±3A max
10pF max
2.4V min
0.8V max
±3A max
10pF max
LOGIC OUTPUTS
CF, 143, DOUT
Output High Voltage, VOH
4V min
4V min
Output Low Voltage, VOL
1V max
1V max
DVDD=5V ± 5%
4.75V min
5.25V max
4.75V min
5.25V max
3mA max
2mA max
4.75V min
5.25V max
4.75V min
5.25V max
3mA max
2mA max
For spcified performance
5V - 5%
5V +5%
5V - 5%
5V +5%
Typcially 1.5mA
Typically 1.5mA
LOGIC INPUTS
4-5-6, DIN, SCLK and CS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
POWER SUPPLY
A V DD
D V DD
A I DD
D I DD
DV DD =5V ± 5%
DV DD =5V ± 5%
Typical 10nA, Vin=0V to DV DD
NOTES:
1. See Terminology section for explanation of specifications.
2. See plots in Typical Performance Graph.
3. Specification subject to chang without notice.
MODEL
ORDERING GUIDE
AD7754AR
AD7754BR
EVAL-AD7754EB
PACKAGE OPTION *
SO-24
SO-24
AD7754 Evaluation Board
* SO = 0.3’ Small Outline IC
–2–
REV. PrA 8/2000
AD7754
AD7754 TIMING CHARACTERISTICS1,2
Parameter
A,B Versions
(AVDD = DVDD = 5V ± 10%, AGND = DGND = 0V, On-Chip Reference,
CLKIN = 10MHz XTAL, TMIN to TMAX = -40°C to +85°C)
Units
Test Conditions/Comments
20
100
100
10
5
4
100
100
ns
ns
ns
ns
ns
µs
ns
ns
CS falling edge to first SCLK falling edge
SCLK logic high pulse width
SCLK logic low pulse width
Valid Data Set up time before falling edge of SCLK
Data Hold time after SCLK falling edge
Minimum time between the end of data byte transfers.
Minimum time between byte transfers during a serial write.
CS Hold time after SCLK falling edge.
100
100
30
ns (min)
ns (min)
ns (min)
t 12 3
20
ns (min)
t 13 4
100
10
100
10
4
ns
ns
ns
ns
µs
Write timing
t1
t2
t3
t4
t5
t6
t7
t8
Read timing
t9
t 10
t 11 3
t 14 4
t 15
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
Minimum time between read command and data read.
Minimum time between data byte transfers during a multibyte read.
Data access time after first SCLK rising edge following a write to the
Communications Register
Data access time after subsequent SCLK rising edges following a write to
the Communications Register
Bus relinquish time after falling edge of SCLK.
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(max)
(min)
(max)
(min)
(min)
Bus relinquish time after rising edge of +5.
Minimum time between end of a write transfer and the start of a read
transfer (i.e., write to communications register)
NOTES
Sample tested during initial release and after any redesign or process change that may affect this parameter.
tf = 5ns (10% to 90%) and timed from a voltage level of 1.6V.
2
See timing diagram below and Serial Interface section of this data sheet.
3
Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8V or
4
Derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit in
extrapolated back to remove the effects of charging or discharging the 50pF capacitor. This means that the
is the true bus relinquish time of the part and is independant of the bus loading.
1
All input signals are specified with tr =
2.4V.
Figure 1. The measured number is then
time quoted in the timing characteristics
Serial Write Timing
t8
CS
t1
t6
t2 t3
t7
t7
SCLK
t4
DIN
1
0
t5
A5 A4 A3 A2 A1 A0
DB0
DB7
DB7
Least Significant Byte
Most Significant Byte
Command Byte
DB0
Serial Read Timing
CS
t1
t9
t14
t10
SCLK
DIN
0
0
A5 A4 A3 A2 A1 A0
DOUT
DB7
REV. PrA 8/2000
DB0
Most Significant Byte
Command Byte
–3–
t13
t12
t11
DB7
DB0
Least Significant Byte
AD7754
ABSOLUTE MAXIMUM RATINGS*
24-Lead SOIC, Power Dissipation . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C
(T A = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
DV DD to DGND . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
DV DD to AV DD . . . . . . . . . . . . . . . . . . . . . –0.3V to +0.3V
Analog Input Voltage to AGND
I AP ,I AN ,I BP ,I BN ,I CP ,I CN ,V AP ,V BP ,V CP ,V N . –6V to +6V
Reference Input Voltage to AGND –0.3V to AVDD+0.3V
Digital Input Voltage to DGND . –0.3V to DV DD+0.3V
Digital Output Voltage to DGND –0.3V to DV DD+0.3V
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7754 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Terminology
MEASUREMENT ERROR
ESD SENSITIVE DEVICE
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The error associated with the energy measurement made
by the AD7754 is defined by the following formula:
Percentage Error =
WARNING!
For the DC PSR measurement a reading at nominal supplies (5V) is taken. A second reading is obtained with the
same input signal levels when the power supplies are varied ±5%. Any error introduced is again expressed as a
percentage of reading.
FG Energy registered by AD7754 - True Energy × 100%IJ
H
K
True Energy
ADC OFFSET ERROR
PHASE ERROR BETWEEN CHANNELS
The HPFs (High Pass Filters) in Channel 1 (inputs IA, IB
and IC) have phase lead response. To offset this phase
response and equalize the phase response between channels, phase correction networks are placed in each input’s
signal path. The phase correction networks ensures a
phase match between the inputs for Channel 1 (inputs IA,
IB and IC) and Channel 2 (inputs VA, VB and VC) to within
±0.1° over a range of 45Hz to 65Hz and ±0.2° over a
range 40Hz to 1kHz. This phase mismatch between the
voltage and the current channels can be further reduced
with the phase calibration registers in each phase.
POWER SUPPLY REJECTION
This quantifies the AD7754 measurement error as a percentage of reading when the power supplies are varied.
For the AC PSR measurement a reading at nominal supplies (5V) is taken. A second reading is obtained with the
same input signal levels when an ac (175mV rms/100Hz)
signal is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of
reading—see Measurement Error definition above.
This refers to the DC offset associated with the analog
inputs to the ADCs. It means that with the analog inputs
connected to AGND the ADCs still see a dc analog input
signal. The magnitude of the offset depends on the gain
and input range selection - see characteristic curves. However, when HPF is switched on the offset is removed from
Channel 1 (inputs IA, IB and IC) and the power calculation
is not affected by this offset. The offsets may be removed
by performing an offset calibration - see Analog Inputs.
GAIN ERROR
The gain error in the AD7754 ADCs, is defined as the
difference between the measured ADC output code (minus
the offset) and the ideal output code. The difference is
expressed as a percentage of the ideal code.
GAIN ERROR MATCH
The Gain Error Match is defined as the gain error (minus
the offset) obtained when switching between a gain of 1
(for each of the input ranges) and a gain of 2, 4. It is expressed as a percentage of the output ADC code obtained
under a gain of 1. This gives the gain error observed when
the gain selection is changed from 1 to 2, 4.
–4–
REV. PrA 8/2000
AD7754
PIN FUNCTION DESCRIPTION
Pin No.
MNEMONIC
DESCRIPTION
1
CF
Calibration Frequency logic output. The CF logic output gives Active Power information. This output is intended to be used for operational and calibration purposes. The
full-scale output frequency can be scaled by writing to the CFNUM and CFDEN registers—see Energy To Frequency Conversion.
2
DGND
This provides the ground reference for the digital circuitry in the AD7754, i.e. multiplier, filters and digital-to-frequency converter. Because the digital return currents in
the AD7754 are small, it is acceptable to connect this pin to the analog ground plane of
the whole system - see Applications Information. However high bus capacitance on the
DOUT pin may result in noisy digital current which could affect performance.
3
D V DD
Digital power supply. This pin provides the supply voltage for the digital circuitry in
the AD7754. The supply voltage should be maintained at 5V ± 5% for specified operation. This pin should be decoupled to AGND with a 10µF capacitor in parallel with a
ceramic 100nF capacitor.
4
A V DD
Analog power supply. This pin provides the supply voltage for the analog circuitry in
the AD7754. The supply should be maintained at 5V ± 5% for specified operation.
Every effort should be made to minimize power supply ripple and noise at this pin by
the use of proper decoupling. The typical performance graphs in this data sheet show
the power supply rejection performance. This pin should be decoupled to AGND with a
10µF capacitor in parallel with a ceramic 100nF capacitor.
5,6;
7,8;
9,10
IAP, I AN;
I BP , I BN;
I CP , I CN
Analog inputs for current channel. This channel is intended for use with the current
transducer. These inputs are fully differential voltage inputs with maximum differential
input signal levels of ±0.5V - See Analog Inputs. Channel 1 also has PGA with gain
selections of 1, 2, 4. The maximum signal level at these pins with respect to AGND is
±0.5V . Both inputs have internal ESD protection circuitry and in addition an
overvoltage of ±6V can be sustained on these inputs without risk of permanent damage.
11
AGND
This pin provides the ground reference for the analog circuitry in the AD7754, i.e.
ADCs and reference. This pin should be tied to the analog ground plane or the quietest
ground reference in the system. This quiet ground reference should be used for all analog circuitry, e.g. anti aliasing filters, current and voltage transducers etc. In order to
keep ground noise around the AD7754 to a minimum, the quiet ground plane should
only connected to the digital ground plane at one point. It is acceptable to place the
entire device on the analog ground plane - see Applications Information.
12
REF IN/OUT
This pin provides access to the on-chip voltage reference. The on-chip reference has a
nominal value of 2.5V ± 8% and a typical temperature coefficient of 30ppm/°C. An
external reference source may also be connected at this pin. In either cases this pin
should be decoupled to AGND with a 1µF ceramic capacitor.
V N ,V CP ,
V BP ,V AP
Analog inputs for voltage channel. This channel is intended for use with the voltage
transducer. VAP, VBP, and VCP are single-ended voltage inputs with maximum signal
level of ±0.5V with respect to VN for specified operation. These inputs also have PGA
with gain selections of 1, 2, 4. All inputs have internal ESD protection circuitry and in
addition an overvoltage of ±6V can be sustained on these inputs without risk of permanent damage.
13-16
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17
RESET
Reset pin for the AD7754. A logic low on this pin will hold the ADCs and digital circuitry (including the Serial Interface) in a reset condition.
18
IRQ
Interrupt Request Output. This is an active low open drain logic output. Maskable
interrupts include: Active Energy Register roll-over, Active Energy Register at half
level, and waveform sampling up to 28kSPS. See AD7754 Interrupts.
19
CLKIN
Master clock for ADCs and digital signal processing. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected
across CLKIN and CLKOUT to provide a clock source for the AD7754. The clock
frequency for specified operation is 10MHz. Ceramic load capacitors of between 22pF
and 33pF should be used with the gate oscillator circuit. Refer to crystal manufacturers
data sheet for load capacitance requirements.
REV. PrA 8/2000
–5–
AD7754
Pin No.
MNEMONIC
DESCRIPTION
20
CLKOUT
A crystal can be connected across this pin and CLKIN as described above to provide a
clock source for the AD7754. The CLKOUT pin can drive one CMOS load when
either an external clock is supplied at CLKIN or a crystal is being used.
21
DIN
Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of
SCLK—see AD7754 Serial Interface.
22
DOUT
Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of
SCLK. This logic output is normally in a high impedance state unless it is driving data
onto the serial data bus—see AD7754 Serial Interface.
23
SCLK
Serial Clock
synchronized
trigger Input
opto-isolator
24
CS
Chip Select. Part of the four wire Serial Interface. This active low logic input allows
the AD7754 to share the serial bus with several other devices. See AD7754 Serial Interface.
Input for the synchronous serial interface. All Serial data transfers are
to this clock—see AD7754 Serial Interface. The SCLK has a schmittfor used with a clock source which has a slow edge transition time, e.g.,
outputs etc.
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PIN CONFIGURATION
SOIC Packages
CF 1
24 CS
DGND 2
23 SCLK
DVDD 3
22 SDIN
AVDD 4
21 SDOUT
IAP 5
AD7754
20 CLKOUT
IAN 6
19 CLKIN
TOP VIEW
IBP 7 (Not to Scale) 18 IRQ
IBN 8
17 RESET
ICP 9
16 VAP
ICN 10
15 VBP
AGND 11
14 VCP
VREF 12
13 VN
NC = NO CONNECT
–6–
REV. PrA 8/2000
AD7754
ANALOG INPUTS
LINE VOLTAGE SAG DETECTION
The AD7754 has totally six analog inputs, dividable in
two channels: Channel 1 and Channel 2. Channel 1 consists of three pairs of fully-differential voltage inputs,
namely (IAP, IAN), (IBP, IBN), and (ICP, ICN). The fully
differential voltage input pairs have maximum differential
voltage of ±0.5V. Channel 2 has three single-ended voltage inputs VAP, VBP, and VCP. These single-ended voltage
inputs have maximum input voltage of ±0.5V with respect
to VN. Both Channel 1 and Channel 2 have PGA (Programmable Gain Amplifier) with possible gain selections
of 1, 2, 4. The gain selections are made by writing to the
Gain register—see Figure 1. Bits 0 to 1 select the gain for
the PGA in the fully-differential voltage channel (Channel
1). The gain selection for the PGA in the single-ended
voltage input channel (Channel 2) is made via bits 2 to 3.
Figure 1 shows how a gain selection for Channel 1 is
made using the Gain register.
The AD7754 can also be programmed to detect when the
absolute value of the line voltage in any combination of
the inputs in Channel 2 drops below a certain peak value,
for a number of half cycles. The input(s) used in SAG
detection are controlled by setting bit 19 to 21 in the
Mode register - See AD7754 Mode Register. The inputs
selected for SAG detection are also monitored for zero
crossing detection - See Zero Crossing Detection section on
this datasheet for details. This condition is illustrated in
Figure 3 below.
GAIN[7:0]
VAP, VBP, or VCP *
Full Scale
SAGLVL[7:0]
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SAG Interrupt Flag
(Bit 1 of STATUS register)
Gain (k)
selection
IAP, IBP, ICP
SAGCYC[7:0] = 06h
6 half cycles
SAG reset low
when channel 2
exceeds SAGLVL[7:0]
* The source of the SAG/Zero crossing detection is selected by bit 19 to 21 of Mode Register
+
-
Vin
k·Vin
IAN, IBN, ICN
Figure 3– AD7754 Sag detection
Figure 1— PGA in Channel 1
Figure 2 shows how the gain settings in the PGA’s in
Channel 1 and Channel 2 are selected by various bits in
the Gain register.
Figure 3 shows the line voltage fall below a threshold
which is set in the Sag Level register (SAGLVL[7:0]) for
nine half cycles. Since the Sag Cycle register
(SAGCYC[7:0]) contains 06h, the sag event is recorded
by setting the SAG flag in the Interrupt Status register. If
the SAG mask bit is set to logic one, the IRQ logic output
will go active low - see AD7754 Interrupts.
Sag Level Set
GAIN REGISTER*
Channel 1 and Channel 2 PGA Control
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
PGA 2 Gain Select
00 = x1
01 = x2
10 = x4
ADDR: 12h
PGA 1 Gain Select
00 = x1
01 = x2
10 = x4
*Register contents show power on defaults
The contents of the Sag Level register (1 byte) are compared to the absolute value of the most significant byte
output from LPF, after it is shifted left by one bit. Thus
for example the nominal maximum code from LPF with a
full scale signal on Channel 2 is 1C396h or
(0001, 1100, 0011, 1001, 0110b)—see Channel 2 sampling. Shifting one bit left will give
0011,1000,0111,0010,1100b or 3872Ch. Therefore writing 38h to the Sag Level register will put the sag detection
level at full scale. Writing 00h will put the sag detection
level at zero. The Sag Level register is compared to the
most significant byte of a waveform sample after the shift
left.
Figure 2— AD7754 Analog Gain register
REV. PrA 8/2000
–7–
AD7754
ZERO CROSSING DETECTION
POWER SUPPLY MONITOR
The AD7754 has a zero crossing detection circuit on
Channel 2. The zero crossing detection can be selected to
monitor the zero crossing for any combination of the VAP,
VBP, or VCP inputs. The input selection is made by setting
the bit 19 to 21 in the Mode register. Note that the inputs
monitored for zero crossing are also checked for voltage
sag - See Voltage SAG Detection section of this datasheet.
This zero crossing is also used in calibration mode - see
Energy Calibration. Figure 4 shows how the zero cross
signal is generated from the ADC of Channel 2.
The AD7754 also contains an on-chip power supply monitor. The Analog Supply (AVDD) is continuously
monitored by the AD7754. If the supply is less than 4V
±5% then the AD7754 will be reset. This is useful to
ensure correct device operation at power up and during
power down. The power supply monitor has built-in hysteresis and filtering. This gives a high degree of immunity
to false triggering due to noisy supplies.
As can be seen from Figure 5, the trigger level is nominally set at 4V. The tolerance on this trigger level is about
±5%. The power supply and decoupling for the part
should be such that the ripple at AVDD does not exceed
5V±10% as specified for nomal operation.
REFERENCE
x1, x2, x4
VAP, VBP, VCP
GAIN[3:2]
1
V2
PGA
TO
MULTIPLIER
-63% to + 63% FS
ADC
AVDD
VN
ZERO
CROSS
Zero Crossing
Detection
5V
4V
LPF
f-3dB = 290Hz
19.65 ⬚ @ 50Hz
1.0
0.74
ZX
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0V
V2
LPF
AD7754
Power-on
Reset
Figure 4– Zero cross detection on Channel 2
Time
Active
Reset
Reset
Figure 5 - On-Chip power supply monitor
Each zero crossing detection input has an internal time-out
register (ZXTOUTA, ZXTOUTB, ZXTOUTC) associated with it. This unsigned, 16 bit register is decremented
(1 LSB) every 48/CLKIN seconds. The register is reset to
its user programmed value in Zero Cross Time Out register (ZXTOUTA) every time a zero crossing is detected on
its associated input. The default power on value in this
register is FFFFh. If the register decrements to zero before a zero crossing at the corresponding input is detected,
it indicates an absence of a zero crossing in the time determined by the ZXTOUT. If the SAG/ZX detection for the
input is switched on, the SAG bit in the IRQ Status Register will be set. An active-low in the IRQ output will also
appear if the SAG mask bit in the Interrupt Mask register
is set to logic one.
The Zero cross Time-out register can be read or written
by the user and has an address of 0Ah - see Serial Interface
section.
TEMPERATURE MEASUREMENT
The AD7754 also includes an on-chip temperature sensor.
A temperature measurement is made every 3072/CLKIN
second. The resultant code is processed and placed in the
Temperature register (TEMP[7:0]). The CF pin can be
programed to vary its frequency output proportional to the
content of the Temperature register.
The contents of the Temperature register are signed (2's
complement) with a resolution of 1 LSB/°C. The temperature register will produce a code of 00h when the
abient temperature is approximately 70°C. The temperature in the AD7754 has an offset tolerance of
approximately ±5°C. The error can be easily calibrated by
MCU. By setting bits 13 and 14 to logic zero and logic
one, CF pin can be used to show the content of the temperature register. The frequency output of CF is centered
at 10kHz with a 10Hz/C resolution, i.e. the frequency
output of CF will be:
CF Output Frequency =
l
10kHz + 10 × Content of Temperature Register
–8–
q
REV. PrA 8/2000
AD7754
Figure 9.
AD7754 ANALOG TO DIGITAL CONVERSION
The analog-to-digital conversion in the AD7754 is carried
out using second order sigma-delta ADCs. The block
diagram in Figure 6 shows a first order (for simplicity)
sigma-delta ADC. The converter is made up of two parts,
first the sigma-delta modulator and secondly the digital
low pass filter.
Antialias filter (RC)
Digital filter
Shaped
Noise
Signal
Sampling
Frequency
Noise
CLKIN/12
0
Analog Low Pass Filter
+
R
Σ
-
2kHz
417kHz
兰
+
VREF
833kHz
Frequency (Hz)
Digital Low Pass Filter
INTEGRATOR
LATCHED
COMPARATOR
High resolution
output from Digital
LPF
Signal
-
1
20
C
....10100101......
Noise
1-Bit DAC
0
Figure 6– First-order Sigma-Delta (Σ−∆) ADC
A sigma-delta modulator converts the input signal into a
continuous serial stream of 1's and 0's at a rate determined
by the sampling clock. In the AD7754 the sampling clock
is equal to CLKIN/12. The 1-bit DAC in the feedback
loop is driven by the serial data stream. The DAC output
is subtracted from the input signal. If the loop gain is high
enough the average value of the DAC output (and therefore the bit stream) will approach that of the input signal
level. For any given input value in a single sampling interval, the data from the 1-bit ADC is virtually meaningless.
Only when a large number of samples are averaged, will a
meaningful result be obtained. This averaging is carried
out in the second part of the ADC, the digital low pass
filter. By averaging a large number of bits from the modulator the low pass filter can produce 20 bit data words
which are proportional to the input signal level.
The sigma-delta converter uses two techniques to achieve
high resolution from what is essentially a 1-bit conversion
technique. The first is over-sampling. By over sampling
we mean that the signal is sampled at a rate (frequency)
which is many times higher than the bandwidth of interest.
For example the sampling rate in the AD7754 is CLKIN/
12 (833kHz) and the band of interest is 40Hz to 2kHz.
Oversampling has the effect of spreading the quantization
noise (noise due to sampling) over a wider bandwidth.
With the noise spread more thinly over a wider bandwidth,
the quantization noise in the band of interest is lowered—
see Figure 7.
However, oversampling alone is not an efficient enough
method to improve the signal to noise ratio (SNR) in the
band of interest. For example, an oversampling ratio of 4
is required just to increase the SNR by only 6dB (1-Bit).
To keep the oversampling ratio at a reasonable level, it is
possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies. This is what
happens in the sigma-delta modulator, the noise is shaped
by the integrator which has a high pass type response for
the quantization noise. The result is that most of the noise
is at the higher frequencies where it can be removed by the
digital low pass filter. This noise shaping is also shown in
2kHz
417kHz
833kHz
Frequency (Hz)
Figure 7– Noise reduction due to Oversampling & Noise
shaping in the analog modulator
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Antialias Filter
Figure 6 also shows an analog low pass filter (RC) on the
input to the modulator. This filter is present to prevent
aliasing. Aliasing is an artifact of all sampled systems.
Basically it means that frequency components in the input
signal to the ADC which are higher than half the sampling
rate of the ADC will appear in the sampled signal at a
frequency below half the sampling rate. Figure 20 illustrates the effect, frequency components (arrows shown in
black) above half the sampling frequency (also know as
the Nyquist frequency, i.e., 417kHz) get imaged or folded
back down below 417kHz (arrows shown in grey). This
will happen with all ADCs no matter what the architecture. In the example shown it can be seen that only
frequencies near the sampling frequency, i.e., 833kHz,
will move into the band of interest for metering, i.e, 40Hz
- 2kHz. This fact will allow us to use a very simple LPF
(Low Pass Filter) to attenuate these high frequencies (near
900kHz) and so prevent distortion in the band of interest.
A simple RC filter (single pole) with a corner frequency of
10kHz will produce an attenuation of approximately
40dBs at 894kHz. This is sufficient to eliminate the effects of aliasing.
Gain Adjustment for Channel 1 inputs
The ADC gain for the inputs in Channel 1 (IA, IB and IC)
can be adjusted by using the multiplier and Active Power
Gain register in each phase (APGAIN, BPGAIN, and
CPGAIN). The gain of the ADC is adjusted by writing a
2’s complement 12 bit word to the Active Power Gain
registers. Below is the expression that shows how the gain
adjustment is related to the contents of the Active Power
Gain register in input IA.
Code =
FG ADC ¥ RS1+ APGAIN UVIJ
H
T 2 WK
12
For example when 7FFh is written to the Active Power
Gain register the ADC output is scaled up by 50%. 7FFh
= 2047 Dec, 2047/212 = 0.5. Similarly, 800h = -2048
REV. PrA 8/2000
–9–
AD7754
Dec (signed 2’s Complement) and ADC output is scaled
by –50%.
AD7754 HPF & Phase compensation
(calibrated at 55Hz)
0.6
PHASE COMPENSATION
When the HPF is disabled the phase error between the
inputs for Channel 1 (IA, IB and IC) and the corresponding inputs for Channel 2 (VA, VB, and VC) is zero from
DC to 3.5kHz. When HPF is enabled (by setting bit 0 of
Mode Register to logic zero), Channel 1 has a phase
response illustrated in Figure 8a & 8b. Also shown in
Figure 8c is the magnitude response of the filter. As can
be seen from the plots, the phase response is almost zero
from 45Hz to 1kHz, This is all that is required in typical
energy measurement applications.
0.5
Error (% reading)
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
42
46
50
54
58
62
66
Frequency (Hz)
0.3
Figure 8c – Gain response of HPF & Phase Compensation
(deviation of Gain as % of Gain at 54Hz)
0.25
0.2
Phase
[Degrees]
0.15
0.1
0.05
0
-0.05
-0.1
100
200
300
400
500
600
Frequency
[Hz]
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700
800
900
Figure 8a – Phase response of the HPF & Phase
Compensation (10Hz to 1kHz)
0.3
0.25
Phase
[Degrees]
0.2
0.15
0.1
0.05
0
-0.05
-0.1
However, despite being internally phase compensated the
AD7754 must work with transducers which may have inherent phase errors. For example a phase error of 0.1° to
0.3° is not uncommon for a CT (Current Transformer).
These phase errors can vary from part to part and they
must be corrected in order to perform accurate power
calculations. The errors associated with phase mismatch
are particularly noticeable at low power factors. The
AD7754 provides a means of digitally calibrating these
small phase errors. The AD7754 allows a small time delay
or time advance to be introduced into the signal processing chain in order to compensate for small phase errors.
Because the compensation is in time, this technique
should only be used for small phase errors in the range of
0.1° to 0.5°. Correcting large phase errors using a time
shift technique can introduce significant phase errors at
higher harmonics.
The Phase Calibration registers (APCAL, BPCAL,
CPCAL) are 2’s complement 8-bit signed registers which
can vary the time delay individually in the VA, VB and VC
signal paths. One LSB is equivalent to approximately 2µs
(CLKIN = 10MHz). With a line frequency of 50Hz this
gives a phase resolution of 0.036° at the fundamental (i.e.,
360° x 2µs x 50Hz). A time advance of 2µs is made by
writing -1 (FFh) to the time delay block, thus reducing
the amount of time delay by 2µs.
1000
ACTIVE POWER CALCULATION
40
45
50
55
Frequency
[Hz]
60
65
7
0
Figure 8b – Phase response of the HPF & Phase
Compensation (40Hz to 70Hz)
Electrical power is defined as the rate of energy flow from
source to load. It is given by the product of the voltage and
current waveforms. The resulting waveform is called the
instantaneous power signal and it is equal to the rate of
energy flow at any instant of time. Electrical power is typically measured in Watt, equivalence of Joules/second.
Equation 3 gives an expression for the instantaneous power
in an ac system.
v(t) =
2V sin(ωt )
i(t) =
2I sin(ωt )
–10–
REV. PrA 8/2000
AD7754
where V = rms voltage, I = rms current.
p(t) = v(t) × i(t)
p(t) = VI - VI cos( 2ωt )
Figure 11 shows the signal processing chain in each phase
for the active power calculation in the AD7754. As
explained, the Active Power is calculated by low pass
filtering the instantaneous power signal. Note that for
simplification purpose, the Gain and Offset are not shown
in this figure.
!
The average power over an integral number of line cycles
(n) is given by the expression in Equation 4.
1
P =
nT
HPF
nT
z
p(t)dt = VI
"
Current Signal - i(t)
-63% to +63% FS
0
where T is the line cycle period.
P is referred to as the Active or Real Power. Note that
active power is equal to the dc component of the instantaneous power signal p(t) in Equation 3 , i.e., VI. This is
the relationship used to calculate active power in the
AD7754. The instantaneous power signal p(t) is generated
by multiplying the current and voltage signals in each
phase. The dc component of the per phase instantaneous
power signal is then extracted by a low pass filter (LPF)
after multiplication to obtain the active power information.
In a polyphase system, the total electrical power is simply
the sum of the real power in all active phases. This process
is illustrated graphically in Figure 9.
Instantaneous
Power Signal
1999Ah
Active Power
Signal = V x I
V. I.
LPF
2851Fh
MULTIPLIER
00h
D7AE1h
Instantaneous Power Signal - p(t)
-40% to +40% FS
1
V
1999Ah
Voltage Signal - v(t)
-63% to + 63% FS
00h
2851Fh
00h
D7AE1h
Figure 11 — Active Power Signal Processing in
an activated phase
The sum of all phases’ active power gives the total active
power consumption. Any combination of the three phases
can be included in the sum by setting bits 16 to 18 of the
Mode register. Figure 12 shows how the total active power
is calculated. Similar to Figure 11, the Gain and Offset
are omitted in this figure.
HPF
IA
PHASE A*
00000h
Current
VA
i(t) = √2 × I sin(2ωt)
Voltage
v(t) = √2 × V sin(2ωt)
PHASE B*
VB
Figure 9– Active Power Calculation
-4
dB
-8
-12
-16
-20
Total Instantaneous
Power Signal
HPF
LPF
20
Active Power
Signal - P
26667h
1
HPF
IC
LPF
20
PHASE C*
VC
1
*Phases to be included in the total active power calculation is determined by bits 16 to 18 of Mode register
Figure 12 — Total Active Power Consumption Calculation
3.0Hz
10Hz
30Hz
100Hz
Frequency
Figure 10 —Frequency Response of the LPF used
for Filtering Instantaneous Power in each phase
REV. PrA 8/2000
1
Shown in Figure 13 is the maximum code (Hexadecimal)
output range for the active power signal in each phase.
Note that the output range changes depending on the contents of the Active Power Gain register of that phase. The
minimum output range is given when the Active Power
Gain register content is equal to 800h and the maximum
range is given by writing 7FFh to the Active Power Gain
register. This can be used to calibrate the Active Power
(or Energy) calculation in the AD7754.
0
-24
1.0Hz
LPF
20
IB
Since the LPF does not have an ideal “brick wall” frequency response—see Figure 10, the active power signal
will have some ripples due to the residual high frequency
component in the instantaneous power signal. This ripple
is sinusoidal and has a frequency equal to twice the line
frequency. Since the ripple is sinusoidal in nature it will be
removed when the Active Power signal is integrated to
calculate Energy – see Energy Calculation.
CCCDh
20
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p(t) = V × I - V × I cos(2ωt)
CCCDh
Active Power
Signal - P
I
–11–
Output LPF
AD7754
1999Ah
CCCDh
6666h
00000h
F999Ah
F3333h
E6666h
000h
Positive
Power
- 10% FS
- 20% FS
Negative
Power
Note that the energy register contents will roll over to
full-scale negative (400,0000,0000h) and continue increasing in value when the power or energy flow is
positive - see Figure XX. Conversely if the power is negative the energy register would under flow to full scale
positive (1FF,FFFF,FFFFh) and continue decreasing in
value.
By using the Interrupt Enable register, the AD7754 can be
configured to issues an interrupt (IRQ) when the Active
Energy register is half full (positive or negative) or when
an over/under flow occurs.
- 30% FS
800h
7FFh
+ 30% FS
+ 20% FS
+ 10% FS
APGAIN[11:0]
Range of Active Power
Calibration in each Phase
Figure 13 – Active Power Calculation Output Range
Integration times under steady load
ENERGY CALCULATION
As stated earlier, power is defined as the rate of energy
flow. This relationship can be expressed mathematically as
Equation 5.
dE
dt
Where P = Power and E = Energy.
Conversely Energy is given as the integral of Power.
P=
z
E = Pdt
(5)
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(6)
The AD7754 achieves the integration of the Active Power
signal by continuously accumulating the Active Power
signal in the 42-bit Active Energy register
(AENERGY[41:0]). This discrete time accumulation or
summation is equivalent to integration in continuous time.
Equation 7 below expresses the relationship
E=
z
As mentioned in the last section, the discrete time sample
period (T) for the accumulation register is 1.2µs (12/
CLKIN). With full-scale sinusoidal signals on all analog
inputs and the Active Power Gain register set to 000h, the
average word value from LPF on each channel is
CCCDh. The maximum value which can be stored in the
Active Energy register before it over flows is 241-1 or
1FF,FFFF,FFFFh. Therefore the integration time under
these conditions is calculated as follows:
R| p(nT ) × T U|
V|
S|∑
W
T
∞
p(t)dt = Lim
T →0
n =0
(7)
Where n is the discrete time sample number and T is the
sample period. The discrete time sample period (T) for
the accumulation register in the AD7754 is 1.2µs (12/
10MHz). As well as calculating the Energy this integration removes any sinusoidal components which may be in
the Active Power signal. Figure 14 shows a graphical
representation of this discrete time integration or accumulation. The Active Power signal in the Waveform register
is continuously added to the Active Energy register. This
addition is a signed addition, therefore negative energy
will be subtracted from the Active Energy contents.
T
+
TOTAL ACTIVE POWER
Σ
41
AENERGY[41:0]
0
+
Active Power
Signal - P
T
TOTAL ACTIVE POWER ARE
ACCUMULATED (INTEGRATED) IN
THE ACTIVE ENERGY REGISTER
Time =
1FF,FFFF, FFFFh
. µs = 16.78 seconds
× 12
3 × CCCDh
POWER OFFSET CALIBRATION
The AD7754 also incorporates an Active Power Offset
register on each phase (APOS, BPOS, or CPOS) Theses
are signed 2’s complement 8-bit registers which can be
used to remove offsets in the active power calculations. An
offset may exist in the power calculation due to cross talk
between channels on the PCB or in the IC itself. The
offset calibration will allow the contents of the Active
Power register to be maintained at zero when no power is
being consumed.
Four LSBs in the Active Power Offset register are equivalent to 1 LSB in the Active Energy register. Each time
power is added to the Active Energy register, the content
of the Active Power Offset register will be added. Assuming the average value from LPF is CCCDh (52,429) with
full ac scale inputs on Channel 1 and Channel 2 , then 1
LSB in the LPF output is equivalent to 1.9% of measurement error at -60dB down on full scale.
That is at -60dB down on full scale (the input signal level
is 1/1000 of the full-scale signal input) the average word
value from LPF is 52.429 (52,429/1,000). One LSB is
equivalent to 1/52.429 x 100% = 1.9% of the measured
value. The Active Power Offset register has a resolution
equal to 1/16 LSB of the LPF output, hence the power
offset correction resolution is 0.12% (1.9%/16) at -60dB.
ENERGY CALIBRATION
26667h
00000h
time (nT)
Figure 14 – AD7754 Energy Calculation
AD7754 is desinged with a dedicated calibration mode to
simplfy calibration process. By using the on-chip zerocrossing detection, AD7754 can accurately measure the
accumulation time of active energy in each phase. The
calibration mode is activated by setting bit CMODE in
the Mode register. In Calibration Mode the AD7754 ac–12–
REV. PrA 8/2000
AD7754
cumulates Active Power signal of each individual phase in
the corresponding Active Calibration Energy registers
(AAENRGY, BAENERGY, CAENERGY) for an integral
number of half cycles. The number of half line cycles is
specified in the CALCYC register. The AD7754 can accumulate Active Power for up to 255 half cycles in each
phase. Because the Active Power is integrated on an integral number of line cycles the sinusoidal component is
reduced to zero. This eliminates any ripple in the energy
calculation. Energy is calculated more accurately because
of this precise timing control. At the end of an energy
calibration cycle the SAG flag in the Interrupt Status register is set. If the SAG mask bit in the Interrupt Mask
register is enabled, the IRQ output will also go active low.
Thus the IRQ line can be used to signal the end of a calibration also. Another calibration cycle will start as long as
the CMODE bit in the Mode register is set. From equations 5 and 11.
nT
E(t) =
z
RS VI UV z cosa2wtfdt
T1 + f / 8.9Hz W
nT
VI dt −
0
0
!
E(t) =
z
VI dt + 0
(14)
0
E(t) = VInT
(15)
CALIBRATING THE ENERGY METER
Calculating the Average Active Power
Average word (LPF) =
(16)
Calibrating the Frequency at CF
Once the average Active Power signal is calculated it can
be used to determine the frequency at CF before calibration. When the frequency before calibration is know the
CF Scaling Numerator and Denominator registers
(CFNUM and CFDEN) and the Active Power Gain register (APGAIN, BPGAIN, and CPGAIN) can be adjusted
so as to produce the required frequency on CF. In this
example a meter constant of 3200 imp/kWh is chosen.
This means that under a steady load of 1kW, the output
frequency on CF would be:
Frequency (CF) =
3200 imp / kWh 3200
=
= 0.8888Hz
60min × 60sec
3600
Eenrgy Meter Display
Active Energy register (AENERGY) can be used to calculate energy. A full description of this register can be found
in the Active Energy Calculation section. The AENERGY
register gives the user both sign and magnitude information regarding energy consumption. On completion of the
CF frequency output calibration, i.e., after the Active
Power Gain registers (APGAIN, BPGAIN, and
CPGAIN) have been adjusted the kWh/LSB coefficient for
the AENERGY register can be determinded. Once the
coefficient has been calculated the MCU can determine
the energy consumption at any time by reading the
AENERGY contents and multiplying by the coefficient to
calculate kWh.
When calibrating the AD7754, the first step is to calibrate
the frequency on CF to some required meter constant,
e.g., 3200 imp/kWh. In order to determine the output
frequency on CF, the average value of the Active Power
signal in each phase (output of LPF after the multiplier in
each phase) must first be determined. One convenient way
to do this is to use the calibration mode. When the
CMODE bit in the Mode register is set to a logic one,
energy is accumulated over an integer number of half line
cycles as described in the last section. Since the line frequency is fixed at, say 60Hz and the number of half cycles
of integration is specified, the total integration time is
given as :
1
× no. of half cycles
2 × 60Hz
For 255 half cycles this would give a total integration time
of 2.125 seconds. This would mean the energy register in
each phase was updated 2.125 / 1.2µs (12/CLKIN) times.
For example, the average output value of LPF in phase A
REV. PrA 8/2000
AAENERGY[32:0] × 24 × fl
CALCYC[7:0]× CLKIN
where fl is the line frequency. Similarly, the average word
for other phases can be calculated.
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where n is a integer and T is the line cycle period.
Since the sinusoidal component is integrated over a integer number of line cycles its value is always zero.
Therefore:
nT
is given as :
–13–
AD7754
AD7754 SERIAL INTERFACE
AD7754 has a built-in SPI interface. The Serial Interface
of the AD7754 is made up of four signals SCLK, DIN,
DOUT and CS. The serial clock for a data transfer is
applied at the SCLK logic input. This logic input has a
schmitt-trigger input structure, which allows slow rising
(and falling) clock edges to be used. All data transfer operations are synchronized to the serial clock. Data is
shifted into the AD7754 at the DIN logic input on the
falling edge of SCLK. Data is shifted out of the AD7754
at the DOUT logic output on a rising edge of SCLK. The
CS logic input is the chip select input. This input is used
when multiple devices share the serial bus. A falling edge
on CS also resets the serial interface and places the
AD7754 in communications mode. The CS input should
be driven low for the entire data transfer operation. Bringing CS high during a data transfer operation will abort the
transfer and place the serial bus in a high impedance state.
The CS logic input may be tied low if the AD7754 is the
only device on the serial bus. However with CS tied low,
all initiated data transfer operations must be fully completed, i.e., the LSB of each register must be transferred
as there is no other way of bringing the AD7754 back into
communications mode without resetting the entire device,
i.e., setting the RESET pin logic low.
All AD7754 functionality is accessible via several on-chip
registers – see Figure 15. The contents of these registers
can be updated or read using the on-chip serial interface.
After power-on or toggling the RESET pin low or a falling edge on CS, the AD7754 is placed in communications
mode. In communications mode the AD7754 expects the
first communication to be a write to the internal Communications register. The data written to the
Communications register contains the address and specified the next data transfer to be a read or a write
command. Therefore all data transfer operations with the
AD7754, whether a read or a write, must begin with a
write to the Communications register.
DOUT
COMMUNICATIONS REGISTER
REGISTER # 1
CS
SCLK
COMMUNICATIONS REGISTER WRITE
DIN
0 0 0
ADDRESS
MULTIBYTE READ DATA
DOUT
Figure 16 – Reading data from the AD7754 via the
serial interface
CS
SCLK
COMMUNICATIONS REGISTER WRITE
DIN
1 0 0
ADDRESS
MULTIBYTE WRITE DATA
Figure 17 – Writing data to the AD7754 via the
serial interface
A data transfer is completed when the LSB of the AD7754
register being addressed (for a write or a read) is transferred to or from the AD7754.
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IN
OUT
REGISTER # 2
IN
OUT
REGISTER # 3
IN
OUT
REGISTER # n-1
IN
OUT
REGISTER # n
IN
OUT
REGISTER ADDRESS
DECODE
DIN
Figure 16 and Figure 17 show the data transfer sequences
for a read and write operation respectively.
On completion of a data transfer (read or write) the
AD7754 once again enters communications mode, i.e. the
next instruction followed must be a write to the Communications register.
Figure 15– Addressing AD7754 Registers via the
Communications Register
The Communications register is an eight bit write only
register. The MSB determines whether the next data
transfer operation is a read or a write. The 6 LSBs contain
the address of the register to be accessed. See AD7754
Communications Register for a more detailed description.
AD7754 Serial Write Operation
The serial write sequence takes place as follows: with the
AD7754 in communications mode and the CS input logic
low, a write to the communications register first takes
place. The MSB of this byte transfer must be set to 1,
indicating that the next data transfer operation is a write
to the register. The six LSBs of this byte contain the address of the register to be written to. The AD7754 starts
shifting in the register data on the next falling edge of
SCLK. All remaining bits of register data are shifted in on
the falling edge of subsequent SCLK pulses – see Figure
18.
As explained earlier the data write is initiated by a write to
the Communications register followed by the data. During
a data write operation to the AD7754, data is transferred
to all on-chip registers one byte at a time. After a byte is
transferred into the serial port, there is a finite time duration before the content in the serial port buffer is
transferred to one of the AD7754 on-chip registers. Although another byte transfer to the serial port can start
while the previous byte is being transferred to the destination register, this second byte transfer should not finish
until at least 5µs after the end of the previous byte transfer. This functionality is expressed in the timing
specification t6 - see Figure 18. If a write operation is
aborted during a byte transfer (CS brought high), then
that byte will not be written to the destination register.
Destination registers may be up to 3 bytes wide – see
AD7754 Register Descriptions. Hence the first byte shifted
into the serial port at DIN is transferred to the MSB
(Most significant Byte) of the destination register. If the
destination register is 12 bits wide, for example, a twobyte data transfer must take place. The data is always
assumed to be right justified, therefore in this case, the
–14–
REV. PrA 8/2000
AD7754
All remaining bits of register data are shifted out on subsequent SCLK rising edges. The serial interface enters
communications mode again as soon as the read has been
completed. The DOUT logic output enters a high impedance state on the falling edge of the last SCLK pulse. The
read operation may be aborted by bringing the CS logic
input high before the data transfer is complete. The
DOUT output enters a high impedance state on the rising
edge of CS.
When an AD7754 register is addressed for a read operation, the entire contents of that register are transferred to
the Serial port. This allows the AD7754 to modify its onchip registers without the risk of corrupting data during a
multi byte transfer.
Note when a read operation follows a write operation, the
read command (i.e., write to communications register)
should not happen for at least 4µs after the end of the
write operation. If the read command is sent within 4µs of
the write operation, the last byte of the write operation
may be lost. The is given as timing specification t15.
four MSBs of the first byte would be ignored and the 4
LSBs of the first byte written to the AD7754 would be the
4MSBs of the 12-bit word. Figure 19 illustrates this example.
AD7754 Serial Read Operation
During a data read operation from the AD7754 data is
shifted out at the DOUT logic output on the rising edge
of SCLK. As was the case with the data write operation, a
data read must be preceded with a write to the Communications register.
With the AD7754 in communications mode and CS logic
low an eight bit write to the Communications register first
takes place. The MSB of this byte transfer must be a 0,
indicating that the next data transfer operation is a read.
The six LSBs of this byte contain the address of the register which is to be read. The AD7754 starts shifting out of
the register data on the next rising edge of SCLK – see
Figure 20. At this point the DOUT logic output switches
from high impedance state and starts driving the data bus.
CS
t1
t2 t3
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t8
t6
t7
SCLK
t4
0
1
DIN
0
t7
t5
A4 A3 A2 A1 A0
DB7
DB0
DB7
Most Significant Byte
Command Byte
DB0
Least Significant Byte
Figure 18– Serial Interface Write Timing Diagram
SCLK
DIN
X
X
X
X
DB11 DB10 DB9
DB8
DB7
Most Significant Byte
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Least Significant Byte
Figure 19—12 bit Serial Write Operation
CS
t1
t9
t14
t10
SCLK
DIN
0
0
0
A4 A3 A2 A1 A0
DOUT
DB7
Figure 20– Serial Interface Read Timing Diagram
REV. PrA 8/2000
DB0
Most Significant Byte
Command Byte
–15–
t13
t12
t11
DB7
DB0
Least Significant Byte
AD7754
ACCESSING THE AD7754 ON-CHIP REGISTERS
All AD7754 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the communications register and then transferring the register data. For a full description of the serial interface protocol, see Serial
Interface section of this data sheet.
Communications Register
The Communications register is an eight bit, write-only register which controls the serial data transfer between the
AD7754 and the host processor. All data transfer operations must begin with a write to the communications register. The
data written to the communications register determines wheather the next operation is a read or a write and which register is being accessed. Table I below outlines the bit designations for the Communications register.
Table I Communications Register
Bit
Location
Bit
Mnemonic
Description
0 to 5
A0 to A5
The five LSBs of the Communications register specify the register for the data transfer
operation. Table II lists the address of each AD7754 on-chip register.
6
RESERVED
This bit is unused and should be set to zero.
7
W/ R
When this bit is a logic one the data transfer operation immediately following the write to
the Communications register will be interpreted as a write to the AD7754. When this bit
is a logic zero the data transfer operation immediately following the write to the Communications register will be interpreted as a read operation.
DB7
DB6
W/R
0
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DB4
DB3
DB2
DB1
DB0
A5
A4
A3
A2
A1
A0
–16–
REV. PrA 8/2000
AD7754
Table II. AD7754 REGISTER LIST
A5 A4 A3 A2 A1 A0
Hex
Name
R / W*
Description
0
0
0
0
0
0
0
0
0
0
0
1
00h
01h
Reserved
AENERGY
R
0
0
0
0
1
0
02h
RAENERGY R
0
0
0
0
0
0
0
1
1
0
1
0
03h
04h
FREQ
MODE
R
RW
0
0
0
1
0
1
05h
MASK
RW
0
0
0
1
1
0
06h
STATUS
RW
0
0
0
1
1
1
07h
0
0
1
0
0
0
08h
0
0
1
0
0
1
09h
0
0
1
0
1
0
0Ah
0
0
1
0
1
1
0Bh
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0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
Reserved.
Active Energy register. This register is a 42 bits readonly register. Active power is accumulated over time in
this read-only register. The AENERGY register can
hold a minimum of 5 seconds of active energy information with full-scale analog inputs before it overflows See Energy Calculation.
Same as the AENERGY register except that the register
is reset to zero following a read operation.
This register is a 8-bit read-only register.
Mode Register. This is a 24 bit register through which
most of AD7754 functionality is accessed. See Mode
Register.
IRQ Mask register. This is eight bit register determines
if an interrupt event will generate an active-low output at
143 pin - see AD7754 Interrupts.
IRQ Status register. This is an eight bit read-only register. This register contains information regarding the
source of AD7754 interrupts - see AD7754 Interrupts.
Same as the STATUS register. This is an eight except
that the register contents are reset to zero (all flags
cleared) after a read operation.
Temperature register. This is an eight-bit register which
contains the result of the latest temperature conversion.
Please refer to Temperature Measurement section on this
datasheet for details on how to interpret the content of
this register.
Waveform register. This is a 24-bit read-only register.
This register contains the digitized waveform of one of
the six analog inputs. The source is selected by data bits
10 to 12 in the Mode register.
Zero Cross Time Out register. If no zero crossing is
detected within a time period specified by this register
the interrupt request line (143) will go active low. The
maximum time - out period is 2.3 seconds - see Zero
Crossing Detection.
Calibration Cycle register. The content of this register
sets the number of line cycles active energy is accumulated in calibration mode - See Energy Calibration.
Sag Line Cycle register. This register specifies the number of consecutive half-line cycles that Channel 2 input
falls below a threshold level. Bit 19 to 21 of the Mode
register determines which input to be monitored. The
detection threshold is specified by SAGLVL register See Voltage SAG Detection.
SAG Voltage Level. This register specifies the detection
threshold for SAG event. See the description of
SAGCYC register for details.
Peak Voltage Value register.
Peak Current Value register.
Channel 1 Offset Compensation register.
Channel 2 Offset Compensation register.
PGA Gain register. This 8-bit registeris used to adjust
the gain selection for the PGA in Channel 1 and 2 - See
Analog Inputs.
Active Power Gain register. This register calculation can
be calibrated by writing to this register. The calibration
range is 50% of the nominal full scale active power. The
resolution of the gain adjust is 0.0244% / LSB.
REV. PrA 8/2000
RSTATUS
R
TEMP
R
WFORM
R
ZXOUT
RW
CALCYC
RW
0Ch
SAGCYC
RW
1
0Dh
SAGLVL
RW
1
1
0
0
1
0
1
0
1
0
0Eh
0Fh
10h
11h
12h
PKVLVL
PKILVL
VOS1
VOS2
GAIN
RW
RW
RW
RW
RW
1
1
13h
APGAIN
RW
–17–
AD7754
A5
0
0
0
0
0
0
0
0
0
A4
1
1
1
1
1
1
1
1
1
A3
0
0
0
0
1
1
1
1
1
A2
1
1
1
1
0
0
0
0
1
A1
0
0
1
1
0
0
1
1
0
A0
0
1
0
1
0
1
0
1
0
Hex
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
Name
BPGAIN
CPGAIN
APCAL
BPCAL
CPCAL
APOS
BPOS
CPOS
CFNUM
R / W*
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
1
1
1
0
1
1Dh
CFDEN
RW
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
Reserved
Reserved
Reserved
AAENERGY
BAENERGY
CAENERGY
AVCAL
BVCAL
CVCAL
AICAL
BICAL
CICAL
R
R
R
R
R
R
R
R
R
Description
Phase B Active Power Gain register.
Phase C Active Power Gain register
Phase A Calibration register.
Phase B Calibration register.
Phase C Calibration register.
Phase A Power Offset register.
Phase B Power Offset register.
Phase C Power Offset register.
CF Scaling Numerator register. The content of this 8bit register is used in the numerator of CF output
scaling.
CF Scaling Denominator register. The content of this 8bit register is used in the denominator of CF output
scaling.
Reserved.
Reserved.
Reserved.
Phase A Energy Calibration register.
Phase B Energy Calibration register.
Phase C Energy Calibration register.
Phase A Voltage Calibration register.
Phase B Voltage Calibration register.
Phase C Voltage Calibration register.
Phase A Current Calibration reigster.
Phase B Current Calibration register.
Phase C Current Calibration register.
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*R/W: Read/Write capability of the register.
R: Read only register.
RW: Register that can be both read and written.
–18–
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AD7754
Mode Register (04h)
Many of the AD7754 functionality is configured by writing to the MODE register. Table III below summarizes the functionality of each bit in the MODE register .
Table III Mode Register
Bit
Location
Bit
Mnemonic
Description
0
DISHPF
The HFP (High Pass Filter) in all Channel 1 inputs are disabled when this bit is set.
1
DISLPF
The LPF (Low Pass Filter) in all Channel 1 inputs are disabled when this bit is set.
2
DISCF
The Frequency output CF is disabled when this bit is set
3
DISMOD1
ADC for Channel 1 inputs are internally shorted together when this bit is set.
4
DISMOD2
ADC for Channel 2 inputs are internally shorted together when this bit is set.
5
SWAP
By setting this bit to logic 1 the analog inputs to Channel 1 are connected to the ADC
for Channel 2 and the analog inputs to Channel 2 are connected to the ADC for Channel 1.
6
RESERVED
This is intended for factory testing only and should be left at zero.
7
SWRST
Software chip reset. A data transfer should not take place to the AD7754 for at least
18µs after a software reset.
8,9
DTRT[1:0]
These bits are used to select the Waveform Register update rate
DTRT0
Update Rate
0
0
27.9kSPS (CLKIN/128)
1
14kSPS (CLKIN/256)
0
7kSPS (CLKIN/512)
1
3.5kSPS (CLKIN/1024)
0
1
1
10-12
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WAVSEL[2:0] These bits are used to select the source of the sampled data for the Waveform Register
WAVSEL2
WAVSEL0
Source
0
0
VA
0
1
VB
1
0
VC
1
1
IA
0
0
IB
0
1
IC
1
1
0
RESERVED
1
1
1
RESERVED
0
0
0
0
1
1
13,14
15
CFSRC[1:0]
CFSCAL
REV. PrA 8/2000
WAVSEL1
Thses bits are used to select the source of pin output.
CFSRC1
CFSRC0
Source
0
0
Total Energy
0
1
Use WAVSEL
1
0
Temperature
1
1
Frequency
Writing a logic one to this bit causes the CF pin to switch to bi-polar frequency mode.
–19–
AD7754
Bit
Location
Bit
Mnemonic
16-18
WATSEL[2:0] These bits are used to select the source of energy calculation.
Description
WATSEL2
19-21
SZSEL[2:0]
WATSEL1
WATSEL0
Source
0
0
0
All Phases
0
0
1
Phases A and B
0
1
0
Phases A and C
0
1
1
Phases A Only
1
0
0
Phase B and C
1
0
1
Phase B Only
1
1
0
Phase C Only
1
1
1
RESERVED
These bits are used to select the source of SAG/Zero Crossing detection.
SZSEL2
SZSEL1
SZSEL0
Source
0
0
0
VA, VB, and VC
0
0
1
VA and VB
0
1
0
VA and VC
1
1
VA Only
0
0
VB and VC
0
1
VB Only
1
0
V C Only
1
1
SAG/ZX DETECTION DISABLE
0
1
1
1
1
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CFLABS
Writing a logic one to this bit will cause the AD7754 to use the absolute value in Calibration mode.
23
RESERVED
This is intended for factory testing only and should be left at zero.
MODE REGISTER*
23
22
21
20
19
18
0
0
0
0
0
0
RESERVED = 0
CALABS
(Use absolute value for calibration)
SZSEL
(SAG/Zero Crossing phase selection)
000 = VA
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
ADDR: 04h
DISHPF
(Disable HPF in Channel 1)
DISLPF
(Disable LPF after multiplication)
DISCF
(Disable Frequency output CF)
001 = VB
010 = VC
DISMOD1
(Disable all inputs from Channel 1)
011 = IA
100 = IB
DISMOD2
(Disable all inputs from Channel 2)
101 = IC
110 , 111 = RESERVED
SWAP
(Swap CH1 & CH2 ADCs)
WATSEL
(Phase selection for energy calculation)
000 = All three phases
001 = Phase A and B
010 = Phase A and C
011 = Phase A Only
100 = Phases B and C
101 = Phase B Only
110 = Phases C Only
111 = RESERVED
RESERVED=0
SWRST
(Software chip reset)
DTRT
(Waveform samples output data rate)
00 = 27.9kSPS (CLKIN/128)
01 = 14.4 kSPS (CLKIN/256)
10 = 7.2 kSPS (CLKIN/512)
11 = 3.6 kSPS (CLKIN/1024)
CFSCAL
(Frequency Mode Selection for CF)
Unipolar = 0
Bipolar = 1
WAVSEL
(Waveform selection for sample mode)
000 = VA
001 = VB
CFSRC
(Source selection for CF output)
00 = Total Wattage
01 = Use WAVSEL
10 = Temperature
11 = Frequency
010 = VC
011 = IA
100 = IB
101 = IC
110 , 111 = RESERVED
–20–
REV. PrA 8/2000
AD7754
Interrupt Mask Register (05h)
When an interrupt event occurs in the AD7754, the IRQ logic output goes active low if the mask bit for this event is
logic one in this register. The following describes the function of each bit in the Interrupt Mask Register.
Bit
Location
Interrupt
Flag
0
AEHF
Enables an interrupt when there is a 0 to 1 transition of the MSB of the AENERGY
register (i.e. the AENERGY register is half-full)
1
SAG
Enables an interrupt when there is a SAG on the line voltage or no zero crossing were
detected.
2
ZX
Enables an interrupt when there is a zero crossing in Channel 2—Zero Crossing Detection
3-5
RESERVED
These bits should be set to zero.
6
WFSM
Enables an interrupt when new data is present in the Waveform Register.
7
AEOF
Enables an interrupt when the Active Energy register has overflowed
Description
INTERRUPT MASK REGISTER*
7
6
0
0
5
0
4
3
2
1
0
0
0
0
0
0
ADDR: 05h
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AEOF
(Active Energy Register Over Flow)
WFMP
(New Waveform Sample Ready)
RESERVED = 0
AEHF
(Active Energy Register Half Full)
SAG
(SAG Event Detect)
ZX
(Zero Crossing Detect)
*Register contents show power on defaults
Interrupt Status Register (06h) / Reset Interrupt Status Register (07h)
The Interrupt Status Register is used to determine the source of an interrupt event. When an interrupt event occurs in the
AD7754, the corresponding flag in the Interrupt Status Register is set logic high. The 143 pin will go active low if the
corresponding bit in the Interrupt Mask register is set logic high. When the MCU services the interrupt, it must first
carry out a read from the Interrupt Status Register to determine the source of the interrupt.
Bit
Location
Interrupt
Flag
Event
Description
0
AEHF
Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the
AENERGY register (i.e. the AENERGY register is half-full)
1
SAG
Indicates that an interrupt was caused by a SAG on the line voltage or no zero crossing
were detected. In calibration mode this flag is also used to indicate the end of an integration over an integer number of half line cycles—see Energy Calibration
2
ZX
Indicates a detection of zero crossing in Channel 2—Zero Crossing Detection
3
ZXDIR
Shows the direction of the zero crossing—Zero Crossing Detection
6
WFSM
Indicates that new data is present in the Waveform Register.
7
AEOF
Indicates that the Active Energy register has overflowed
INTERRUPT STATUS REGISTER*
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
AEOF
(Active Energy Register Over Flow)
ADDR: 06h/07h
AEHF
(Active Energy Register Half Full)
WFMP
(New Waveform Sample Ready)
SAG
(SAG Event Detect)
ZX
(Zero Crossing Detect)
RESERVED = 0
ZXDIR
(Zero Crossing Direction)
*Register contents show power on defaults
REV. PrA 8/2000
–21–
AD7754
should be disabled using the global interrupt mask bit. At
this point the MCU external interrupt flag can be cleared
in order to capture interrupt events which occur during the
current ISR. When the MCU interrupt flag is cleared a
read from the Status register with reset is carried out.
This will cause the IRQ line to be reset logic high (t2)—
see Interrupt timing. The Status register contents are used
to determine the source of the interrupt(s), and hence
appropriate action can be taken. If a subsequent interrupt
event occurs during the ISR (t3), that event will be recorded by the MCU external interrupt flag being set
again. On returning from the ISR, the global interrupt
mask will be cleared (same instruction cycle) and the external interrupt flag will cause the MCU to jump to its
ISR once again. This will ensure that the MCU does not
miss any external interrupt.
AD7754 INTERRUPTS
AD7754 Interrupts are managed through the Interrupt
Status register (STATUS[7:0]) and the Interrupt Mask
register (MASK[7:0]). When an interrupt event occurs in
the AD7754, the corresponding bit in the Status register is
set to a logic one - see Interrupt Status register. If the
mask bit for this interrupt event in the Interrupt Mask
register is set to logic one, then the IRQ pin will go active
low. The status bits in the Status register are set irrespective of the state of the mask bits.
In order to determine the source of the interrupt, the system master (MCU) should perform a read from the Status
register with reset. This is achieved by carrying out a read
from address 07h. The IRQ pin will go logic high on
completion of the Interrupt Status register read command—see Interrupt timing. When carrying out a read with
reset the AD7754 is designed to ensure that no interrupt
events are missed. If an interrupt event occurs just as the
Status register is being read, the event will not be lost and
the IRQ logic output is guaranteed to go high for the duration of the Interrupt Status register data transfer before
going logic low again to indicate the pending interrupt.
See the next section for a more detailed description.
Interrupt timing
The AD7754 Serial Interface section should be reviewed
first before reviewing the interrupt timing. As previously
described, when the IRQ output goes low the MCU ISR
must read the Interrupt Status register in order to determine the source of the interrupt. When reading the Status
register contents, the IRQ output is set high on the last
falling edge of SCLK of the first byte transfer (read Interrupt Status register command). The IRQ output is held
high until the last bit of the next 8-bit transfer is shifted
out (Interrupt Status register contents). See Figure 22. If
an interrupt is pending at this time, the IRQ output will
go low again. If no interrupt is pending the IRQ output
will stay high.
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Using the AD7754 Interrupts with a MCU
Shown in Figure 21 is a timing diagram which shows a
suggested implementation of AD7754 interrupt management using an MCU. At time t1 the IRQ line will go
active low indicating that interrupt event(s) have occurred
in the AD7754. The IRQ logic output should be tied to a
negative edge triggered external interrupt on the MCU.
On detection of the negative edge, the MCU should be
configured to start executing its Interrupt Service Routine
(ISR). On entering the ISR, all interrupts detection
t2
t1
IRQ
MCU Program
Sequence
Global int.
Mask Set
Jump to
ISR
Clear MCU
int. flag
Read
Status with
Reset (05h)
MCU
int. flag set
t3
ISR Action
(Based on Status contents)
ISR Return
Global int. Mask
Reset
Jump to
ISR
Figure 21– AD7754 interrupt management
CS
t1
t9
SCLK
DIN
0
0
0
0
0
1
0
1
t12
t11
DOUT
DB7
Read Status Register Command
DB0 DB7
DB0
Status Register Contents
IRQ
Figure 22– AD7754 interrupt timing
–22–
REV. PrA 8/2000