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APPLIED PHYSICS LETTERS 93, 073503 共2008兲
Improved carrier injection in gate-all-around Schottky barrier silicon
nanowire field-effect transistors
J. W. Peng,1,2 S. J. Lee,1,a兲 G. C. Albert Liang,1 N. Singh,2 S. Y. Zhu,2 G. Q. Lo,2 and
D. L. Kwong2
1
Silicon Nano Device Lab, Department of Electrical and Computer Engineering, National University of
Singapore, Singapore 117576, Singapore
2
Institute of Microelectronics, 11 Science Park Road, Science Park II, Singapore 117685, Singapore
共Received 20 May 2008; accepted 30 July 2008; published online 22 August 2008兲
This letter presents the performance improvement of Schottky barrier metal-oxide-semiconductor
field-effect transistor by employing gate-all-around 共GAA兲 Si-nanowire 共SiNW兲 structure. Without
employing any barrier lowering technique, the mid-band-gap Ni-silicide Schottky barrier transistors
demonstrated excellent performance and achieved subthreshold slope of ⬃86 mV/ decade and
on-current of 19 ␮A / ␮m on a 12.5 nm SiNW, and subthreshold slope of ⬃79 mV/ decade and
on-current of 207 ␮A / ␮m on a 4 nm diameter SiNW. Assisted with simulation, we show that this
improvement can be attributed to the strong reduction in the Schottky barrier thickness as a result
of the better gate control of GAA SiNW structure. © 2008 American Institute of Physics.
关DOI: 10.1063/1.2973211兴
Silicide based Schottky-barrier 共SB兲 source/drain 共S/D兲
metal-oxide-semiconductor field-effect transistor 共MOSFET兲
has attracted renewed attention due to its inherent advantage
in device scalability, especially applicable for the sub-10-nm
gate-length devices due to its highly conductive metal S/D,
atomically abrupt junctions as defined by the silicide-silicon
interface achieved by a low-temperature process.1 However,
it is suggested that the S/D SB height 共SBH兲 should be less
than 0.1 eV in order to obtain comparable current drivability
as the conventional p / n-doped S/D MOSFET.2 Moreover,
the reported SBH of the p-channel MOSFETcandidate PtSi3
is ⬃0.2 eV and that of n-channel MOSFETcandidate, such
as ErSi4 or YbSi,5 is ⬃0.27– 0.36 eV. In view of lack of
silicide with sufficiently low SBH at present, it is important
to turn the effort to minimize the SB width to maximize the
tunneling current. Meanwhile, for the channel/gate structure,
the gate-all-around 共GAA兲 Si-nanowire 共SiNW兲 MOSFET
structure is considered as a potential candidate for the endof-the-roadmap devices for its better electrostatic control.6
Therefore, there is great interest to assess the GAA SiNW
channel device integrated with SB S/D contact.
In this letter, we demonstrate enhanced tunneling current
for a GAA SiNW structure with NiSi intentionally encroached through the spacer in a SB MOSFET. For a gate
length of 150–850 nm, the mid-band-gap NiSi SB MOSFETs
with GAA SiNW structure demonstrate excellent device
characteristics in terms of small subthreshold slope 共SS兲 and
large Ion / Ioff ratio. Top-gated 共TG兲 planar silicon-oninsulator 共SOI兲 and GAA SiNW structures are compared, and
the GAA SiNW structure is identified as the dominant factor
for the carrier injection enhancement.
SiNWs were formed by the self-limited oxidation of
the Si-Fin—details can be found elsewhere.7 Then the
⬃5 nm gate oxide was thermally grown, followed by 100
nm low pressure chemical vapor deposition ␣-Si deposition,
implantation with P / 4 ⫻ 1015 cm2 / 25 keV, and activation
a兲
Author to whom correspondence should be addressed. Electronic mail:
elelsj@nus.edu.sg.
0003-6951/2008/93共7兲/073503/3/$23.00
共1050 ° C for 10 s兲. The polycrystalline silicon gate was patterned to have the edges of SiNW exposed for silicidation.
Subsequently, 100 Å SiO2 / 150 Å SiN stack was deposited
and etched to form a thin spacer. Then 1 nm Ti / 9 nm nickel
was sputtered after cleaning of the remaining oxide. Silicide
was formed at both of the exposed SiNW and S/D pads by
rapid thermal annealed 共RTA兲 at 500 ° C for 30 s.
In previous studies, Lu et al.8 reported that NiSi encroaches into a 37.5 nm SiNW after annealing with diffusion
speed of 1.1 Å / s; Appenzeller et al.9 reported that NiSi has
a faster diffusion speed along SiNW with smaller diameter.
Based on these works, we estimate that the NiSi in our
SiNW devices have encroached through the thin spacer
共⬃15 nm兲 after 500 ° C for 30 s RTA process and the final
device structure is shown in Fig. 1共a兲. The SiNW cross section transmission electron microscope 共TEM兲 images of a 4
nm diameter and a 12.5 nm width SiNWs, which are investigated in this work, are shown in Figs. 1共b兲 and 1共c兲.
Figure 2 shows the transfer characteristics of a 4 nm
diameter SiNW, a 12.5 m width SiNW, and a 1 ␮m width
FIG. 1. 共Color online兲 共a兲 The device schematic of the GAA SiNW SB
MOSFET. 共b兲 TEM image of the 4 nm diameter SiNW cross section. 共c兲
TEM image of the 12.5 nm diameter SiNW cross section.
93, 073503-1
© 2008 American Institute of Physics
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073503-2
Peng et al.
FIG. 2. 共Color online兲 The Id-Vg characteristics of the 4 nm and 12.5 nm
diameter GAA SiNW and the 100 nm Si thickness TG SOI NiSi S/D SB
MOSFETs. The inset is the energy band diagram of the NiSi SB MOSFET
at on-state with −1.2 V drain bias.
planar SOI SB MOSFETs on a single wafer without normalization. The gate length of the 4 nm diameter SiNW is 150
nm, and the gate lengths of the 12.5 nm width SiNW and
1 ␮m width planar SOI device are 850 nm. To assist the
discussion, the inset in Fig. 2 describes the energy band diagram of the device at on-state. Due to the large SB of NiSi
for hole, the carrier transport is dominated by the tunneling
current through the source barrier. Results show that the use
of GAA SiNW structure improves the SS, the on-current, as
well as the off-current of SB MOSFETs. The SS of the 4 nm
diameter and 12.5 nm width SiNW is 79 and 86 mV/decade,
respectively, which is much smaller than the 442 mV/decade
of the 1 ␮m width 100 nm body thickness TG planar SOI
device. Since the SB of NiSi for holes is ⬃0.47 eV,10 which
is much larger than kT, carrier transport related to thermionic
emission can be neglected and SS is dominated by the
change in the tunneling probability through the SB with
changing gate bias. Even though SS is influenced by changes
in the depletion charge as well as by trapped charges at the
Si/ SiO2 interface with changing Vg, these factors have been
estimated to have a minor effect on SS in undoped SB
MOSFETs.11 Therefore, SS represents a robust measurement
of the carrier injection in SB MOSFETs, and the carrier injection has been improved in SB MOSFETs based on GAA
SiNW architecture. This improvement is significant in that
the SS of a 12.5 nm SiNW is 86 mV/decade while the theoretical SS of a 12.5 nm Si body TG planar SOI SB MOSFET
is ⬃254 mV/ decade with the same gate oxide thickness.11
The GAA SiNW SB MOSFETs achieved the on-current of
19 ␮A / ␮m from the 12.5 nm width SiNW with 850 nm gate
length, which is much larger than the on-current of
0.33 ␮A / ␮m for the 100 nm body thickness TG planar SOI
device with same gate length. Under the biases of Vg =
−2.3 V and Vds = −1.2 V, the 4 nm diameter, 150 nm gatelength SiNW SB MOSFET with 5 nm gate oxide achieved
smaller SS of 79 mV/decade and large on-current of
207 ␮A / ␮m, which is comparable to those of conventional
p / n-doped S/D MOSFETs.7 This on-current improvement
can also be understood by the carrier injection improvement
in GAA SiNW architecture.
The subthreshold current of SB MOSFET can be modeled using the thermionic emission equation
Appl. Phys. Lett. 93, 073503 共2008兲
FIG. 3. 共Color online兲 The effective SBH of the 4 nm and 12.5 nm diameter
GAA SiNW SB MOSFETs, and TG 100 nm Si body SOI SB MOSFET as
the function of gate bias.
I = wAⴱⴱT2 exp共− q␾eff/KT兲关exp共qV/KT兲 − 1兴,
共1兲
where w is the physical geometry factor, Aⴱⴱ is the effective
Richardson constant, k is the Boltzmann constant, T is temperature, and V is the drain source bias. As the gate bias
increases in subthreshold regime, i.e., Vg ⬍ Vt, the SB becomes thinner due to the gate bias and the contribution of the
tunneling current will become larger while the contribution
from the thermionic current will not change. Hence, the
overall current will become less sensitive to the temperature
change and the effective SBH becomes smaller. Therefore,
effective SBH can be a measure to investigate the tunneling
current in SB MOSFET.
A series of subthreshold characteristics at large drain
bias 共−1.2 V兲 was measured at 260– 360 K, and the experimental effective SBH as a function of gate voltage was obtained and shown in Fig. 3. All three devices 共4 nm and 12.5
nm GAA SiNW SB MOSFETs and TG SOI SB MOSFET兲
show ⬃0.45 eV effective SBH at −1 V gate bias, close to
its real SBH. As the gate bias becomes larger 共negatively兲,
the effective SBH of the 4 nm SiNW decreases faster than
that of the 12.5 nm GAA SiNW SB MOSFET and the TG
SOI SB MOSFET. This faster decrease in the effective SBH
suggests that the carrier injection increases much faster in 4
nm GAA SiNW SB MOSFET than in 12.5 nm GAA SiNW
SB MOSFET and faster in GAA SiNW than in TG SOI
devices due to better gate coupling. The observed negative
barrier height indicates that NiSi/SiNW contact shows
Ohmic-contact-like behavior under high gate bias due to the
dominance of tunneling effects. Comparable barrier heights
between 4 nm and 12.5 nm GAA SiNW SB MOSFETs are
observed in this tunneling-dominant high gate bias condition.
For a quantitative analysis on the impact of gate structure over the tunneling current at the on-state gate bias, the
barrier shape of TG planar SOI and GAA SiNW devices was
numerically solved by MEDICI in cylindrical coordinates with
the parameters set to be the same as the experimental devices
described above. The potential profile along the 2 nm below
the gate oxide surface of TG planar SOI device and GAA
SiNW is plotted at the inset of Fig. 4. It was reported that for
TG planar SOI SB MOSFETs, thinner body thickness could
result in smaller SS;11 therefore, the potential profile of a 4
nm and 12.5 nm TG planar SOI SB MOSFETs was solved
and plotted in the same graph for fair comparison. Results
show that at the on-state gate bias, SiNW with 12.5 nm di-
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073503-3
Appl. Phys. Lett. 93, 073503 共2008兲
Peng et al.
GAA SiNW structure is a means to improve the electrical
characteristics of SB MOSFETs.
In conclusion, we have demonstrated that carrier injection is greatly enhanced in GAA SiNW SB MOSFET due to
the better gate modulation of the SB shape. With the advantage of GAA SiNW structure, the mid-band-gap NiSi SB
MOSFETs achieved a SS of 79 mV/decade from a 4 nm
SiNW device and a SS of 86 mV/decade from a 12.5 nm
device at room temperature.
J.W.P. acknowledges financial support from the Chartered Semiconductor Manufacturing Singapore for his Ph.D.
work at the National University of Singapore.
1
FIG. 4. 共Color online兲 The simulated barrier FWHM 共X1/2兲 as the function
of the Si body thickness of the TG planar SOI device and the GAA SiNW
diameter in NiSi SB MOSFET at on-state. The inset is the potential profile
at 2 nm below the gate oxide surface of the GAA SiNW and TG SOI device
at on-state, where the x axis D represents the distance from the silicide/
channel junction.
ameter has a thinner SB than a 4 nm SOI device. This agrees
with the experimental data, where the 12.5 nm SiNW device
has a SS ⬃86 mV/ decade while the theoretical SS for a 4
nm SOI is larger than 150 mV/decade.11 The barrier full
width at half maximum 共FWHM兲 x1/2 as a function of the
SOI body thickness or SiNW diameter is shown in Fig. 4. It
clearly demonstrates the advantage of GAA SiNW SB MOSFETs in terms of obtaining a thinner SB at a given gate bias.
Given the exponential dependence of tunneling current on
the SB width and the enhanced barrier thinning effect of
GAA SiNW structure, we have demonstrated that the use of
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