類比電路設計(3349) - 2004
Frequency Response of Amplifiers
Ching-Yuan Yang
National Chung-Hsing University
Department of Electrical Engineering
Overview
z Reading
B. Razavi Chapter 6.
z Introduction
In this lecture, we study the response of single-stage and differential
amplifiers in the frequency domain. Following a review of basic concepts, we
analyze the high-frequency behavior of common-source and common-gate
stages and source followers. Next, we deal with cascode and differential
amplifiers. Finally, we consider the effect of active current mirrors on the
frequency response of differential pairs.
Analog-Circuit Design
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Ching-Yuan Yang / EE, NCHU
1
Miller effect
z Application of Miller effect to a floating impedance
That is,
Z

Z1 =
V
1− Y

VX


Z 2 = Z
V

1− X

VY

V X − VY V X
=
 Z
Z1


VY − V X = VY
Z2
 Z
Analog-Circuit Design
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6-2
Association of poles with nodes
z Cascade of amplifiers
‡ The overall transfer function can be written as
A2
1
Vout
A1
(s ) =
⋅
⋅
1 + RSCin s 1 + R1CN s 1 + R2C P s
Vin
We may say “each node in the circuit contributes one pole to the transfer function.”
The pole is determined by the total capacitance seen from each node to ground
multiplied by the total resistance seen at the node to ground.
‡ In general, the transfer function is given as
A
Vout
(s ) = ∏ js = Av ∏ 1 s
j
j
Vin
1+
1+
ωj
ωj
−1
where each pole with one node of the circuit, i.e., ω j = τ j , where τj is the product
of the capacitance and resistance seen at node j to ground.
Analog-Circuit Design
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Common-source stage
z High-frequency model of a CS stage
(Assume λ = 0 and M1 operates in saturation)
‡ At the input node, the total capacitance seen
from X to ground is equal to
Cin = CGS + (1 − Av)CGD,
where Av = − gmRD.
The input pole is ωin =
RS [CGS
(Miller multiplication)
1
+ (1 + gm RD )CGD ]
‡ At the output node, the total capacitance seen to ground is equal to
Cout = CDB + (1 − Av−1)CGD ≈ CDB + CGD
The input pole is
ωout =
1
RD (C DB + CGD )
Analog-Circuit Design
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6-4
Common-source stage (cont’d)
z Model for calculation of output impedance
(If RS is relative large, the effect of RS is neglected.)
‡ The output pole: Z X =
where Ceq =
 C + CGS 1 
1

||  GD
⋅
Ceq s  CGD
gm1 
CGDCGS
CGD + CGS
Thus, the output pole is roughly equal to ωout =
‡ Finally, we surmise that the transfer function is
Analog-Circuit Design
6-5

RD

1
 CGD + CGS 1 
 (Ceq + C DB )

⋅
gm1 
 CGD
Vout
− gm RD
(s ) =
Vin

s 
s 
1 +
1 +

ω
ω

in 
out 
Ching-Yuan Yang / EE, NCHU
3
Common-source stage (cont’d)
z Equivalent circuit of CS stage
V X − Vin

+ V X CGS s + (V X − Vout )CGD s = 0

RS


(V − V )C s + g V + V  1 + C s  = 0
X
GD
m X
out 
DB 
 out

 RD
⇒
zero
(CGD s − gm )RD
Vout
(s ) =
Vin
RS RDξs 2 + [RS (1 + gm RD )CGD + RSCGS + RD (CGD + C DB )]s + 1
poles
where ξ = CGSCGD + CGSCDB + CGDCDB.
Note the transfer function is of second order even through the circuit contains three
capacitors. While the denominator appears rather complicated, it can yield intuitive
expressions for the two poles, ωp1 and ωp2, if we assume |ωp1|<< |ωp2|. Writing the
denominator as
 s
 s

 1
1 
s2
D = 
+ 1
+ 1 =
+ 
+
s + 1
ω
ω
ω
ω
ω
ω
p1 p 2
p2 
 p1
 p 2

 p1
Analog-Circuit Design
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6-6
Common-source stage (cont’d)
If ωp2 is much farther from ωp1 (i.e., |ωp1| << |ωp2|), then
D=
≈
s2
ω p1ω p 2
s2
ω p1ω p 2
 1
1 
+ 
+
s + 1
ω
ω
p
1
p2 

1
+
s +1
ω p1
We obtain
ω p1 =
ω p2 =
1
RS (1 + gm RD )CGD + RSCGS + RD (CGD + C DB )
1
⋅
1
ω p1 RS RD (CGSCGD + CGSC DB + CGDC DB )
If RD(CGD + CDG) is negligible, then
ω p1 ≈
=
RS (1 + gm RD )CGD + RSCGS + RD (CGD + C DB )
RS RD (CGSCGD + CGSCDB + CGDC DB )
1
= ωin
RS [CGS + (1 + gm RD )CGD ]
If CGS >> (1 + gmRD)CGD + RD(CGD + CDB)/RS ,
then ω p 2 ≈
Analog-Circuit Design
1
RSCGS
=
= ωout
RS RD (CGSCGD + CGSC DB ) RD (CGD + C DB )
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4
Common-source stage (cont’d)
z Feedforward path through CGD
The transfer function exhibits a zero given by ωz = +gm/CGD. Located in
the right half plane, the zero arises from direct coupling of the input to the
output through CGD at very high frequency. Note that a zero in the right
half plane introduces stability issues in feedback amplifiers
Analog-Circuit Design
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Common-source stage (cont’d)
z Calculation of the zero in a CS stage
Zero:
Vout
(s )
=0
s = sz
Vin
For a finite Vin, this means that Vout(sz) = 0 and hence the output can
be shorted to ground at the frequency with no current. Therefore, the
currents through CGD and M1 are equal and opposite:
V1CGD sz = gmV1.
That is , sz = +gm/CGD.
Analog-Circuit Design
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Common-source stage (cont’d)
z Input impedance
‡ At high frequency, the effect of the output node must be
taken into account.
I
RD
(I X − gmV X )
+ X = VX
1 + RDC DB s CGD s
⇒ ZX =
1 + RD (CGD + C DB )s
VX
=
I X CGD s (1 + gm RD + RDC DB s )
1
CGS s
‡ At frequencies where |RD(CGD + CDB)s| << 1 and
|RDCDBs| << 1 + gmRD,
1
ZX =
, indicating that the input
(1 + gm RD )CGD s
hence Z in = Z X
impedance is primarily capacitive.
‡ In fact, if CGD is large, it provides a low-impedance path
between the gate and drain of M1, yielding the equivalent
circuit that 1/gm1 and RD appear in parallel with the input.
Analog-Circuit Design
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Source followers
z Source follower
V1CGS s + gmV1 = VoutC L s
Vin = RS [V1CGS s + (V1 + Vout )CGD s ] + V1 + Vout
Transfer function:
Vout
gm + CGS s
(s ) =
Vin
RS (CGSC L + CGSCGD + CGDC L )s 2 + (gm RSCGD + C L + CGS )s + gm
‡ Zero: The transfer function contains a zero in the left half plane. This is because
the signal conducted by CGS at high frequencies adds with the same polarity to the
signal produced by the intrinsic transistor.
‡ Poles: If the two poles of the transfer function are assumed far apart, then the
domain pole is
1
gm
ω p1 ≈
=
gm RSCGD + C L + CGS R C + C L + CGS
S GD
gm
Also, if RS = 0, then ωp1 = gm / (CL + CGS ) .
Analog-Circuit Design
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6
Source followers (cont’d)
z Input impedance
CGD is ignored, we have
VX =

1 
IX
g I  1

+  I X + m X 
CGS s 
CGS s  gmb C L s 
∴
Z in =

1
1
VX
g 
=
+ 1 + m 
I X CGS s 
CGS s  gmb + C L s
‡ At relative low frequencies, gmb >> |CLs| and
1 
g 
1
1
1
1 + m  +
=
+
CGS s 
gmb  gmb  gmb 
gmb

CGS s
 gm + gmb 
indicating that the equivalent input capacitance is equal to CGSgmb / (gm + gmb ).
By Miller approximation: The low-frequency gain Av = gm / (gm + gmb )
Z in ≈
Thus, Ceq = CGS (1 − Av ) = CGSgmb / (gm + gmb ), and Cin ,total = CGD +
‡ At high-frequencies, gmb << |CLs| and Z in ≈
Analog-Circuit Design
1
1
gm
+
+
CGS s C L s CGSC L s 2
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CGS gmb
gm + gmb
Negative resistor
Ching-Yuan Yang / EE, NCHU
Source followers (cont’d)
z Output impedance
CGD is neglected,
V1CGS s + gmV1 = − I X
V1CGS sRS + V1 = −V X
⇒
Z out =
V X RSCGS s + 1
=
IX
gm + CGS s
‡ At low frequencies, Zout ≈ 1/gm.
‡ At very high frequencies, Zout ≈ RS, because CGS shorts the gate and source.
1
> RS
gm
Analog-Circuit Design
1
< RS
gm
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Source followers (cont’d)
z Equivalent output impedance of a source follower
If Z1 = Zout, find R1, R2 and L:
Take R2 = 1/gm, R1 = RS − 1/gm, then
Z out
1
−
=
gm
1
⇒
Z out −
⇒

1 

CGS s  RS −
gm 

gm + CGS s
L=
1
gm
CGS
gm
=
1
RS −
1
gm
+
1
1
1
=
+
CGS s 
1  R1 Ls
 RS −

gm 
gm 

1 
 RS −

gm 

That is, the dependence of L upon RS implies that if a source follower is driven by a
large resistance, then it exhibits substantial inductive behavior.
Analog-Circuit Design
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Common-gate stage
z CG stage at high frequencies




ωin = CS  RS
−1

1
 , where C = C + C
S
GS
SB
gm + gmb 
ωout = ( RDCD )−1, where CD = CDG + CDB
At low frequency, Av =
(gm + gmb )RD
1 + (gm + gmb )RS
(gm + gmb )RD
1
Thus, Vout (s ) = Av ⋅
=
Vin

s 
s  1 + (gm + gmb )RS
1 +
1 +

ωin  ωout 

1


CS
1 +
s (1 + RDC D s )
gm + gmb + RS−1 

An important property of CG stage is that it exhibits no Miller multiplication of
capacitances, potentially achieving a wide band.
z Input impedance Z in ≈
ZL
(gm + gmb )ro
+
1
1
, where Z L = RD
CDs
gm + gmb
Since Zin now depends on ZL, it is difficult to associate a pole with the input node.
Analog-Circuit Design
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Common-gate stage (cont’d)
z CG stage
‡ Transfer function:
(− VoutC L s + V1Cin s )RS
+ Vin = −V1
ro (− VoutC L s − gmV1 ) − V1 = Vout
⇒
Vout
1 + gmro
(s ) =
Vin
roC LCin RS s 2 + [roC L + Cin RS + (1 + gmro )C L RS ]s + 1
The gain at low frequencies is equal to 1 + gmro.
‡ Input impedance:
1
1
1
Z in =
+
⋅
gm + gmb C L s (gm + gmb )ro
As CL or s increases, Zin approaches
1/(gm + gmb ) and hence the input pole
can be defined as
ω p ,in =
1


1
Cin
 RS
gm + gmb 

Analog-Circuit Design
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Cascode stage
z High-frequency model of a cascode stage
Cascode stage = CS stage (input impedance) + CG stage (suppressing the miller
effect)
Gain:
VX
gm1
≈−
VA
gm 2 + gmb
1




g m1
CGD1 
RS CGS1 + 1 +
gm 2 + gmb 



Node A: ω p ,A =
Node X: ω p,X =
gm 2 + gmb2

gm 2 + gmb2 
CGD1 + CDB1 + CSB 2 + CGS 2
1 +
gm1


Node Y: ω p ,Y =
1
RD (C DB 2 + C L + CGD 2 )
In actual design, ωp,X is typically chosen to be farther from the origin than the other
two. This choice plays an important role in the stability of op amps.
Analog-Circuit Design
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Cascode stage (cont’d)
z Simplified model of a cascode stage with a current source
VX = −(VoutCY s + Iin) / (CX s)
ID2 = −gmVGS2 = gm2VX = − gm2 (VoutCY s + Iin) / (CX s)


g
1
− ro 2 (VoutCY s + I in ) m 2 + VoutCY s  − (VoutCY s + I in )
= Vout
C
s
C


X
Xs
Vout
g r +1
1
⇒
= − m2 o2
⋅
C
I in
CXs
1 + (1 + gm 2ro 2 ) Y + CY ro 2s
CX
for gm2ro2 >> 1 and gm2ro2CY /CX >> 1 (i.e., CY > CX ),
g
1
Vout
≈ − m2
C X s CY g + C s
I in
m2
Y
CX
hence
g g
Vout I in Vout
1
=
≈ − m1 m 2
Vin Vin I in
CY C X s gm 2 /C X + s
We can find that the pole at node X is given by gm2 / CX .
Neglecting CGD1 and CY, we have Zout = (1 + gmro2)ZX + ro2, where ZX = ro1||(CX s)−1.
Analog-Circuit Design
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Differential pair
z Half-circuit equivalent
z Differential pair
z Equivalent circuit for common-mode input
Av ,CM

1 

∆gm  RD
C L s 

=−


(gm1 + gm 2 ) ro 3 1  + 1
 CP s 
If the output pole is much farther from the origin than
is the pole at node P, the common-mode rejection of
the circuit degrades considerably at high frequencies.
Analog-Circuit Design
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10
Differential pair (cont’d)
z Effect of high-frequency supply noise in differential pair
‡
If the supply voltage contains high-frequency noise and the circuit exhibits
mismatches, the resulting common-mode distance at node P leads to a differential
noise component at the output.
‡
A trade-off between voltage headroom and CMRR: To minimize the headroom
consumed by M3, its width is maximized, introducing substantial capacitance at the
sources of M1 and M2 and degrading the high-frequency CMRR. The issue
becomes more serious at low supply voltages.
Analog-Circuit Design
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6-20
Differential pair (cont’d)
z Differential pair with current-source loads
Node G is an ac ground.
The output pole is given by ωout =
Analog-Circuit Design
1
(ro1 ro 3 )C L
6-21
, the dominant pole.
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11
Differential pair (cont’d)
z High-frequency behavior of differential pair with active current mirror
Mirror pole: ω p ,E =
gm 3
, where CE denotes the total capacitance at E to ground.
CE
CE: CGS3, CGS4, CDB3, CDB1, and the miller effect of CGD1 and CGD4.
Analog-Circuit Design
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Differential pair (cont’d)
z High-frequency model of differential pair with active current mirror
Thevenin equivalent: VX = gmN roN Vin, RX = 2roN.
Assumed 1/gmP << roP ,
VE = (Vout
1
C E s + gmP
− VX )
1
+ RX
C E s + gmP
(
)
and − gm 4VE − I X = Vout C L s + roP−1 , we have
Vout
gmN roN (2gmP + CE s )
=
Vin
2roP roN CEC L s 2 + [(2roN + roP )C E + roP (1 + 2gmProN )C L ]s + 2gmP (roN + roP )
Since the miller pole is typical quite higher in magnitude than the output pole, we get
ω p1 ≈
(2roN
and ω p 2 ≈
2gmP (roN + roP )
1
≈
(roN roP )C L for 2gmProN >> 1
+ roP )CE + roP (1 + 2gmProN )CL
gmP
.
CE
Analog-Circuit Design
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12
Differential pair (cont’d)
‡ In addition, there is a zero with a
2gmP
in the left half
CE
magnitude of
plane. The appearance of such a zero
is that the circuit consists of a “slow
path” (M1, M3 and M4) in parallel with
a “fast path” (M1 and M2).
‡ Representing the two paths, we have
Vout
A0
A0
=
+
(1 + s /ω p1 )(1 + s /ω p 2 ) 1 + s /ω p1
Vin
=
A0 (2 + s /ω p 2 )
(1 + s /ω p1 )(1 + s /ω p 2 )
That is, the system exhibits a zero at
2ωp2.
Analog-Circuit Design
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Differential pair (cont’d)
z Determine the zero (method)
ID4
IL
For zero frequency, IL = 0 and ID4 = IX.
We have
ID4 = −gmPVE
IX = VE (gmP + CE s)
Thus, −gmPVE = VE (gmP + CE s)
ωz = −
2gmP
CE
Analog-Circuit Design
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