AN-B032
Chrontel
Application Notes
PCB Layout and Design Guide for CH7107B
HDMI To SDTV Converter
1.0 INTRODUCTION
The CH7107B is a low-cost, low-power semiconductor device, which can convert HDMI signals into SDTV outputs
with IIS or SPDIF audio output.
This application note focuses only on the basic PCB layout and design guidelines for CH7107B Converter. Guidelines in
component placement, power supply decoupling, grounding, input /output signal interface are discussed in this document.
The discussion and figures that follow reflect and describe connections based on the 40-pin QFN package of the
CH7107B. Please refer to the CH7107B datasheet for the details of the pin assignments.
2.0 COMPONENT PLACEMENT AND DESIGN CONSIDERATIONS
Components associated with the CH7107B should be placed as close as possible to the respective pins. The following
discussion will describe guidelines on how to connect critical pins, as well as describe the guidelines for the placement
and layout of components associated with these pins.
2.1
Power Supply Decoupling
The optimum power supply decoupling is accomplished by placing a 0.1μF ceramic capacitor to each of the power
supply pins as shown in Figure 1. These capacitors (C1, C2, C4, C6, C7, C9, C10, C12) should be connected as close as
possible to their respective power and ground pins using short and wide traces to minimize lead inductance. Whenever
possible, a physical connecting trace should connect the ground pins of the decoupling capacitors to the CH7107B
ground pins, in addition to ground vias.
2.1.1 Ground Pins
The grounds of the CH7107B should be connected to a common ground plane to provide a low impedance return path
for the supply currents. Whenever possible, each of the CH7107B ground pins should be connected to its respective
decoupling capacitor ground lead directly, then connected to the ground plane through a ground via. Short and wide
traces should be used to minimize the lead inductance. Refer to Table 1 for the Ground pins assignment.
2.1.2 Power Supply Pins
The power supply includes VDDPLL, DVDD, AVCC, AVCC_DAC, and AVDD. Refer to Table 1 for the Power supply
pins assignment. Refer to Figure 1 for Power Supply Decoupling.
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Table 1: Power Supply Pins Assignment of the CH7107B (QFN)
Pin Assignment
# Of Pins
Type
Symbol
Description
1
2, 18
3, 19
11, 38
24, 27
35
Thermal pad
1
2
2
2
2
1
1
Power
Power
GND
Power
Power
Power
Ground
VDDPLL
DVDD
DGND
AVCC
AVCC_DAC
AVDD
GND
PLL Power Supply (1.2V)
Digital supply voltage (1.2V)
Digital Ground
Analog supply voltage (3.3V)
DAC power supply (2.5V~3.3V)
HDMI receiver power supply (1.2V)
Power supply ground
U1
47R 100MHz
DVDD
DGND
AVDD
QFN
VDDPLL
Ther mal Pad
L1
2, 1 8
1
2
C3
3, 1 9
C1
C2
0.1uF 0.1uF
10u F
47R 100MHz
L5
35
1
2
C13
47R 100MHz
C12
0.1uF
1
L2
10u F
1
VCC1_ 2
2
C5
C4
0.1uF
41
10u F
VCC3_ 3
47R 100MHz
AVCC
11, 38
C6
C7 C8
0.1uF 0.1uF10u F
24,27
C9
0.1uF
L3
1
2
47R 100MHz
AVCC_DAC
C10
0.1uF
C11
10u F
L4
1
2
CH7 107B
Figure 1: Power Supply Decoupling and Distribution
Note: All the Ferrite Beads described in this document are recommended to have an impedance of less than 0.05
 at
25MHz & 47 at 100MHz. Please refer to Fair Rite part #2743019447 for details or an equivalent part can be used for the
diagram.
2.2
Internal Reference Pins
• RBIAS pin
This pin sets the DAC current. A 10 KΩ, 1% tolerance resistor should be connected between RBIAS and GND as
shown in Figure 2. A smaller resistance will create more DAC current. This resistor should be placed with short and
wide traces as near as possible to CH7107B.
U1
RBIAS
29
QFN
Ther mal Pad
R1
10K( 1%)
41
CH7 107B
Figure 2: RBIAS pin connection
2
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2.3
AN-B032
General Control Pins
• RB
This pin is the chip reset pin for CH7107B, which is internally pulled-up, places the device in the power on reset
condition when this pin is low. A power-reset switch can be placed on the RB pin on the PCB as a hardware reset for
CH7107B as shown in Figure 3. When the pin is high, the reset function can also be controlled through the serial port.
AVCC
U1
RB
10
R1
1M
SW1
RB
P805 8SS-ND
C1
0.1uF
CH7 107B
Figure 3: RB pin connection
• GPIO [1:0]
These pins are general-purpose input/output. Please refer to reference schematic.
• XI/FIN and XO
CH7107B have capability to accept external crystal with frequencies 27 MHz. The crystal must be placed as close as
possible to the XI and XO pins, with traces connected from point to point, overlaying the ground plane. Since the
crystal generates timing reference for the CH7107B, it is very important that noise should not couple into these input
pins. Traces with fast edge rates should not be routed under or adjacent these pins. In addition, the ground reference
of the external capacitors connected to the crystal pins must be connected very close to the CH7107B.
The crystal load capacitance, CL, is usually specified in the crystal spec from the vendor. As an example to show the
load capacitors Figure 4 gives a reference design for crystal circuit design.
1
U1
XI
22
P1
P2
GND
3
2
53 5-91 18-1 -ND (27 MHz)
1
C1
XO
18 pF
C2
2
23
2
XO
X1
GND
1
4
18 pF
XI
CH7107B
Figure 4: XI, XO pin connection
Reference Crystal Oscillator
CH7107B integrate an oscillator circuit that allows a predefined-frequency crystal to be connected directly.
Alternatively, an externally generated clock source may be supplied to CH7107B. If an external clock source is used,
it should be of CMOS level specifications. The clock should be connected to the XI pin, and the XO pin should be left
open. The external source must exhibit ±20ppm or better frequency accuracy, and have low jitter characteristics.
If a crystal is used, the designer should ensure that the following conditions are met:
The crystal is specified to be predefined-frequency, ±20 ppm fundamental type and in parallel resonance (NOT series
resonance). The crystal should also have a load capacitance equal to its specified value (CL).
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External load capacitors have their ground connection very close to CH7107B (C ext).
To be able to tune, a variable capacitor may be connected from XI to ground.

Note that the XI and XO pins each has approximately 10 PF (Cint) of shunt capacitance internal to the device. To
calculate the proper external load capacitance to be added to the XI and XO pins, the following calculation should be
used:
Cext = (2 x CL) - Cint - 2CS
Where
Cext = external load capacitance required on XI and XO pins.
CL = crystal load capacitance specified by crystal manufacturer.
Cint = capacitance internal to CH7107B (approximately 10-15 pF on each of XI and XO pins).
CS = stray capacitance of the circuit (i.e. routing capacitance on the PCB, associated capacitance of crystal holder
from pin to pin etc.).
In general,
CintXI = CintXO = Cint
CextXI = CextXO = Cext
Such that
CL = (Cint + Cext) / 2 + CS and Cext = 2 (CL - CS) - Cint=2CL - (2CS + Cint)
Therefore CL must be specified greater than Cint /2 + CS in order to select Cext properly.
After CL (crystal load capacitance) is properly selected, care should be taken to make sure the crystal is not operating
in an excessive drive level specified by the crystal manufacturer. Otherwise, the crystal will age quickly and that in
turn will affect the operating frequency of the crystal.
For detail considerations of crystal oscillator design, please refer to AN-06.
2.4
Serial Port Control for CH7107B
• SPC0 and SPD0
SPD0 and SPC0 function as a serial interface where SPD0 is bi-directional data and SPC0 is an input only serial clock.
In the reference design, SPD0 and SPC0 pins are pulled up to +3.3V with 6.8K resistors always as shown in Figure 4.
• DDC_SCL and DDC_SDA
DDC_SCL and DDC_SDA are used to interface with the DDC of HDMI Source or transmitter and the serial PROM.
This DDC pair needs to be pulled up to 5V through 47 KΩ resistors (Refer to Figure 5).
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U1
2
2
VCC3_ 3
R1
VDD5
R2
DDC_SCL
DDC_SDA
4
5
R4
47K
47K
6.8K
1
2
R3
1
QFN
12
13
1
SPC0
SPD0
2
1
6.8K
SPC0
SPD0
DDC_SCL
DDC_SDA
CH7107B
Figure 5: Serial Port Control
2.5
HDMI receiver Pins
The RCP, RCN, RD [2:0] P, RD [2:0] N signals are high frequency differential signals that need to be routed with
special precautions. Since those signals are differential, they must be routed in pairs.
2.5.1
Differential Pair Impedance
To match the external cable impedance and maintain the maximal energy efficiency it is important to meet the
impedance target of 100-Ω ± 10% for the differential data/clock traces. The restriction of this impedance target is to
prevent any loss of signal strengths resulting from a reflection of unwanted signals. The impedance can be acquired
by proper design of trace length, trace width, signal layer thickness, board dielectric, etc. The HDMI differential pairs
should be routed on the top layer directly to the HDMI connector pads if possible.
2.5.2
Trace Routing Length
To prevent from capacitive and impedance loading, trace lengths should be kept as minimal as possible. Vias and
bends should always be minimized; inductive effects may be introduced, causing spikes in the signals. Trace routing
lengths from CH7107B to the HDMI connector are limited to a maximum of 2 inches. The CH7107B should be as
close to the HDMI connector as possible.
2.5.3
Length Matching for Differential Pairs
The HDMI specifies the intra-pair skew and the inter-pair skew as in Table 2. The intra-pair skew is the maximum
allowable time difference on both low-to-high and high-to-low transitions between the true and complement signals.
The inter-pair skew is the maximum allowable time difference on both low-to-high and high-to-low transitions
between any two single-ended data signals that do not constitute a differential pair.
Table 2: Maximum Skews for the HDMI Transmitter
Skew Type
Maximum at Transmitter
Intra-Pair Skew
0.15 Tbit
Inter-Pair Skew
0.20 TPixel
Where Tbit is defined as the reciprocal of Data Transfer Rate and T Pixel is defined as the reciprocal of Clock Rate.
Therefore, TPixel is 10 times Tbit. In other words, the intra-pair length matching is much more stringent than the interpair length matching.
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It is recommended that length matching of both signals of a differential pair be within 5 mils. Length matching should
occur on a segment-by-segment basis. Segments might include the path between vias, resistor pads, capacitor pads, a
pin, an edge-finger pad, or any combinations of them, etc. Length matching from one pair to any other should be
within 100 mils.
Note that lengths should only be counted to the pins or pad edge. Additional etch within the edge-finger pad, for
instance, is electrically considered part of the pad itself.
2.5.4
ESD Protection for HDMI Interface
In order to minimize the hazard of ESD, a set of protection diodes are highly recommended for each HDMI input
(data and clock).
International standard EN 55024:1998 establishes 4kV as the common immunity requirement for contact discharges
in electronic systems. 8kV is also established as the common immunity requirement for air discharges in electronic
systems. International standard EN 61000-4-2:1995 / IEC 1000-4-2:1995 establishes the immunity testing and
measurement techniques.
System level ESD testing to International standard EN 61000-4-2:1995 / IEC 1000-4-2:1995 has confirmed that the
proper implementation of Chrontel recommended diode protection circuitry, using BCD AT1140 diode array devices,
will protect the CH7107B device from HDMI transmitter discharges of greater than 19kV (contact) and 20kV (air).
The AT1140 have a typical capacitance of only 0.50pF between I/O pins. This low capacitance won’t bring too much
bad effect on HDMI eye diagram test.
Figure6 (A) and (B) show the connection of HDMI connectors, including the recommended design of AT1140 diode
array devices. HDMI connector is used to connect the CH7107B HDMI inputs from HDMI transmitter.
U1
RCN
RCP
RD0N
QFN
RD0P
RD1N
RD1P
RD2N
RD2P
HPD
31
RCN
32
RCP
33
RD0N
34
RD0P
36
RD1N
37
RD1P
39
RD2N
40
RD2P
30
HPD
CH7 107B
Figure 6(A): The connection of the HDMI input
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J1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
RD2P
RD2N
RD1P
U2
1
2
3
4
5
RD2P
RD2N
RD1P
RD1N
LINE1 NC
NC LINE2
3
3
LINE3 NC
NC LINE4
10
9
8
7
6
RD1N
RD0P
RD2P
RD2N
RD0N
RCP
RD1P
RD1N
RCN
AT1140
DDC_SCL
DDC_SDA
VCC5_0
HPD
C21
10uF
C20
0.1uF
U4
1
2
3
4
5
RD0P
RD0N
RCP
RCN
LINE1 NC
NC LINE2
3
3
LINE3 NC
NC LINE4
10
9
8
7
6
AT1140
RX2+
RX2_shld
RX2RX1+
RX1_shld
RX1RX0+
RX0_shld
RX0RXC+
RXC_shld
RXCCEC
RESERVED
SCL
SDA
DDC_GND
+5V
HTPLUG
GND
GND
GND
GND
HDMI_A
RD0P
RD0N
VCC5_0
RCP
RCN
D1
SM5817
VCC5_0
2
47K
DDC_SCL 1
AZ5125-01H
1
D2
1
R7
47K
DDC_SDA 1
R6
1
HDMI input
2
R5
1k
HPD
D3
2
D4
2
2
AZ5125-01H
AZ5125-01H
Figure 6(B): The connection of the HDMI inputs－CH7107B HDMI connectors
The following is the description for each HDMI interface pins
• HDMI Link Data Channel (RD [2:0] P and RD [2:0] N)
These pins provide HDMI differential inputs for data channel 0 (blue), data channel 1 (green) and data channel 2 (red). (Refer
to Figure 6 (A)).
• HDMI Link Clock Outputs (RCP and RCN)
These pins provide the HDMI differential clock inputs for HDMI corresponding to data on the RD [2:0] P and RD [2:0] N
inputs (Refer to Figure 6 (A)).
• HPD (HDMI Hot Plug Detect)
This output pin connects to the +5V power through a 1KΩ resistor. Refer to Figure 6 (B) for the design example.
2.6
SDTV Outputs

 CVBS (SDTV) output
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Three on-chip 9-bit high speed DACs provide CVBS (SDTV) output. If the DACs require a double termination, A 75
resistor should be placed between each DAC pin and the ground as shown in Figure 7. (Refer to Figure 7)
33pF
C22
1
2
1
1
1.8uH
2
CN3
AZ5125-01H
1
C29
270pF
D7
100pF
2
2
1
2
2
D6
JACK-RCA-2P
C30
75
C26
270pF
1
2
1.8uH
2
2
1
C27
L10
1
1
2
100pF 1
1
1
DAC0
33pF
2
1
C28
2
2
1.8uH
75
R10
CN2
JACK-RCA-2P
AZ5125-01H
2
1
R9
L9
1
DAC1
C25
2
1
1
2
2
2
100pF 33pF
2
C23
75
C24
270pF
D5
1
1
R8
JACK-RCA-2P
L8
1
1
DAC2
CN1
2
2
AZ5125-01H
Figure 7: CH7107B CVBS (SDTV) output
2.7
Audio Output
• IIS
IIS audio output can be configured through programming CH7107B registers. (Refer to Figure 8)
• SPDIF
For SPDIF output, CH7107B supports audio sample frequencies from 32Khz to 192kHz. (Refer to Figure 8)
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3
2
1
J1
HEADER 3
SPDIF
U1
SD/SPDIF
WS
SCL K
MCLK
6
7
8
I2S DAC
9
CH7 107B
Figure 8: CH7107B IIS or SPDIF Output Pins
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3.0 REFERENCE DESIGN EXAMPLE
The figures below are the reference schematic of CH7107B, which is provided here for design reference only.
Please contact Chrontel Applications group for further support. Table 3 provides the BOM list for the reference
schematic.
3.1
Reference Schematic
V CC5_0
1
1 R1 453 K 2
2
2
E N1 S W1
FB 1 GND1
V IN2 V IN1
GND2 FB 2
S W2 E N2
2.2uH
2
R3
100 K
C3
10u F
2
A VCC_DA C
FB
C4
C5
0.1uF 0.1uF
V CC1_2
C9
10u F
2.2uH
C7
0.1uF
C6
10u F
C8
0.1uF
V CC1_2
L6
L5
1
1
2
C11 R4
22p F
100 K
2
A VDD
FB
DVDD
FB
C13
10u F
C14
0.1uF
C15
10u F
C16
0.1uF
C17
0.1uF
V CC1_2
2
2
11
AT7109
1
1
L4
L3
10
9
8
7
6
1
A VCC
V CC3_3
1
2
1
2
3
4
5
GND
C12
10u F
U1
C2 22p F
V CC1_2
C10
1
4.7uF
L2
L1
1
FB
R2
100 K
V CC5_0
V CC3_3
V CC3_3
C1
4.7uF
L7
1
2
V DDPLL
FB
C18
10u F
C19
0.1uF
Power of CH7107B
A VDD
RD0P
RD0N
RCP
RCN
34
33
32
31
RD0N
RD0P
RCN
RD1N
35
RCP
RD1P
36
A VDD
A VCC
37
RD1P
RD1N
RD2N
38
A VCC
RD2P
39
RBIAS
28
DAC2
27
A VCC_DA C
26
DAC1
25
DAC0
24
A VCC_DA C
23
XO
22
XI
21
NC
15
HPD
29
NC
RB
D1
S M58 17
Rclamp0524 V CC5_0
CH71 07B
R7
47K
47K
33p F C22
1
JACK-RCA-2P
1
1
2
XO
XI
2
1
2
2
Reserved,
according to your
resolution and
application
2
R17
10K 1%
0.1uF
1
2
3
4
5
SD
S CLK
WS
MCLK
C37
0.1uF
CH7107B interface
R18
7.5K
V CC3_3
U5
C38
10u F
S DIN A OUTR
S CLK
VA
LRCK
GND
MCLK A OUTL
VQ
FILT +
10
9
8
7
6
CS43 44
C34
47u F
C35
10u F C36
47u F
1
C33
1
2
3
4
5
6
2
22p F
RB
C39
10u F
Audio
J2
1
2
3
4
5
6
PJ
R20
7.5K
1
1
R15
1M
Y1
1
A VCC
47K
1RBIAS
1
R23
Reserved
C32
27MHz
2
2
A Z512 5-0 1H
2
10K
22p F
C31
2
1
2
1
GPIO1
R21
S PC0
S PD0
D7
100 pF
20K
2
1
1
2 GPIO0
2
2
R19
C29
270 pF
C30
75
CN3
JACK-RCA-2P
2
1
1.8uH
R10
D6
A Z512 5-0 1H
1
2
2
2
2
L10
1
1
DAC0
100 pF1
2
1
33p F C27
C28
1
C26
270 pF
2
2
2
1
2
1.8uH
75
6.8K
JACK-RCA-2P
A Z512 5-0 1H
1
L9
1
R9
6.8K
CN2
2
A Z512 5-0 1H
DAC1
R13
2
1
2
2
100 pF 33p F C25
1
R12
C24
270 pF
D5
C23
75
GPIO5 V
1
1
1.8uH
R8
D4
A Z512 5-0 1H
2
2
DAC2
D3
V CC3_3
CN1
2
L8
1
A Z512 5-0 1H
1
D2
DDC_SDA 1
DDC_SCL 1
1
R6
1
2
2
R5
1k
HPD
HDMI input
XI
30
20
10
RB
MCLK
DGND
9
XO
19
MCLK
S CLK
DGND
8
A VCC_DA C
DVDD
S CLK
WS
18
7
DAC0
DVDD
WS
DAC1
QFN40
S D/SP DIF
NC
6
17
SD
A VCC_DA C
CH7107B
DDC_SDA
NC
5
DDC_SCL
16
V CC5_0
RCP
RCN
DDC_SDA
DAC2
GPIO1
HDMI_A
RD0P
RD0N
4
DGND
A VCC
RCP
RCN
LINE 1 NC
NC LINE 2
3
3
LINE 3 NC
NC LINE 4
10
9
8
7
6
DDC_SCL
RBIAS
GPIO1
U4
1
2
3
4
5
RD0P
RD0N
3
HPD
DVDD
GPIO0
0.1uF
DGND
V DDPLL
14
HPD
C21
10u F
C20
2
GPIO0
GPIO5 V
DVDD
GND
S PD0
DDC_SCL
DDC_SDA
V CC5_0
1
13
Rclamp0524
V DDPLL
S PD0
RCN
RD2P
RD1P
RD1N
U3
41
DGND
RD2N
RD0N
RCP
S PC0
RD1N
RD0P
RD2P
RD2N
12
10
9
8
7
6
11
RD1P
RD1N
LINE 1 NC
NC LINE 2
3
3
LINE 3 NC
NC LINE 4
S PC0
1
2
3
4
5
RD2P
RD2N
RX2+
RX2_ shl d
RX2RX1+
RX1_ shl d
RX1RX0+
RX0_ shl d
RX0RXC+
RXC_shl d
RXCCEC
RES ERVE D
S CL
S DA
DDC_GND
+5V
HTP LUG
GND
GND
GND
GND
A VCC
RD2N
RD1P
U2
40
J1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
RD2P
I2S to L, R CHANNEL
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Reference Board Preliminary BOM
Table 3: CH7107B Reference Design BOM List
Item
Quantity
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
3
2
4
11
11
3
3
3
2
1
6
1
1
5
2
3
1
3
1
3
3
2
2
1
1
2
1
1
2
1
1
1
206-1000-032
Reference
CN1, CN2, CN3
C1, C10
C2, C11, C31, C32
C3, C6, C9, C12, C13, C15, C18, C21, C35, C38, C39
C4, C5, C7, C8, C14, C16, C17, C19, C20, C33, C37
C22, C25, C27
C23, C28, C30
C24, C26, C29
C34, C36
D1
D2, D3, D4, D5, D6, D7
J1
J2
L1, L2, L5, L6, L7
L3, L4
L8, L9, L10
R1
R2, R3, R4
R5
R6, R7, R23
R8, R9, R10
R21
R12, R13
R15
R17
R18, R20
R19
U1
U2, U4
U3
U5
Y1
Rev.0.2
10/11/2014
Part
RCA Jack
4.7uF
22pF
10uF
0.1uF
33pF
100pF
270pF
47uF
SM5817
AZ5125-01H
HDMI_A
PJ
FB
2.2uH
1.8uH
453K
100K
1k
47K
75
10K
6.8K
1M
10K 1%
7.5K
20K
AT7109
Rclamp0524
CH7107B
CS4344
27MHz
11
CHRONTEL
AN-B032
4.0 REVISION HISTORY
Table 3: Revisions
Rev. #
0.1
0.2
12
Date
12/24/2012
10/11/2014
Section
All
All
Description
Initial release
Update for CH7107B
206-1000-032
Rev.0.2
10/11/2014
CHRONTEL
AN-B032
Disclaimer
This document provides technical information for the user. Chrontel reserves the right to make changes at any time
without notice to improve and supply the best possible product and is not responsible and does not assume any
liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of
our products and assume no liability for errors contained in this document. The customer should make sure that they
have the most recent data sheet version. Customers should take appropriate action to ensure their use of the products
does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe
upon or assist others to infringe upon such rights.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT
SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF
Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used
as directed can reasonably expect to result in personal injury or death.
Chrontel
Chrontel International Limited
129 Front Street, 5th floor,
Hamilton, Bermuda HM12
www.chrontel.com
E-mail: sales@chrontel.com


2014 Chrontel - All Rights Reserved.
206-1000-032
Rev.0.2
10/11/2014
13