Cut power consumption for highspeed apps with ADC architectures
By Mark Holdaway
Director of Product Marketing
ADC Products
Xignal Technologies GmbH E-mail: mark.holdaway
@xignal.de
Continuous time delta-sigma
(CTDS) ADC technology shatters the conventional wisdom
that pipeline ADCs are the only
conversion technique available
for high-speed, dynamic range
applications. CTDS technology
offers lower-power operation,
better dynamic performance
and economy of design.
CTD S technology is an
inherently power-efficient
architecture that eliminates
power-hungry sample-and-hold
amplifiers (SHA) and the widebandwidth gain stages essential
to the pipeline ADC concept.
An alias-free Nyquist sample
range is made available by exploiting inherent oversampling
and on-chip digital filtering.
Digital filtering permits tailoring of group delay performance
and the signal transfer function
to specific applications. The
integration of a clock and low
jitter PLL, elimination of antialiasing filters and integration
of input gain stages simplify
input signal path design of
high-resolution data-conversion systems. Switchless design
future-proofs CTDS technol-
ogy through its easy migration
to next-generation CMOS processes, enabling greater speed
and power benefits.
The architecture supports
high-resolution ADC systems
from 10bit to 16bit and beyond with sampling rates up to
100MHz.
Today, most ADC designs
aim to reduce power, particularly in high-speed conversion,
and to minimize the number of
comparators needed. It is broadly assumed that the pipeline
converter provides the highest
sample rates while yielding a
high dynamic range. It is used
as a standard in data-conversion
applications at 10bit and higher
resolutions, and for sample
rates from 5MHz to 100MHz or
more. The architecture reduces
the number of comparators
needed by deploying multiple
low-resolution flash conversion stages cascaded together
to form the pipe. Although the
resolution of each conversion
stage is reduced, the first stage
must be designed with linearity
at least as good as the maximum
resolution of the ADC (12bit
linearity for a 12bit ADC).
Different pipeline implementations exist, but all work by
reducing a multibit conversion
into several lower-resolution
“flashes” that are processed
synchronously. At each stage
Good clock
frequency spectrum
Amplitude
Amplitude
Poor clock
frequency spectrum
in the pipe, a reconstruction of
the previous stage’s quantized
output generated by a DAC is
subtracted from the original
input signal. The residual signal is then amplified before
moving onto the next stage for
finer quantization. In pipeline
conversion, a SHA needs to
acquire the input signal and
hold it to better than 0.5LSB
for the conversion’s duration.
Once all sub-stages have a valid
conversion result, a digital correction block constructs the
final multibit result.
The pipeline ADC is capable
of high dynamic performance.
However, beyond 12bit resolution and as the sampled signal
moves through the pipeline,
transferring the charge associated with a given signal demands high-gain bandwidth to
ensure that stage settling times
fall within the limits set by the
high-frequency signals being
sampled. To maintain linearity, you need to calibrate and
correct for the limits in component matching achievable with
current process technologies;
it is tough to migrate designs
from one process to another. As
operating voltages fall from one
process generation to the next,
the input signal headroom is
compressed. Furthermore,
designing switches with reduced threshold voltages that
Frequency
Frequency
Figure 1: The simplest single-order DS modulator block components are clocked at oversampling frequency.
work well in deep-submicron
processes gets harder.
Remember that pipeline
ADCs form only part of a dataconversion system—in addition,
you need to find a low-jitter
clock source and design input
stages that include anti-alias
filters (AAFs). In AAF design,
steep attenuation characteristics are hard to achieve, tempting you to consider over-sampling the signal of interest.
Over-sampling stretches the
Nyquist zone, lowering demands on filter roll-off. But the
trade-offs are increased system
power and higher processing
speeds demanded of the backend DSP system. With CTDS
conversion, on the other hand,
you don’t need an AAF.
The DS converter uses a
low-resolution quantizer—often only 1bit—clocked at rates
considerably greater than Nyquist demands. The quantizer
creates many low-resolution
samples that—averaged over
time—yield an increased dynamic range. The analog design
is potentially straightforward,
given the linearity of a 1bit (2level) quantizer. In the digital
domain, filtering and decimation—the process of sample-rate
reduction—are needed to reconstruct output data and remove
out-of-band noise.
Figure 1 shows the simplest
single-order DS modulator
block. It comprises a summing
node, integrator and comparator. The comparator’s output
feeds a 1bit DAC that closes
the modulator’s feedback loop.
The modulator compares the
input signal against a voltage
reference level fed back from
the DAC. The comparator is
clocked at the oversampling
frequency. Assuming enough
loop gain, the modulator is a
pulse stream, the density of 1s
or 0s of which is a direct digital
representation of the input signal. The DAC switches between
Vref to close the control loop.
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Figure 2: The quantization error is modeled as Q added to the modulator output.
For the DS ADC, resolution
increases are gained by balancing the over-sampling ratio, DS
modulator order and quantizer
resolution.
Oversampling allows sample
frequency/SNR trade-off and
improves dynamic range. It
gives a 6dB (or 1bit’s worth)
SNR improvement for every
quadrupling of the sample
rate, but dynamic range is
more effectively enhanced by
increasing the resolution of
the quantizer and/or by adding
more integration stages to the
modulator.
Noise shaping is a property
of DS ADCs resulting from the
application of feedback that
extends dynamic range. This
feature is best illustrated by
the mathematical analysis of
the feedback control loop of the
DS modulator as modeled in the
frequency domain (Figure 2).
This model reveals the key
value of the DS modulator. A
closed loop modulator works
as a high-pass filter to quantization noise and as a low-pass
filter to the input signal. The effect of this is a further increase
in dynamic range of 9dB for
each doubling of the sample
rate. Additional integrators
within the loop can increase the
steepness of the noise characteristic, giving further dynamic
range increases.
Figure 3 shows simulation
results for the noise power density for the DS modulator used
in a CTDS ADC. This FFT plot
(with 65k points) of the modulator illustrates the noise power
Figure 3: The quantization noise simulation result hints at the unrealized
dynamic range of a multibit DS modulator used in a CTDS ADC.
density (per FFT bin) relative
to the input signal frequency.
The simulation was driven
with an input signal frequency
of approximately 4.8MHz. The
minimum noise power density
achieved by this modulator is
166dBc/Hz (in the pass band).
Note the characteristic of the
out-of-band noise—i.e. those
frequencies above 20MHz.
Here, noise power levels rise
at the rate of 21dB/octave, a
telltale sign of a third order
modulator. Deployed within
this ADC design is a 16-level
(or 4bit) quantizer that delivers
14bit dynamic range at modest
oversampling rates. Having
established a modulator system
capable of achieving these low
noise levels, the next stage is to
apply filtering to eliminate outof-band noise and decimation
to resample the data.
A digital filter must reject all
signal components within the
serial data stream that occurs
beyond the Nyquist bandwidth.
Simplistically, two frequencyselective filter structures can
be implemented in the digital
domain. They are the finite
and infinite impulse response
filter systems (FIRs and IIRs,
respectively). FIRs are more
widely used because they are
simpler and have a linear phase
response. IIR filter design is
more complicated by virtue
of the feedback included. The
potentially infinite response of
the IIR filter means that there is
always a possibility for the filter
to become unstable. In addition, group delay can become
significant and have adverse
effects on performance in some
systems.
Many degrees of freedom exist for signal transfer function
optimization in a CTDS ADC
by combining different filter
algorithms. However, optimal
solutions may require many
cascaded stages of FIR and
IIR sections. Digital filtering
allows for the data reduction
or downsampling necessary to
provide output data at the originally intended sample rate.
In summary, the basic elements of a DS ADC are oversampling, noise shaping and
digital filtering. Oversampling
spreads quantization noise;
noise shaping reduces the inband noise at the expense of
higher out-of-band noise; and
digital filtering attenuates
out-of-band noise and signal
components.
CT vs. discrete time systems
Most DS converters found in
audio and precision applications exploit switched capacitor, discrete time (DT), loop
filters within the modulator
for noise shaping. Switched
capacitor filters create their
own mixing products, and the
DT DS design is susceptible to
this type of noise aliasing. But
the advantage of DT schemes
is their relatively simple architecture—the way that increased
sample rates produce dynam-
Driver
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LVDS-001
Figure 4: CTDS ADC eliminates complex input filtering.
ic range improvements and
their compatibility with VLSI
CMOS processes. However, the
switched capacitor stages act as
a limit on the maximum signal
bandwidth in the DTDS ADC.
Moving to CT loop filters opens
up new application possibilities
including wide baseband sampling out to several tens of MHz
to under-sampling RF signals in
bandpass designs.
Pipeline and DTDS ADCs
have a common design thread.
In discrete time, sampling an
input signal requires the signal
to be acquired at a precise moment. For an accurate representation of the input signal,
the input stages should settle
to a finite level, dictated by the
accuracy limits of the system
and a time period driven by the
system sample-rate needs. This
settling time eats into the sample time period of the system.
At 40MSps, a conversion system can have a sample period of
just 25ns, setting the maximum
time limits for circuit settling.
At higher resolutions, this
drives the need for very high
gain bandwidth circuits within
the acquisition signal path. In
fact, the converter system must
be designed with circuits that
work with bandwidths many
times that of the input signal.
Thus, discrete time circuits
have to burn excess power to
process a given bandwidth.
The move to a CT strategy
eliminates the settling time
issue altogether, allowing either a lower-power CTDS ADC
implementation vs. discrete
time, at a given sample rate or
a higher sample rate for a given
power budget.
There is no acquisition
phase in CTDS, so a high performance sample-and-hold
stage is eliminated. CT does
not require the high-gain bandwidth stages necessary to force
rapid settling, so power in these
stages is reduced. A little more
power is demanded from the
post modulator digital filter
stages, but the CT loop filter reduces the power demands of the
modulator and eliminates the
additional discrete time-sampling effects seen in the DTDS
ADC. In addition, there is no
down-mixing of noise, eliminating any additional spectral
spurs in the baseband.
With CTDS the filter perfor-
mance is dependent on conventional active filter design rules.
If the sample rate is changed to
match input signal bandwidth,
the CT filter must be tuned.
Thus, a potential limit on the
CTDS implementation is how
to ensure that a wide range of
sample rates can be supported
from a single product platform.
This problem is solved using
adaptive filter combined with
calibration techniques.
For high-resolution implementations, the loop filter must
have significant gain to obtain
high linearity. This is provided
using multipath and cascaded
gain stages operating at 1.2V
and delivering 80dB of gain for
a 30MHz bandwidth. This has
been clearly demonstrated as
possible in 0.1µm CMOS.
The first product to implement CTDS conversion offers
a low-power alternative to the
pipeline converter. It is said to
be a complete data-conversion
system, designed to operate
FPGA clock manager
CLKO
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[7:0]
Figure 5: For a 10MHz bandwidth signal, at 12bit resolution, clock jitter must be less than 3ps rms.
seamlessly over a wide range
of sample rates without highperformance, expensive and
external components.
Simplify application
Xignal’s implementation of a
CTDS quantizer and digital filtering supports resolutions up to
and beyond 14bits. The generalpurpose ADC core is combined
with several features designed
to simplify its application. It
consumes less power—60mW
for the ADC core, leading to an
energy figure of merit (FOM) of
0.79pJ/conversion.
The CTDS ADC architecture eliminates complex input
filtering due to the effect of
oversampling in combination
with digital filtering (Figure
4). With filter performance
characteristics set in the digital
domain, a very high level of
pass-band flatness and steep
roll-off is possible. The current
digital filter allows 90 percent
of the first Nyquist zone to be
exploited whilst offering a passband ripple of only ±0.0002dB
and 80dB stop-band attenuation. Group delay for this filter
is only 0.33 samples.
Xignal uses a third-order
CTDS modulator, designed
around a 4bit quantizer stage
achieving dynamic range at an
oversampling rate of 16. The
differential input signal path
has a bandwidth of 30MHz. The
internal sample clock operates
at 640MHz. Today’s technology allows for increased sample
rates to 80MSps (at 14bits)
with an over-sampling clock
rate of approximately 1.3GHz.
Through self-adaptive tunable
loop filter components, the
ADC is optimized for sample
rates of 20MSps to 40MSps.
Xignal integrates a clock
source on-chip with the ADC
core. The ADC just needs a lowcost crystal, parallel connected
to its clock input. The clock
is connected to a high-performance PLL block that uses an
on-chip LC-tuned circuit to create a high-Q resonator, creating
a precise clock source.
Alternatively, an external
clock can drive the ADC. Highfrequency jitter from an external distributed clock tree will
be removed, provided its jitter
falls outside the 350kHz PLL
bandwidth of the jitter cleaner
circuit. However, an advantage
of the on-chip precision clock is
that it can be routed to external
circuits. Furthermore, it can
be used as a system reference
clock for other time-critical
parts of the system, potentially
eliminating the extra cost of a
low-jitter source, saving both
design effort and board area.
A low-jitter clock is a crucial
function in all high-speed, highresolution data-conversion systems. Phase accuracy of the
sample clock has a major impact
on measured performance. In
fact, decibels of dynamic range
are easily sacrificed by picoseconds of phase jitter. Figure 5
shows the mathematical derivation of maximal clock jitter
for a given resolution and input
signal frequency. For a 10MHz
bandwidth signal, at 12bit resolution, clock jitter must be less
than 3ps rms. For 14bits, this
demand drops to 1ps rms.
The initial results are encouraging and better than the
FOMs achieved by contemporary pipeline ADC designs.
Furthermore, the architecture
has the ability to scale with
CMOS process developments
and to yield further increases
in efficiency and speed. This is
important as pipeline design
will become more challenging
within the restrictive confines
of the CMOS process roadmap
with its sub-bandgap threshold
requirements.
The ongoing development at
Xignal shows that the ADC core
can be successfully combined
with input signal path components to provide a high level of
integration. The digital processing (filtering and decimation)
provided also shows that in the
future, it is possible for system designers to tailor-transfer
functions for a given application. Finally, the elimination
of external anti-alias networks
and the inclusion of a high-performance PLL significantly ease
the design of a high-resolution,
high-speed sampling system.
The quantization noise
simulation result hints at the
unrealized dynamic range of a
multibit DS modulator. There is
some room for further dynamic
range improvements with careful design, particularly with
thermal noise—the dominant
noise source in this design
today. Although complex, the
deployed CTDS ADC has been
implemented in such a way to
be transparent to the user.