Copyright © 2005 UMC Corporation and Ansoft Corporation
1
Table of Contents
Table of Contents.........................................................................................................................................................2
Executive Summary .....................................................................................................................................................3
RFIC Design Challenge ...............................................................................................................................................3
Design Flow Solution ..................................................................................................................................................6
Applications ...............................................................................................................................................................15
UMC – Ansoft Collaboration.....................................................................................................................................15
UMC 0.13um RFCMOS Solution..........................................................................................................................15
Ansoft EDA Technology .......................................................................................................................................16
Benefit........................................................................................................................................................................16
Conclusion .................................................................................................................................................................16
About the Companies.................................................................................................................................................17
UMC ......................................................................................................................................................................17
Ansoft ....................................................................................................................................................................17
RFIC Design and Verification
2
Executive Summary
Applications such as WLAN, Bluetooth, 3G, Gigabit Ethernet, and portable communications devices are fueling
the demand for advanced Mixed Signal/RFCMOS semiconductors. Requirements for lower cost, lighter weight
and longer battery life drive greater functional integration leading to sophisticated single-chip solutions. Modern
portable consumer electronic systems, for example, combine high digital content for advanced user experience with
high analog and radio frequency (RF) resources for connectivity to remote systems and services. This results in
complex System on Chip (SoC) solutions that combine mixed-signal circuits, embedded high-performance analog
and sensitive RF front-end blocks together with complex digital circuitry on the same chip.
UMC delivers advanced SoC solutions that address the needs of communications and networking industries for
high-performance and low power digital and analog circuits. UMC has paid particular attention to the sensitive
analog and RF circuits that are critical to the success of an IC design project. Addressing the analog section of the
system with rigor can eliminate costly re-spins. To ensure high yield, the analog blocks must be as robust as the
digital blocks and must take into account analog nonlinearities, parametric yield and process variations.
Complexities in achieving this robustness force design organizations to search for new technologies and methods to
deliver solutions that are rigorous and reliable. Of critical importance is the design flow and modeling for custom
integrated circuits that include RF circuits on the analog front-end, analog and mixed-signal circuits at baseband,
and digital signal processing on the back-end. UMC and Ansoft have teamed to develop a design solution for
complex systems that include custom RF and analog circuits. UMC’s advanced RFCMOS process combined with
electronic design automation (EDA) tools from Ansoft and other established vendors provide the platform upon
which advanced RFICs can be developed. Advanced simulation technologies provided by Ansoft’s Nexxim®
simulator and HFSS® 3D electromagnetic extractor enhance the Cadence RFIC design flow.
This joint effort leverages UMC’s production-proven 0.13um RFCMOS process with advanced circuit simulation
and electromagnetic extraction tools from Ansoft. This document describes RF and analog design and verification
in the RFIC design flow. Circuits from an on-going project to develop an ultrawideband (UWB) multi-band
orthogonal frequency division multiplexed (MB-OFDM) radio will be used as the vehicle to demonstrate the
process technology, EDA tools and design flow.
RFIC Design Challenge
RFIC designers face several significant challenges. Large RFICs, such as wireless transceivers, contain analog and
digital components including voltage-controlled oscillators (VCOs), phase locked loops (PLLs), mixers, filters,
amplifiers, automatic gain control (AGC) loops, digital-to-analog converters (DACs), and analog-to-digital
converters (ADCs). Characterizing these elements requires detailed simulation in the time- and frequencydomains. In addition, simulating multiple radio elements cascaded to form a complete transceiver chain often
exceeds the limits of traditional EDA tools. Too often designers are forced to compromise on the breadth of their
verification simulations due to long simulation run time and short design schedules. New technology is needed to
provide the accuracy and robust convergence required for sensitive analog blocks and the capacity and speed
necessary for handling the large numbers of transistors and parasitic elements typical in mixed-signal SoC designs.
Modern radio systems operate at GHz frequencies under advanced signaling methods like orthogonal frequency
division multiplexing (OFDM) and fast frequency hopping to maximize link reliability and minimize interference
with other services. Circuits that perform at high frequency with high switching speed are extremely sensitive to
active and passive device models, distributed layout parasitics, substrate coupling effects, inter-stage impedances,
IC packaging, and power supply noise. Providing new methods that accurately characterize layout and other
parasitic effects is more critical than ever to first pass success.
RFIC design requires specialized and unique analysis techniques specific to RF design. Nonlinear effects of
harmonic distortion, gain compression, oscillator phase noise, and mixer noise figure are most often simulated and
reported in the frequency domain. Switching behavior, circuit initial start-up, and transceiver response to
instantaneous events such as frequency hopping are best examined in the time domain. Technology to allow
RFIC Design and Verification
3
simulation in the time- and frequency-domains with consistent results between is required for modern RF circuit
simulation and verification.
Integrated circuits are eventually assembled into an IC package. In many cases, RF circuits are added to large
SoCs in a single-chip solution. Another approach is to integrate RF circuitry by using system-in-package (SiP)
techniques leading to similar verification challenges as found in SoC solutions. The most comprehensive system
approach allows for a multi-die package that may include a digital SoC together with wireless, sensor and actuator
die as necessary.
New technologies for circuit simulation capacity and speed that add value to a ready established flow can be
integrated into existing design solutions. For analog and RF circuits, the most popular flow is the Cadence®
Virtuoso® Analog Design Environment (ADE). Ansoft’s products for advanced circuit and electromagnetic
simulation are linked into that environment. Many RFICs contain the analog-to-digital converter (ADC), digitalto-analog converter (DAC), phase-lock loop (PLL), and possibly a digital synthesizer. These functions are
generally created through a different environment and integrated on-chip. Verification of these blocks is still
performed using SPICE-level circuit simulators for critical accuracy. The addition of Nexxim® new technology
for high-performance circuit simulation combined with the reliability of the High-Frequency Structure Simulator
(HFSS®) component and layout electromagnetic extraction into the design flow creates new opportunities for SoC
designers to achieve first-pass silicon success.
RFIC Design and Verification
4
System Design and
Behavioral Modeling
Testbench Development
Circuit
Specifications
Circuit Design w/
Idealized Interconnect
Time and
Frequency
Domain
Circuit
Simulation
Layout
Foundry
Design Kit
Design/Extraction of
Critical On-Chip Passives
Design/Extraction of
Package Parasitics
Electromagnetic
Layout Extraction
Verification in
System Testbench
Tapeout or
Chip Integration
Figure 1. RFIC Design and Verification Flow.
RFIC Design and Verification
5
Design Flow
Design Tools
System Design and
Behavioral Modeling
Ansoft Designer
Matlab
HDL
Spreadsheet
Schematic Entry and
Design Environment
Cadence Virtuoso Schematic
Time and Frequency
Domain Circuit Simulation
Layout
Electromagnetic
Extraction
Ansoft Nexxim
Cadence Spectre
Cadence Ultra-sim
Cadence Virtuoso-XL
Cadence Encounter P&R
Ansoft HFSS
Ansoft Q3D
Ansoft TPA
Parasitic Extraction,
DRC, and LVS
Cadence Assura DRC/LVS
Mentor Calibre DRC/LVS
Verification in
System Bench
Ansoft Nexxim + Designer
Figure 2. Design and Verification Tools used in the RFIC Design Solution.
Design Flow Solution
Figure 1 is a flow chart depicting the typical RFIC flow and Figure 2 is a functional chart that indicates tools used
in that flow. The process begins with system design and behavioral modeling test bench development. Common
modeling approaches are to use Matlab®, a high-level language like C, a hardware description language (HDL)
like Verilog-A or VHDL-AMS, or dedicated system simulators like the one found in Ansoft Designer®. These
tools are effective in creating a behavioral simulation of a system that may contain RF, analog, and digital sections.
Figure 3 depicts a behavioral block diagram of a wireless system with blocks displaying the baseband digital signal
processing (DSP), data converters, radio transmitter and receiver, and the radio channel. Behavioral models for
each of these blocks can be created using the aforementioned tools. The level of detail in each behavioral model
depends upon the requirements of the analysis and the maturity of the project. By modeling the full chip within a
top-level test bench, verification of critical system performance in terms of constellation plots and metrics such as
error-vector magnitude (EVM) or bit-error rate (BER) can be performed. Circuit block specifications are
developed to define such metrics as gain, return loss, noise figure, sensitivity, effective number of bits (ENOB) for
the data converters, etc.
This behavioral test bench ultimately serves as the framework for more complex mixed level simulations, where
blocks can be inserted at the transistor level and verified in a system context. This allows designers to make a
tradeoff between analysis rigor and simulation speed by inserting critical blocks at the transistor level and wellcharacterized blocks at the behavioral level. Continuous verification of system performance as blocks mature can
be performed to track system evolution during the design process. Problems can be detected and mitigated early in
the design cycle allowing corrective measures to be performed. Block design by disparate design teams can occur
concurrently and assembled into the top-level simulation as they become available.
RFIC Design and Verification
6
S xx( f )
RF Transmitter / Receiver
CCOD802153A
HDR802153A
PUNCT802153A
INT802153A
3
MPSKMOD802153a SPR802153A ADDPILOT802153A
01
10
P HY
100
MA C
00
PAY802153A
SCR802153A
CCOD802153A
PUNCT802153A
INT802153A
3
DATA
x
x*
PRE
IFFT
U20
DAC1
CYCLIC_PREFIX
10
PAY
11
00
10
I
Q
x
x*
x
x*
FC=1GHz
IFFT
OUT
LO
U36
Antenna
FL=1GHz
FU=2GHz
U22
Synthesizer1
1
2
TFCOD802153A
D IV
FL=1GHz
FU=2GHz
0
N0/ 2
50
TX802153A
BSRC
RANDOM
U24
Synthesizer1
P RE
HDR
C OD INT MOD IFFT
SP
P A Y S C R C OD INT MOD IFFT
TFCOD802153A
S xx( f )
0
CDMUX
10
3
DPUNCT802153A
10 0
10
DINT802153A
11
01
x
x* x*
x x
DSPR802153A REMPILOT802153A
MPSKDEM802153a
1
2
LO
OUT IN
AGC
ADC
CDMUX
FFT
AMP
FL=1GHz
FU=2GHz
MIXER3P
FC=1GHz
CYCLIC_REMOVE
S xx( f )
ptn
10
00
Q
I
AVGPP
VDEC
SCR802153A
U37
Antenna
50
U25
ADC
SINK
SINK
Indoor
D IV
BERP
CAWGN
01
10
Channel
MIXER3P
IN
DAC
HDR
MPSKMOD802153a SPR802153A ADDPILOT802153A
10
100
x
x*
SP
BSRC
RANDOM
11
I
Q
10
S CR
Sxx ( f )
SP
PRE802153A
AVGPP
Baseband Transmitter / Receiver
Figure 3. Full transceiver behavioral model of UWB radio for early system-level trade-off studies. Circuit
includes all baseband DSP and signal conditioning circuits, radio circuits, and a multipath fading radio
channel model.
The behavioral modeling tool used for the UWB project is Ansoft Designer. It provides very comprehensive
models for radio blocks such as mixers, filters, amplifiers, radio channel models, and antennas. Ansoft Designer
also provides DSP and mixed-signal blocks often encountered in modern radio systems such as fast Fourier
transforms (FFTs), data converters, symbol mappers, random bit sources, and detectors. A very significant
advantage of this solution is that it can co-simulate with Matlab models and allows customization of user-defined
blocks using standard C programming. For this RFIC project, Ansoft and UMC created a custom library of
behavioral components for the UWB baseband signal processing including data scrambling, convolutional
encoding, puncturing, symbol mapping and OFDM symbol generation. These models represent a Multiband
OFDM Alliance1 (MBOA)-compliant system library that is available to UMC and Ansoft customers.
The next step in the flow is circuit design using idealized interconnect and foundry design kit device models.
Circuits at this level are used for early design trades to select designs that meet performance specifications. Circuit
simulation is performed in the time- and frequency-domains to characterize critical performance metrics. The
choice of domain depends on the circuit, type of simulation, and desired output. The Nexxim circuit simulator
performs time-domain simulation with an optimized transient simulation engine; it performs frequency-domain
simulation using a high-performance harmonic balance engine. UMC has been a leader in the adoption of this new
and powerful technology. The Nexxim simulator is fully integrated into the Cadence RFIC design flow. Figure 4
illustrates the tight integration directly within the menu structure of Cadence ADE.
The value of transient plus harmonic balance in a single simulator is made apparent by time- and frequency-domain
simulations on RF circuits. Figure 5 is the schematic for the UWB receiver analog baseband including the
baseband filter and variable gain amplifier for automatic gain control (AGC). Peripheral elements surrounding the
core circuit represent the circuit test bench that provides in-phase (I) and quadrature (Q) inputs and outputs and
various control and power supply voltages. This circuit is designed using the UMC 0.13um Foundry Design Kit
(FDK) models and simulations were performed using Ansoft’s Nexxim circuit simulator. Figure 6 provides typical
frequency-domain results for this circuit including swept frequency results using linear network analysis, harmonic
distortion results using Nexxim harmonic balance analysis, and gain compression. Figure 7 provides typical timedomain results for the same circuit including the input waveform for a complex OFDM input and the output I and
Q channel responses for a single UWB frame using Nexxim transient simulation. A single process design kit and
associated environment enables a smooth determination and selection of the simulation algorithm desired. Results
are presented through a display appropriate for the selected simulation type. As circuits are completed at block
level, they are verified within the top-level context with behavioral stimulus and descriptions for the surrounding
chip.
1
The Multiband OFDM Alliance is a special interest group organized to develop, publish, and promote the best
overall solution for global UWB standardization. See http://www.multibandofdm.org/ for more information.
RFIC Design and Verification
7
Cadence ADE
Tool Select
Launch Nexxim
Figure 4. Ansoft’s Nexxim circuit simulator is fully integrated into Cadence ADE.
0
V1772
0
0
V1775
IOutn
QOutp
Vctrl_1p
Vct rl_1n
E1752
Qoutn
Vct rl_2p
Vct rl_2n
V1777
1e- 012
test
V
0
BBqn
E1782
1e- 012
BBIn
BBqp
10k
coremos_corner =tt
iomos_corner =tt
cirspl_case=typ
sqskspl_case=typ
mimcap_case=typ
varmis12_case=typ
varmis33_case=typ
vardio_case=typ
npn_vn_case=ty p
npn_vs_case=ty p
pnp_vn_case=ty p
rnhr_case=typ
rnnpo_case=t yp
rnppo_case=t yp
diodn_esd_case=ty p
diop_esd_case=typ
pad_rf_case=typ
PD
IOutp
AGND
V
mos_corner =tt
res_case=res_typ
UMC0. 13um1.2V/3. 3V
Twin, Tri pple W
e l RFCMOS
AVDD
BBIp
GNDd ump
0
V
E1750
10k
LPF _Vtun
UMC0. 13um1.2V/3. 3V
T wn
i , Tripp e
l Wel lMixed_Mode
U1
BB1
R17 45
V1776
R17 47
mos_corner =tt
V
V
E1781
C1 746
V1769
UMC0. 13um1.2V/3. 3V
T wn
i , Tripp e
l Wel lMixed_Mode
C1 748
V
0
0
V
0
E1760
E1761
E1765
V
E1766
V1957
V1758
V1759
V1763
V1764
0
0
0
-0.145(min gain)<=Vctrl1<=0.2(max gain)
V1762
0
-0.11(min gain)<=Vctrl2<=0.2(max gain)
V1767
0
Figure 5. Analog baseband of UWB receiver including baseband filter and variable gain AGC amplifier.
RFIC Design and Verification
8
(a)
(b)
(c)
Figure 6. Example frequency-domain results for the baseband circuit in Figure 5. (a) Swept frequency
response for various gain states, (b) Harmonic distortion as reported by harmonic balance simulation, and
(c) Gain compression plot as computed by harmonic balance.
(a)
(b)
Figure 7. Example time-domain results for the baseband circuit in Figure 5. (a) OFDM digitally modulated
input waveform using PWL source, (b) I and Q output as predicted by Nexxim.
RFIC Design and Verification
9
To improve the fidelity of the simulation, on-chip passive elements like spiral inductors and metal-oxide-metal
(MoM) capacitors can be synthesized, extracted, and added to the circuit simulations. The foundry design kit
passive models are highly accurate so long as design rules are followed and parameter ranges are not exceeded.
UMC has provided a novel mechanism for device topologies outside those provided in standard design kits to
enhance designer’s innovation. UMC’s Electromagnetic Design Methodology (EMDM) uses full-wave 3D
simulation to create models for the on-chip passives with accuracy traceable to the foundry process. For spiral
inductors, the inductance and quality factor (Q) is computed by Ansoft’s HFSS using advanced full-wave finite
element simulation.
To simplify the process of using full 3D EM for circuit designers, UMC and Ansoft collaborated on the EMDM
project. Ansoft created a tool called the Component Wizard for UMC to develop parameterized models that match
their foundry design process. Figure 8 depicts the Component Wizard and the process used by UMC to create
ready-to-solve parametric HFSS projects. The wizard uses the Cadence layout P-cell and layer stackup technology
file to create HFSS projects. A library of fully parameterized spiral inductor geometries in HFSS has been
produced using this method. The library is available to UMC customers as a foundry-validated EMDM design kit.
The kit contains fully parameterized HFSS projects for spiral geometries including circular, rectangular, octagonal,
and symmetric inductors. A methodology to back annotate the optimized design to common layout tools was also
provided. Figure 9 provides plots that compare HFSS simulated results with measured results for two circular
spiral geometries. As can be seen in the figures, agreement is excellent for both inductance and quality factor.
Component Wizard
P-Cell
Parametric
HFSS Project
(UserDefined
Primitive)
Stackup
Compression
M3
M2
2
M1
SiO2
Si
ε
Stackup Tech File
Figure 8. Component Wizard reads UMC process technology file and P-cells to create ready-to-solve
parametric HFSS projects.
RFIC Design and Verification
10
IND605 comparison
14
10
12
7
10
4
8
1
6
-2
4
20
16
12
12
IND605_m_Q
IND605_5_Q
9
8
6
4
3
0
0
-4
-3
-6
-9
-5
IND602_m_L
IND602_S_L
2
-8
IND602_m_Q
IND602_S_Q
0
-8
-11
-2
-12
-14
-4
-16
0
2
4
6
8
10
12
14
Frequency[GHz]
(a)
16
18
20
15
IND605_m_L
IND605_S_L
Quality Factor
16
13
Inductance[nH]
16
Quality Factor
Inductance[nH]
IND602 real-comparison
-12
0
2
4
6
8
10
12
14
16
18
20
Frequency[GHz]
(b)
Figure 9. Comparison of HFSS simulated vs. measured inductance and Q for circular spiral inductor. (a)
150um outer diameter, (b) 300um outer diameter.
The next step in the process is to perform circuit layout. Automated design-rule-driven and connectivity-driven
layout may be used judiciously, especially to take advantage of direct ties to schematic and design-rule-checking
(DRC). Critical analog blocks, however, are generally manually routed using a full custom approach to ensure that
highly sensitive analog circuitry meet specifications.
As layouts are completed, electromagnetic simulation is used to provide highly accurate models for interaction of
passive components and interconnect. For example, several spiral inductors may be selected as highly critical and
a target for EM simulation in a single project. These EM simulation models can replace the models that were
created earlier in the design process, and can be mixed and matched with the existing models. This gives the
designer full control over the passive modeling process, and again enables the ability to tradeoff runtime vs.
accuracy.
An emerging capability for extremely sensitive blocks like VCOs allows the extraction of the full layout at the
block level using full-wave 3D electromagnetic simulation. The performance of simulation tools like HFSS and
computer platforms continues to improve and hence it is now possible to use 3D simulation on critical radio blocks.
The advantage is that this rigorous method simulates all high-frequency layout effects including on-chip inductors,
interconnect, coupling between on-chip passives and to other interconnect structures, and substrate coupling. No
assumptions are made regarding parasitics or coupling. Of course the net-based RLC extractors have their place in
the RFIC flow, but there is always designer input to manage which parasitic effects to include. It is not always
clear which parasitic effects are most critical in the circuit context. Rigorous EM extraction of the entire block
removes any doubt in the process.
Figure 10 depicts an HFSS simulation project for the layout of an entire VCO block. All active elements and MoM
capacitors have been removed and their terminals were replaced with lumped ports. The HFSS project contains
142 ports and was solved on a dual processor PC in just over nine hours. Simulation required 2.15 GBytes of
RAM. Although the simulation is lengthy, it is still reasonable to run overnight and the results for this case were
well worth the effort. Figure 11 shows plots of the VCO negative resistance generator S11 magnitude (blue) and
phase (red). S11 must be above the green dashed line (S11 > 0dB) in order for the device to oscillate. It is shown
here that when extracted parasitics computed by full-block extraction are included the device no longer oscillates.
Such a failure would not have been discovered until after tapeout, fabrication, and test. This level of layout
extraction and verification can be very valuable to design organizations to ensure first silicon success.
RFIC Design and Verification
11
Figure 10. Critical VCO circuit layout geometry as simulated in HFSS.
(a)
(b)
Figure 11. Plots of VCO negative resistance generator S11 magnitude (blue) and phase (red). S11 must be
above the green dashed line in order for the device to oscillate. (a) Before full-block layout extraction shows
oscillation at 4.4 GHz. (b) After full-block layout shows that device no longer oscillates.
The next critical step is to extract package parasitics and add those effects to the circuit simulations. At RF
frequencies even the smallest amount of lead inductance can have a significant effect on circuit performance.
Figure 12 contains images of an HFSS model for a quad flat no-lead (QFN) integrated circuit package. Simulations
were performed to extract a full S-parameter matrix for all leads. From these simulations we can compute lead
inductance for all conductors. Figure 13 depicts the schematic for the UWB radio receiver including the T/R
switch, variable gain LNA, balun, I/Q demodulator, and baseband filtering/AGC. This circuit was used to examine
the effects of package parasitics on circuit performance. Figure 14 is a plot of the small signal performance of the
circuit shown in Figure 13 with and without ground and supply lead inductance. The blue trace is the baseline with
no ground or supply inductance included. As can be seen from this plot, the S11 response looking into the LNA is
less than 0dB across the frequency range and hence the circuit is stable. The red trace is a plot of S11 for the LNA
including ground and supply package lead inductance for the T/R switch. Again, the circuit remains stable. The
green trace is a plot of S11 looking into the LNA when ground and supply package lead inductance is included for
RFIC Design and Verification
12
the T/R switch and LNA. These results show that the ground inductance, common to the first and second stages of
the LNA, cause the circuit to oscillate. In the same simulation it was observed that the small signal gain of the
LNA decreased by ~15dB. Adjustments to the design of the various blocks were performed to stabilize the circuit.
Port2
Port4
Port1
Die
Port3
Exposed Die
Paddle
Gold Wire
Cu Leadframe
Vias
Ports
(a)
(b)
Figure 12. Quad flat no-lead (QFN) IC package model. (a) Model in HFSS. (b) Finite element mesh.
V
V
V
E1657
0
Ibias_mxi
Ibias_mxq
0
RxMx_VDD
LNA_VDD
LNA_Ibias
TRsw_VDD1
V
E1648
TRsw_VDD2
BB_AVDD
LPF_Tun
Balun_VDD
AVDD1
AVDD2
V
U37
TRswitch
Rx
Ibias
RFin
ANT
AVDD
LNA
U166
RxMx
U53
ActBal
Ibias_mxi
Ibias_mxq
U85
BB
A V DD
LPF_Vtun
AVDD
BB_Ibias
PD
IFi
BBIp
IOutp
IFin
BBIn
IOutn
IFq
BBqp
IFqn
BBqn
AVDD
VoutI
RF
RFout
RFout
RFin
VoutIn
RFN
LNA_PD
RxTx
PD
AGND
PD
RFoutn
AGND
GC AGND1
RxMx_PD
PD
LOi
Tx
Vctrl_1n
Vctrl_2p
QOutp
VoutQ
Qoutn
VoutQn
Vctrl_2n
LOi
LNA_GC
RxTx
Vctrl_1p
A GN D
Balun_GND
LNA_GND
LNA_GND1
TRsw_GND1
LOib LOq LOqb
A GND
Tx
A GN D 1 A GN D 2 AGN D 3
GN D dum p
ANT
V
U2
LNA
Balun_PD
Vctrl_1p
LOib
Vctrl_1n
Vctrl_2p
Vctrl_2n
RxMx_GND
TRsw_GND2
LOq
TRsw_GND3
BB_AGND
LOqb
0
E1664
V
Figure 13. UWB receiver schematic including T/R switch, variable gain LNA, balun, I/Q demodulator, and
baseband filtering/AGC.
RFIC Design and Verification
13
Figure 14. Input return loss looking into the LNA of the circuit shown in Figure 13 with and without ground
and supply lead inductance. Blue trace is the baseline with no ground or supply inductance included. Red
trace includes ground and supply package lead inductance for the T/R switch. Green trace includes ground
and supply package lead inductance for the T/R switch and LNA causing the circuit to become unstable.
The final step prior to tape-out or additional chip integration is to perform full-chip verification in a system
(behavioral) test bench. The verification can include transistor-level circuits for multiple circuit blocks with
incorporation of all extracted parasitics. The system should allow designers to select the particular level of
abstraction for individual circuit blocks in order to make reasonable trades between accuracy and simulation run
time. Figure 15 depicts a circuit schematic for full-chip verification of radio transceiver transistor-level circuits
within a system test bench. MBOA bit and frame accurate time-domain waveforms are automatically linked to the
input of the receiver circuit. Nexxim circuit simulation is performed on the full receive chain with all extracted
parasitics included. Figure 16 contains plots of some representative results from the full-chip analysis. Figure 16
(a) is a spectral plot of the signal at the input to the receiver and Figure 16 (b) is a constellation plot showing the
detected QPSK symbols at the receiver.
SP
mod _ou t
M I XE R3P
fin al _tx
FF T L=8 19 2*2
T YPE=1
WINDOW _T YPE= 1
INIT SAMP=0
S xx ( f)
OUT
LO
SP
U2
rx_rfi n
UWB_ Rx
SIN K
U1
DAC2
rx_ out_ I
MNCH
R
DAC
AMP
NS1 =t m
i e _s ync _drop
NS2 =2^2 0
Vsu ppl y= 1.2
LNA_PD=0
Bal un _PD=0
RxMx_PD=0
LNA_L G= 0
flo =4 g
rxlo _a mp= 800 m
txrx =0
RxBB_ PD= 0
Vctrl1 =-0. 14 5
Vctrl2 =-0. 11
VcmOut= 0.68
Ibi as _l na =0
Ibi as _mx= 0
Hata
M I XE R3P
IN
I
40
MS21= 15
I
C DM UX
RITOC
rx_ou t_ Q
CT ORI
pa pr=9
exp and =4 0
fc utoff=2 56MHz
fl e ngth= 10 24
fb eta= 0.02
R
rx_i n
OUT
LO
SP
SP
ti mi ng_ re co v_rx
SP
bb tx
bb rx
SRDC
BMEN
NB=2
Q
SP
T YPE= 0
NS1= 1
NS2= 56
SI NK
SP
T YPE= 0
NS1=3 2
NS2=1 33
rx_ fr e q
TYPE=0
NS1 =16 0
NS2 =5
SP
SIN K
SP
T YPE=0
NS1=3 2
NS2=1 28
CDM U X
C MU X
RIT OC
M= 4
CCONST
R
CSCALE
DF= 40
rx _ti me
C MU X
01 10/ 6
NB=1 12*2 *symb ol s/2. 5
BR=d ata_ra te *2
SEED= 1
T YPE=0
NS1=1
NS2=5 6
CCONST
I
REAL_ CONST =0V
I MAG_CONST =0 V
NSAMP=32 *symb ol s
SAMPLE_RAT E= da ta _rat e
tx _ fr e q
SP
BSRC
RANDOM
tx _b i ts
REAL_ CONST= 0V
IMAG_CONST =0 V
NSAMP= symb ol s
SAMPLE_RATE= dat a _rat e
CSCALE
C DM UX
CM UX
IFF T
C MUX
C MU X
GAIN=1 /s qrt( 2 )
T YPE= 0
NS1=5 7
NS2=7 1
FF TL =1 28
CCONST
R
SI NK
T YPE=0
NS1 =1 28
NS2 =5
F FT L= 12 8
SINK
REAL_ CONST= 0V
IMAG_ CONST =0V
NSAMP= 5*s ymbol s
SAMPLE_RATE=d ata_ ra te
SP
REAL _CONST =0 V
T YPE= 0
IMAG_ CONST= 0V
NS1= 15
NSAMP=1 5*s ymbo sl
NS2= 56
SAMPL E_ RAT E=d ata_ra te
tx _ ti me
T YPE=0
NS1 =5 6
NS2 =5 6
CD MU X
C DM UX
CCONST
I
FF T
CD MU X
T YPE=0
NS1 =57
NS2 =71
R
CT ORI
R
CSCAL E
I
GAIN= sq rt (2)
MBEN
6/011 0
CT ORI
I
TYPE=0
NS1 =56
NS2 =56
Q
BERP
M=4
NB=2
I
Q
CT ORI
I
C MU X
CDM U X
T YPE= 0
NS1= 15
NS2= 56
rx_ b ti s
IN
I
Ir e
Q
EVMP
f
re f
EVM
Figure 15. Full-chip verification for radio transceiver transistor-level circuit in system test bench.
RFIC Design and Verification
14
(a)
(b)
Figure 16. Full-chip verification simulation results. (a) Spectrum at input to receiver. (b) Constellation plot
of QPSK symbols detected at the receiver.
Applications
The RFIC design solution is applicable to many diverse applications from sophisticated analog-digital SoCs
containing wireless front-ends to simpler RFIC devices that only contain RF circuit blocks. The method provides
for higher fidelity in the simulation of the sensitive and critical analog sections by combining rigorous EM
extraction with more powerful circuit simulators in an integrated design flow. Wireless and high-speed devices for
networking and communications provide the greatest opportunity for this flow. A selection of likely applications
is:
•
•
•
•
•
Cellular CDMA power amplifier
10Gb/s Backplane Transceiver
GHz-frequency PLL
Gb/s Data Converter
UWB Radio Transceiver.
UMC – Ansoft Collaboration
UMC and Ansoft have a shared vision regarding partnerships and the need for advanced technology in the SoC
design flow. Partnerships are developed to address significant needs in the IC design industry that align with the
mission of both partners. The best partnerships are those that have the additional benefit of scaling the business of
the members of the partnership and the business of their joint customers. The collaboration between UMC and
Ansoft aims to build the most reliable solution for SoCs that contain high-performance analog front-ends by
leveraging UMC’s advanced RFCMOS processes and Ansoft’s new technology for circuit and electromagnetic
simulation.
UMC 0.13um RFCMOS Solution
UMC provides a logic-based technology platform with Mixed Signal/RF devices--a high performance, low cost
solution for SOC designs. Besides providing a common technology platform, UMC also provides a design
environment to support Mixed Signal/RF designs, meeting our customers' time to market needs. The design
environment includes Mixed Signal/RF foundry design kits, accurate models and P-cells, automatic schematic
driven layout environments with links to electromagnetic extraction, simulation, and verification flow. The UMC
RFIC Design and Verification
15
0.13um CMOS process offers low 1.2V core voltage, Ft of 105 GHz, Fmax = 90 GHz, and very low noise figure and
high Q inductors.
Ansoft EDA Technology
Ansoft provides electronic design automation (EDA) products that deliver high-performance and high-accuracy to
support modern electronic and RF integrated circuit design. Ansoft’s best-in-class technology for circuit and
electromagnetic simulation complements established monolithic IC design flows allowing designers to simulate
sensitive analog circuits while including layout and packaging electromagnetic effects. Electromagnetic simulation
using such tools as the High Frequency Structure Simulator (HFSS) provides accurate modeling of on-chip
passives, layout, package parasitics, and substrate coupling. Ansoft’s Nexxim circuit simulator links directly into
the mainstream Cadence design environment and adds high-performance transient and harmonic balance
simulation. Harmonic balance, including the capacity to handle today’s larger designs, allows the engineer to
predict non-linear performance of circuits including gain compression, IP3, inter-modulation, mixer spurious,
phase noise, and sensitivity. Transient simulation plus Harmonic Balance in a singular simulator allows circuit
validation in time- and frequency-domain under real-world communications waveforms.
Benefits
The RFIC design flow significantly benefits fabless semiconductor design organizations now and in the future.
Organizations large and small are highly concerned with achieving silicon success in order to avoid expensive respins and to hit a particular market window. The lifespan of wireless products is typically 12 – 18 months.
Avoiding a program slip for re-spin can make the difference between successful design-in and missed opportunity.
The RFIC flow provides a methodical approach to the design, simulation, and integration of complex SoCs. By
allowing continuous monitoring of project development using system-level verification and co-design with
transistor-level circuits, fabless design organizations can establish true metrics for design feasibility and efficacy.
The examples shown here are for the UMC 0.13um RFCMOS process. The need for this flow increases as
technologies scale to smaller technology nodes where parasitic and interconnect effects are more significant.
As technologies continue to scale to smaller technology nodes and include greater analog complexity and RF
functionality, parasitic effects and the need to solve ever larger circuits faster, with more accuracy, becomes
increasingly more significant. The adoption of newer methods is no longer a question of if, but when.
Conclusion
UMC’s advanced RFCMOS process combined with electronic design automation (EDA) tools from Ansoft and
other established vendors provide the platform for developing advanced RFICs. This joint effort leverages UMC’s
production-proven 0.13um RFCMOS process for RFICs with advanced circuit simulation and electromagnetic
extraction tools from Ansoft. This document described RFIC design and verification in the RFIC design flow and
demonstrated key benefits by real examples from an ongoing UWB radio project. It was shown that additional
fidelity in modeling, simulation, and verification coverage can be gained by following this method.
RFIC Design and Verification
16
About the Companies
UMC
UMC (NYSE: UMC, TSE: 2303) is a leading global semiconductor foundry that manufactures advanced process
ICs for applications spanning every major sector of the semiconductor industry. UMC delivers cutting-edge
foundry technologies that enable sophisticated system-on-chip (SoC) designs, including volume-production,
industry-leading 65nm, and mixed signal/RFCMOS. UMC’s 10 wafer manufacturing facilities include two
advanced 300mm fabs; Fab 12A in Taiwan and Singapore-based Fab 12i are both in volume production for a
variety of customer products. UMC employs approximately 12,000 people worldwide and has offices in Taiwan,
Japan, Singapore, Europe, and the United States. UMC can be found on the web at http://www.umc.com.
Ansoft
Ansoft is a leading developer of high-performance electronic design automation (EDA) software. Engineers use
Ansoft’s software to design state-of-the-art electronic products, such as cellular phones, Internet-access devices,
broadband networking components and systems, integrated circuits (ICs), printed circuit boards (PCBs),
automotive electronic systems and power electronics. Ansoft markets its products worldwide through its own
direct sales force and has comprehensive customer-support and training offices throughout North America, Asia
and Europe. For more information, please visit www.ansoft.com.
UMC USA
488 De Guigne Drive,
Sunnyvale, CA 94085, USA
Tel: 1-408-523-7800
Fax: 1-408-733-8090
www.umc.com
Ansoft Corporation
225 West Station Square, Suite 200
Pittsburgh, PA 15219
Tel: 412-261-3200
Fax: 412-471-9427
www.ansoft.com
RFIC Design and Verification
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