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Elektrotechnik & Informationstechnik (2009) 126/11: 390–395. DOI 10.1007/s00502-009-0689-2
Digital signal processing for data converters
in mixed-signal systems
Ch. Vogel, St. Mendel, P. Singerl, F. Dielacher
In this paper, we investigate data converters that exploit the possibilities of advanced digital signal processing. After discussing the
necessity and prospects of digital signal processing for data converters to comply with next generation system specifications, we
demonstrate three examples of digitally enhanced data converters: time-interleaved analog-to-digital converters, all-digital phase-locked
loops, and predistorted power amplifiers. To this end, we extend the term of a data converter to a cooperating system that includes digital
and analog pre=postprocessing units to fullfil the required specification.
Keywords: data converters; digital enhancement; signal processing
Digitale Signalverarbeitung fu€r Datenumsetzer in Mixed-Signal-Systemen.
In diesem Beitrag untersuchen die Autoren Datenumsetzer, die die Mo€glichkeiten von fortgeschrittener digitaler Signalverarbeitung ausnutzen. Nach der Diskussion u€ber Notwendigkeit und Aussichten der digitalen Signalverarbeitung fu€r Datenumsetzer zur Erfu€llung
zuku€nftiger Systemspezifikationen werden anhand von drei Beispielen digital verbesserte Datenumsetzer erla€utert: zeitverschachtelte
Analog-zu-Digitalumsetzer, digitale Phasenregelkreise und vorverzerrte Leistungsversta€rker. Zu diesem Zweck wird der Begriff des
Datenumsetzers zu einem kooperierenden System erweitert, das zur Erfu€llung der geforderten Spezifikationen digitale und analoge Vorund Nachverarbeitungseinheiten umfasst.
Schlu€sselwo€rter: Datenumsetzer; digitale Verbesserung; Signalverarbeitung
Received May 5, 2009, accepted September 23, 2009
ß Springer-Verlag 2009
1. Introduction
Almost any electronic device we are using today is a mixed-signal
system, which consists of analog and digital signal processing units
connected by data converters. Traditionally, analog and digital signal
processing are strictly separated by the interface units, but recently
these boundaries have become blurred. We cannot strictly distinguish between signal processing domains anymore. The many amenities of digital signal processing and the tremendous scaling of
digital CMOS technology let researchers and circuit designers
develop new concepts that exploit digital signal processing to
improve, enhance, and emulate the characteristics of data converters (Murmann, Vogel, Koeppl, 2008). This development is driven by
market demands requiring flexible mixed-signal devices with more
functionality for the same price whereby data converters become
the bottleneck of the system.
In principle the most stringent design requirements are power
consumption and costs. In contrast to costs, which have always been
important, the power consumption has become progressively important with the evolution of mobile devices leading to energy centered
designs. The discussion about environmental care amplifies this
development to carefully deal with energy resources. In principle,
we have two possibilities to increase the operating time of battery
based systems: to reduce their power consumption and to increase
their power efficiency. Power reduction has always been a major
concern in mobile devices and engineers are quite successful in
realizing low power systems on circuit level. The technology scaling
of digital CMOS circuits and the reduction of supply voltage has
boosted this trend. A further reduction of the power consumption,
however, requires an optimization of the entire system on the system level before optimizing parts on the circuit level. But even if the
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power consumption in the device is reduced to a minimum, we need
a fixed amount of power for the communication at the front end.
This power is determined by physical demands, e.g. the path loss of
electromagnetic radiation, and cannot be further reduced at this
point. The only remaining possibility is to increase the processing
efficiency, e.g., in the power amplifiers, to avoid any power loss.
2. Digitally enhanced data converters
By comparing analog and digital integrated circuits we can see a cost
gap and an energy gap between them. Although we cannot compare blocks of integrated circuits directly as they typically fulfill quite
different tasks, we can extract trends from basic observations. For
digital circuit design we have reached a much higher level of automation as for analog circuit design. The designer is supported and
guided by a large amount of tools, which allow for building circuits
with first silicon success. Moreover, build-in self tests allow for
efficiently testing the functionality of digital circuits after they have
been manufactured. In contrast, the tool support for analog designs
is limited and the design typically needs two or three design cycles
including the time-consuming manufacturing of prototypes and
their lab testing. For the energy consumption we get a similar
picture. Although, the consumption is in general not directly comparable, we can find interesting comparisons for particular designs.
For analog-to-digital converters, for instance, it has been shown that
starting with an accuracy of about 40 dB we can use additional
Vogel, Christian, Dipl.-Ing. Dr., Mendel, Stefan, Dipl.-Ing., Signal Processing and
Speech Communication Laboratory, Graz University of Technology, 8010 Graz, Austria;
Singerl, Peter, Dipl.-Ing. Dr., Dielacher, Franz, Dipl.-Ing. Dr., Infineon Technologies
Austria AG, 9500 Villach, Austria (E-mail: vogel@tugraz.at)
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digital logic without significantly increasing the power consumption
of the overall system (Murmann, Vogel, Koeppl, 2008). This trend
was basically driven by Moore’s law and the increasing gap between
analog and digital circuit integration. The example of the power
consumption of analog and digital circuits in ADCs shows, however,
that we can use extensive digitally enhanced data converters in
mixed-signal systems.
Digitally enhanced data converters exploit the growing gap
between analog and digital circuits to optimize the overall performance of mixed signals systems. In particular digital circuits can
support data converters as they are often the bottleneck of the
system. In order to be successful, the typical divide-and-conquer
approach has to be reconsidered. Instead of designing separated
functional blocks, we have to use a holistic design approach as
shown in Fig. 1 to develop cooperating blocks that exploit system
knowledge. For example, we can simplify identification of data
converter impairments by knowing the statistics and characteristics
of the input signals. Therefore, the functional blocks become application dependent and the application moves closer to the circuits.
Indeed, as we will show, we can overcome performance limits with
such an approach, but as a drawback the design complexity
increases and the reuse of functional blocks becomes more difficult.
Fig. 1. Holistic design approach
3. Examples of digitally enhanced data converters
In the following, we will discuss three examples of digitally enhanced
data converters, which demonstrates the possibilities of advanced
digital signal processing. First, we will discuss time-interleaved ADCs,
which is a converter topology of increasing popularity stemming
from the possibilities of advanced digital post-processing. The second example is an all-digital phase-locked loop (ADPLL). In contrast
to an analog phase-locked loop, an ADPLL is also a digital-to-frequency converter. In the final example, we explore efficient RF
power amplifiers. This example particularly shows the holistic design
approach with merging functional analog and digital blocks, i.e., a
digital filter, an ADC, and a power amplifier, to obtain the best
overall performance of the converter. In this sense, the overall system may be seen as data converter as well.
3.1 Digitally enhanced time-interleaved ADCs
As shown in Fig. 2, a time-interleaved ADC (TI-ADC) consists of M
parallel channel ADCs that take samples in a time-interleaved manner. Hence, each sample is periodically taken by a different channel.
In the ideal case, a TI-ADC is identical to a single channel ADC
running at an M-times higher rate. The idea of a TI-ADC is more
than 25 years old, but it has needed today’s stringent requirements
on the one hand and the possibility of using extensive digital postprocessing on the other hand to make this architecture attractive
(Vogel, Johansson, 2006). Time interleaving is used for realizing
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Fig. 2. The principle of a time-interleaved ADC
high-speed CMOS ADCs as needed in sampling oscilloscopes (Poulton, et al., 2003) and for low-power medium-speed ADCs as needed
for next generation communication systems (Draxelmayr, 2004).
The main problem with TI-ADCs are matching problems among
the channels (Vogel, 2005). As soon as their channel characteristics
differ, additional modulation products appear in the output spectrum and significantly degrade performance measures such as the
signal-to-noise ratio and the spurious-free dynamic range. These
modulation products are generated by the periodic change of the
channel characteristics due to time interleaving. An illustrative example is the gain mismatch of a two-channel TI-ADC. In a two-channel
TI-ADC all even samples are taken by the first channel with gain g1
and all odd samples are taken by the second channel with gain g2. In
this way the samples are multiplied by the sequence g1, g2, g1, and
so on. As soon as the gains differ, we obtain a modulation of the
input signal producing spurious components in the output spectrum.
In general, many characteristics of the channels can differ, but in the
past three characteristics have been extensively investigated, as they
have the greatest impact on the performance of a TI-ADC (Vogel,
Kubin, 2005). The first is the already introduced gain mismatch.
Second, we have offset mismatches and, third, we have time offset
mismatches. From this group of mismatches, the calibration of time
offset mismatches is the most difficult task and was one reason why
TI-ADCs have not been used for medium to high resolution applications in the past. A time offset is the deterministic time deviation
from the ideal sampling time as shown in Fig. 3.
Fig. 3. Time offset mismatches
The time offset is affected by different time delays of the clock
signals for each channel ADC as well as by the signal delays caused
by the channel characteristics themselves. Conceptually, a time-offset mismatch leads to a periodically non-uniformly sampled signal.
Although there is a vast amount of literature on the digital recon-
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struction of non-uniformly sampled signals, it is not practical to
simply apply these methods.
As outlined in the introduction, the immense evolution of integrated digital circuits allows for combining advanced digital algorithms with analog interface circuits. Nevertheless, the additional
digital circuits are still not for free and are limited by energy tradeoffs between the digital and the analog circuits. Fortunately, we can
exploit a system property of time offset mismatches to simplify the
reconstruction. The time offsets are small compared to the sampling
period of the TI-ADC. With this property new efficient algorithms can
be developed to comply with the restricted requirements (Tertinek,
Vogel, 2007; Tertinek, Vogel, 2008). The situation for the identification of timing offset mismatches is even worse. Although blind identification methods exist, e.g., (Vogel, 2008), the research is today
more focused on application oriented approaches, e.g., calibration
of TI-ADCs in communication receivers (Tsai, Hurst, Lewis, 2009).
By using digital enhancement and time interleaving we can build
better ADCs. In order to obtain useful algorithms, we need a holistic
design approach that considers the entire system to find the best
trade-off between digital and analog signal processing.
3.2 Digitally enhanced all-digital phase locked loops
All-digital phase-locked loops (ADPLLs) are an attractive alternative
to traditional analog charge-pump PLLs with equivalent or even
superior performance. The main motivation to shift the functional
complexity towards digital signal processing is driven by the market
demand to implement the entire RF transceiver on a single chip with
preferably one technology. In mass markets like wireless communications low-cost solutions are essential, and the most aggressive
CMOS technology seems to be the best choice. Consequently,
CMOS compatible solutions for typical analog components, such
as PLLs, are required.
Figure 4 shows a phase-domain ADPLL architecture for wireless
communications (Staszewski, Balsara, 2006). Although the name
ADPLL may suggest different, an ADPLL is a mixed-signal system,
consisting of digital parts, analog parts, and data converters
between them. The key component of an ADPLL is the digitally
controlled oscillator (DCO) that replaces the traditional voltage controlled oscillator (VCO). It converts a digital tuning word d½m into an
analog oscillation with frequency fv ½m. The feedback path converts
the analog oscillation back into a digital phase signal ’v ½m which is
then compared with a digital reference phase signal ’r ½m to pro-
duce a digital phase error signal ’e ½m (Staszewski, Balsara, 2006;
Mendel, Vogel, 2007).
The ADPLL has basically two data converters. The DCO converts a
digital value into an analog oscillation of certain frequency, i.e., it
acts as an digital-to-analog converter (DAC), and in the feedback
path a counter in combination with a time-to-digital converter (TDC)
converts the oscillation back into a digital phase signal, i.e., it acts as
an ADC. The digital phase signal from the feedback path is compared to the reference phase signal at the clock rate of the nonuniform clock CKR (on average @ fref with time index m). The nonuniform clock CKR is introduced to synchronize the DCO output
frequency (CKV @ fv and time index i) with the reference clock
domain (clock REF @ fref). Hence, within one period of the clock
CKR, the counter accumulates one at the rate of the DCO output
frequency fv to produce the digital phase signal ’v ½i with integer
accuracy, and the TDC increases this accuracy by measuring the time
between CKV and REF. In high-frequency applications the DCO is
typically an LC oscillator with varactors, i.e., switchable capacitances, implemented in CMOS. The frequency resolution of the
DCO is limited to the frequency change of a single varactor, which
is in the range of 20 kHz (Staszewski et al., 2003). This strong
quantization leads to undesired spurs and an increased noise level
in the output phase noise spectrum. In order to increase the instantaneous frequency resolution and shift the quantization errors
towards higher frequencies, the digital tuning word d½m is dithered
by a modulator.
The modulator allows ADPLLs to achieve equivalent performance
as analog PLLs. Additional digital signal processing techniques, however, can enhance ADPLLs beyond the performance of analog PLLs.
In gear shifting for instance, the intrinsic trade-off between transient
behavior (lock time) and steady-state behavior (phase noise performance) is circumvented by iteratively refining the loop bandwidth
(Staszewski, Balsara, 2006, 2007). Thus, with little additional effort,
a fast lock time and a good phase noise performance can be provided by changing the digital loop filter coefficients. Furthermore,
two point modulation allows for modulating the DCO output frequency in the digital domain (Staszewski, Leipold, Balsara, 2005).
Therefore, the modulation data is injected at two points (a direct and
a compensation feed) of the system, so that the output frequency
fv ½m is effectively modulated. Therefore accurate knowledge of the
time-varying DCO gain K is required to avoid any DCO transients.
Off-line (Staszewski, Leipold, Balsara, 2005) and adaptive LMS-
Fig. 4. A phase-domain ADPLL architecture (Staszewski, Balsara, 2006)
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Fig. 5. Block diagram of a radio frequency transmitter with digital predistortion
based (Staszewski et al., 2006) identification methods have been
proposed. These examples emphasize the increased flexibility and
new possibilities of ADPLLs in contrast to their analog counterparts.
The drawback, however, is the increased system complexity. Circuit
designers need in addition to good analog design skill, a deep
system level understanding to effectively exploit the mentioned
advantages.
3.3 Efficiency enhanced radio frequency power amplifiers
The power efficiency of high power radio frequency (RF) transmitters
in radio base-stations is one of the most important parameters,
because it affects production costs (transistor chip area) and operating costs (power consumption) considerably. To operate the RF
transmitters with an admissible efficiency (30 % linear efficiency),
the final RF power amplifier (PA) output stages are usually driven in
their nonlinear region due to the approximate inverse relationship
between the PA linearity and the PA efficiency (Kennington, 2000;
Cripps, 1999; Cripps, 2002). The drawback of a higher efficiency are
in-band distortions caused by the nonlinearity of the PA, which
degrades the bit-error performance on the receiver side. Moreover,
the nonlinearity causes spectral regrowth, which leads in general to
an unacceptable strong adjacent-channel interference. Bandwidth
efficient modulation schemes such as wideband code-division-multiple-access (WCDMA) or orthogonal frequency-division-multiplexing
(OFDM) are especially vulnerable to nonlinearities due to their highly
fluctuating RF signal envelope and the resulting high peak-to-average power ratios (PAPR) up to 13 dB. In order to comply with the
spectral masks imposed by the regulatory bodies and to reduce the
bit error rate on the receiver side, the PA must be linearized.
One of the most efficient linearization techniques is the digital
baseband predistortion (Kennington, 2000; Cripps, 1999; Cavers,
1989). A digital predistorter is a functional block that precedes the
PA in order to compensate the nonlinear distortion of the RF PA
(DPD-core in Fig. 5). The digital predistorter incorporates the approximate inverse functional of the RF PA to obtain in the ideal case an
overall linear system whose RF PA output signal is an amplified
version of the input signal. Therefore, a PA with predistortion can
be seen as a digitally enhanced DAC, where a holistic approach is
mandatory that encompasses knowledge of the PA and RF signal
processing, the data converter and analog signal processing, and the
predistorter and digital signal processing.
If the input signal is narrowband, the predistorter can be often
realized by static nonlinearities (Raich, Zhou, 2002; Singerl, Kubin,
2005) (complex look-up table techniques as shown in Fig. 6) to
obtain a sufficient performance in terms of linearity (Cavers,
1989). If the input signal becomes wideband, the memory effects
(electrical and thermo-electrical) (Vuolevi, Rahkonen, 2003; Vuolevi,
Rahkonen, Manninen, 2001; Boesch, Gatti, 1989) of the PA cannot
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Fig. 6. Block diagram of a look up table based digital predistortion
be longer neglected if we want a sufficient linearization performance. Due to the memory effects, the output signal of the PA at
a certain time instant depends not only on the current input signal
but on the past history of the input signal as well (Schetzen, 1980;
Rugh, 2002; Mathews, Sicuranza, 2000). The introduced memory
makes the wideband predistortion more difficult. For wideband
applications, complex Volterra series are a powerful mathematical
tool to describe memory-based weak nonlinearities (Schetzen, 1980;
Rugh, 2002; Mathews, Sicuranza, 2000). A serious drawback of a
Volterra series is the large number of parameters that must be
determined for the predistortion resulting in a high computational
complexity (Mathews, Sicuranza, 2000). For this reason, in wireless
RF transmitters special subtypes of Volterra systems with a lower
number of parameters – such as Wiener systems, parallel Wiener
systems, Hammerstein systems, and memory polynomials – are digitally applied to linearize the RF PA (Kim, Konstantinou, 2001;
Yeqing, Qi, Tianren, 2003; Ding et al., 2004).
In general there are two possibilities to estimate the parameters of
the digital predistorter core in Fig. 5. The first one is to identify the
nonlinear behavior of the RF PA itself and calculate its inverse. This
can be accomplished by using for example a pth-order inverse
(Schetzen, 1980), but whose structure becomes computational complex for higher order nonlinearities. The second method is to identify
the digital predistorter with an indirect learning architecture (Kim,
Konstantinou, 2001; Yeqing, Qi, Tianren, 2003; Ding et al., 2004;
Ding, Raich, Zhou, 2002; Eun, Powers, 1997). Therefore we need a
feedback path in the RF transmitter as depicted in Fig. 5, which is
composed of a cascade of a frequency down-converter and an
analog to digital converter (ADC). The predistorter input signal
~ ½n and ADC output signals y~½n in Fig. 5 are employed to identify
w
the parameters for the DPD core adaptively. The exact knowledge of
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the application and the statistics of the involved signal can significantly simplify the identification task.
To further push the limits of RF PAs digital enhancement techniques are necessary. These techniques can only be successful when in
a a holistic design approach all components – from the digital signal
to the PA output signal – are considered together. Therefore, the
functional blocks become application dependent and the application
moves closer to the circuits. Indeed, with an increased design complexity, we can overcome performance limits with this approach.
4. Conclusion
In this paper we have shown that in a holistic design approach
digitally enhanced data converters can overcome the limitations of
analog signal processing in deep-submicron circuit technologies. The
scope of a data converter expands and includes digital=analog preprocessing and analog=digital postprocessing to fullfil today’s stringent system specifications. In consequence, former individual blocks
become mutually dependent and the design complexity increases.
Moreover, as the designers try to move the data converter closer to
the sensor=antenna to obtain more flexibility, the application moves
closer to the circuits and further increases the design complexity.
Digital signal processing for data converters becomes an essential
part of circuit design.
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Authors
Christian Vogel
received the Dipl.-Ing. degree in Telematik
and the Dr. techn. degree in electrical and
information engineering (summa cum laude)
from Graz University of Technology, Graz,
Austria, in 2001 and 2005, respectively.
From 10=2004 to 12=2004, he was visiting researcher at the Division of Electronics
€ping University, Sweden,
Systems at Linko
and from 1=2008 to 6=2009, he was a postdoctoral researcher at the Signal and Information Processing Laboratory at ETH Zurich, Switzerland. Currently, he is senior researcher at
the Signal Processing and Speech Communication Laboratory at
Graz University of Technology, Austria. His research interests include
the design and theory of digital, analog, and mixed-signal processing
systems with special emphasis on communication systems and digital enhancement techniques for analog signal processing systems.
Christian Vogel is author and co-author of 35 international publications, where three of them have received best paper awards.
Stefan Mendel
was born in Graz, Austria, in 1981. He
received the Bakk. techn. degree and Dipl.Ing. degree in Telematik from Graz University
of Technology, Austria in 2004 and 2006,
respectively. During his master thesis he
worked on post compensation of channel
mismatches in time-interleaved analog-todigital converters. Since 2006, he has been
pursuing his Ph.D. at the Signal Processing
and Speech Communication Laboratory at Graz University of Technology, Austria, working on digital synthesizers for gigahertz-range
fast frequency-hopping systems. His research interests are all-digital
phase-locked loops, analog-to-digital converters, digital enhancement of analog circuits, mixed signal systems, and systems for communications.
November 2009 | 126. Jahrgang
Peter Singerl
received his M.Sc. in telematics and his Ph.D.
in electrical engineering from Graz University
of Technology, Austria in 2000 and 2006,
respectively. From 8=2003 to 3=2007 he
was with the Christian Doppler Laboratory
for Nonlinear Signal Processing at the Graz
University of Technology, Austria. He joined
Infineon Technologies Austria in 8=2000,
where he is currently working as a Concept
Engineer for wireless communication applications. Peter Singerl’s
research interests include the identification and linearization of
power amplifiers as well as system concepts for high power radio
frequency transmitters. Peter Singerl received two international student best paper awards and has authored and co-authored more
than 20 international publications including journal and conference
papers and patents.
Franz Dielacher
received his M.Sc. and Ph.D. degrees in electrical engineering from Graz University of
Technology, Austria, in 1981 and 1990,
respectively. Since 1994, his main focus has
been high-speed digital communications.
Current research interests include RF- and
mixed-signal IC design, telecom-system-integration and design methodologies.
He has worked in circuit design and concept engineering including standardisation for wireline and wireless
communications. Dr. Dielacher is currently chief scientist for telecom
circuits and RF-Power components at Infineon Technologies.
He has been a member of the IEEE ISSCC program committee
since 1999; is currently the ISSCC Wireline subcommittee chair and
is a member of ESSCIRC’s steering committee.
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