IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 5, MAY 1997
809
A 3-Terminal Model for Diffused
and Ion-Implanted Resistors
Richard V. H. Booth and Colin C. McAndrew, Senior Member, IEEE
Abstract— In this paper, we present a new, physically based
3-terminal model for diffused and ion-implanted resistors. The
model accounts for the effects of geometry, temperature, and
bias, and includes parasitic p-n junction diodes. The junction
depletion capacitances are distributed to model high-frequency
behavior accurately.
I. INTRODUCTION
T
HE ELECTRICAL behavior of integrated (diffused and
ion-implanted) resistors depends nonlinearly on geometry, temperature and bias [1]–[3]. The temperature dependence
is caused by the change with temperature both of mobility
and of the built-in potential, and hence depletion width, of the
junction between the resistor body and the tub or substrate.
The bias dependence is caused by the change with bias both of
mobility and of the depletion widths at the bottom and sides of
the resistor body. Consequently, a 3-terminal model is required
to model integrated resistors properly, two terminals for the
ends of the resistor, and a third terminal for the tub/substrate.
Two-terminal resistor models with voltage and temperature
coefficients can be used for resistors with a grounded tub
or substrate, since each terminal voltage is then implicitly
referenced to the ground terminal. If the tub or substrate is
grounded, then the third device terminal coincides with the
2-terminal resistor model reference node. However, these 2terminal models are not accurate for integrated resistors whose
tub or substrate is not connected to ground. A further difficulty
may arise when these models are used outside of the range of
biases where data was taken for parameter extraction. In this
case, the model may predict very unrealistic resistance values.
In this paper we present a new 3-terminal resistor model for
integrated resistors. The temperature and bias dependences of
the model are physically based, so the model is accurate and
can be used for resistor geometries outside the range used to
determine the parameters of the model. In addition, the model
accounts for parasitic capacitances, resistances and junction
currents.
In Section II, we present the derivation of the resistor model,
including dc characteristics, parasitic elements, temperature
and frequency response. In Section III, we compare model
results with measurements of integrated resistors over bias
and temperature.
Manuscript received September 10, 1996; revised Decemer 6, 1996. The
review of this paper was arranged by Editor D. A. Antoniadis.
R. V. H. Booth is with Bell Laboratories/Lucent Technologies, Allentown,
PA 18103-6209 USA.
C. C. McAndrew was with AT&T Bell Laboratories. He is now with
Motorola Corporation, Tempe, AZ 85284 USA.
Publisher Item Identifier S 0018-9383(97)03006-2.
Fig. 1. Cross section along channel of n-well resistor.
II. MODEL DERIVATION
In this section, we present the derivation of the resistor
model. The complete model includes two sections for the
resistor body, contact and tub/substrate parasitic resistances,
and parasitic p-n junction capacitances and currents. We begin
first with the derivation of the – relation for a resistor
considered as a single dc element. Following this, we present
the model with parasitics and give the motivation for splitting
the model into two internal sections.
A. DC Characteristics
Fig. 1 shows an idealized cross section of an n-tub integrated resistor. The resistor has three contacts, one at each
end to n regions in the body of the resistor and one to the
substrate. There is a p-n junction between the substrate and the
resistor body that is reverse biased in normal operation. The
device resistance is mainly determined by the resistivity and
geometry of the resistor body,
,
and
, where
is the depth of the body to substrate
metallurgical junction. A depletion region exists at the bottom,
sides and ends of the n-tub region. The depletion region
thickness, and thus the resistance of the device, is modulated
by both the junction bias and the operating temperature.
As Fig. 1 shows, the biases
and
are applied to
terminals 1 and 2, respectively, and
is the substrate bias,
applied to terminal 3. The polarity of the resistor current is
defined to be positive when it flows into terminal 2. The biases
and
are defined as
and
(1)
respectively.
At a position
along the length of the resistor, an inhas a voltage drop
finitesimally small slice with thickness
0018–9383/97$10.00  1997 IEEE
810
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 5, MAY 1997
, as Fig. 1 shows. The width and depth of the conducting
(undepleted) portion of the resistor at this point in the channel
are functions of the local resistor body bias with respect to
the substrate. The conducting portion, that above the depletion
edge, is shaded in Fig. 1. Assuming an abrupt junction and the
depletion approximation, the channel depth at is given by
where
is an effective length,
and
We have also used
to simplify the last term in (8).
Expanding
about a voltage
gives
(2)
(9)
and the channel width is given by
Here,
is the junction depth,
is the difference between
the metallurgical width and the masked width
is
and
are the built-in
resistor body to substrate bias at
potentials, and
and
are the depletion-width factors, of
the bottom (area) and side (perimeter) portions of the body to
substrate junction, respectively.
includes the factor 2, for
two sides of the resistor.
The current through the slice is
the first 3 terms of (9) in (8) give
For
(3)
(10)
and for
this becomes
(4)
is the electron mobility at depth
which is a
where
function of temperature, doping density and electric field. For
moderate currents and temperatures, the electron density is
nearly equal to the doping density
We assume that the
doping density and mobility are nearly constant over the range
of depths of the resistor where the depletion edge is found. Let
be the depth of the conducting region at zero reverse-bias.
Then, under the above assumptions, (4) may be rewritten as
(11)
Equation (11) gives the first order voltage dependence of
the 3-terminal resistor model, for a resistor considered as a
single element.
For short resistors, the electric field in the channel is large
enough for the average carrier speed to approach the saturated
drift speed. This effect is modeled as a mobility degradation by
(12)
is the zero-bias sheet resistance of the resistor.
where
Using the definition for , (2), in (5) yields
is the mobility at zero bias and
is the critical
where
field for saturation of the drift speed.
From (2) and (3), the channel pinches off if
is greater
than either
(6)
(13)
(5)
where
Note that for mobility and
doping constant through the entire resistor body
or
(14)
since
, (3), in (6)
in this case. Using the definition for
(7)
and are limited so that they do not
To account for this,
exceed the minimum of
and
Since the expansion
leading to (11) is not accurate for large
, the biases
and must be forced to saturate slightly before this minimum.
To ensure that the model is
-continuous, the limiting
approach of [4] and [5] is used.
and
in (11) are thus
replaced by
and integrating over the length of the resistor, gives
ln
(8)
(15)
is either
or
is the saturation voltage,
where
and
is a parameter that controls the “hardness” of the
saturation.
BOOTH AND McANDREW: 3–TERMINAL MODEL FOR RESISTORS
811
Adding the high field and saturation effects to the first order
model gives the complete – model for an integrated resistor
considered as a single section
(16)
where
given by (15), and
and
are the limited voltages,
The large-signal resistance is thus
(17)
where
Fig. 2. Equivalent circuit of resistor.
and
The p-n junction diode currents are modeled as
(20)
B. Temperature Dependence
varies with temperature both beThe resistor current
cause the mobility changes with temperature and because the
junction built-in potential changes with temperature.
The temperature dependence of the mobility is modeled by
[6]
(18)
where typically about 2, is the mobility temperature degradation parameter, and
is a reference temperature in K
The temperature dependence of the built-in potentials is
ln
(19)
is the activation energy
where is the thermal voltage, and
for the intrinsic carrier concentration. Typically,
is close
to the band-gap energy.
where is the area associated with the diode current source,
is the saturation current per unit area, and
is the bias
across the junction. It is necessary to include junction currents
to model resistor behavior properly at high temperatures,
when junction leakage is important, and during transients that
forward bias part of the body to tub/substrate junction.
varies with temperature as [1]
(21)
The junction capacitances are given by
,
is the junction bias, and
is the excess depletion
where
charge on one side of the junction. The depletion charges are
modeled by the
-continuous depletion charge model of [5].
Separate components are included for the area and perimeter
of the junction. For each component
(22)
C. Parasitics
The 3-terminal resistor model also includes contact resistances, tub/substrate resistance, and currents and capacitances
of the body to tub/substrate p-n junction. Fig. 2 gives the
equivalent circuit for the complete model. In the equivalent
circuit, there are two resistor sections,
and
, two pn junction diode current sources
and
, and three p-n
junction capacitances,
, and
The reason for this
partitioning is described in the next section.
The contact resistances
and
, and the tub/substrate
resistance
, are modeled as constant series resistances.
Although
has negligible influence on the dc behavior
for normal biases, where the body to tub/substrate junction
is reverse biased, it is required to model ac behavior properly.
where the limited junction bias (for each component) is
ln
(23)
Here,
is the zero-bias junction capacitance,
is the
junction built-in potential,
is the junction grading coefficient, and
and
are parameters that control the charge
is smoothly limited
at high forward bias. In forward bias,
to
Again, the (area or perimeter) component of junction
capacitance is the derivative of (22) with respect to the applied
Since the charge is
-continuous, the
junction voltage
capacitance is also. The areas and perimeters associated with
and
, in the equivalent circuit of Fig. 2, are
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 5, MAY 1997
determined by the partitioning described in the next section.
The zero bias junction capacitance varies with temperature as
(24)
for both area and perimeter components.
D. Two-Section Model
Integrated resistors typically can be several hundred microns
in length, and involve considerable area [1]. For such long
resistors, the corner frequency
(the frequency where the
input admittance with a short circuit termination
begins
to increase noticeably with increasing frequency) is low.
Consequently, the ac behavior of long resistors, at frequencies
of interest in circuits, is dominated by their distributed nature.
The frequency response of integrated resistors with distributed
resistance and capacitance can differ significantly from that
predicted by the simple lumped element model that we have
developed so far.
To improve the model accuracy over frequency, we use two
resistor body sections and distribute the depletion capacitance
over three internal branches, D-A, D-B, and D-C in Fig. 2,
such that the model matches the exact distributed response as
closely as possible. The two resistor body sections are pictured
as
and
in Fig. 2, and each section is modeled by (16).
The 3-junction charge storage elements are labeled
,
and
in Fig. 2. This approach has been reported before;
e.g., [8], [9]. These references present slightly different forms
from the results which we obtain here, since different lumped
equivalent circuits for the distributed RC transmission line
were used.
To determine the best capacitance partitioning between
, and
, we examine an ideal RC transmission
line with constant resistance and capacitance per unit length.
Including the full voltage dependence of the resistance and
capacitance would be considerably more difficult, but under
normal bias conditions, integrated resistors behave nearly
linearly. Reference [8] examines the voltage dependent case.
The input admittance of the line, terminated in a short
circuit, is given by [7]
(25)
and
are the total resistance and capacitance
where
of the resistor, and
Expanding (25) to third order gives
(a)
(b)
Fig. 3. (a) Magnitude and (b) phase of the input admittance for N-section RC
ladders with different numbers of sections. is the capacitance partitioning
number, described in Section III-B.
Thus, at high frequencies,
increases 10 dB per decade,
with a constant 45 phase.
The transadmittance of the ideal RC transmission line,
terminated in a short circuit, is given by
(26)
From (26),
given by
(29)
begins to increase at a “corner frequency”
Expanding (29) to third order gives
(27)
(30)
Equation (26) is a good approximation for frequencies
below and up to about one decade above
Above these
frequencies, (25) approaches
(28)
The result (30) is also obtained in [10] for the case of an
MOS transistor treated as an RC transmission line. From (29)
and (30), the magnitude of the transadmittance decreases to
zero at high frequencies.
BOOTH AND McANDREW: 3–TERMINAL MODEL FOR RESISTORS
813
(a)
Fig. 5. Comparison between measured (circles) and modeled (lines) values
of capacitance of two n-minus resistors. The devices have drawn lengths
of L = 400 m, and two different widths — W = 5; 40 m. The
measurement frequency is 200 KHz.
m
m
in the alternating sequence
, except at
the two endpoints where the capacitance is
Fig. 3 shows the magnitude and phase of the input admittance for several N-section RC ladders compared with the
exact transmission line response. For comparison, the choice
, where the capacitance is equally partitioned to each
node in the ladder, is also shown. As the figure shows, the
choice of
significantly increases the accuracy for both
magnitude and phase.
III. MEASUREMENTS
(b)
Fig. 4. Comparision between measured (circles) and modeled (lines) values
of (a) current and (b) resistance of an n-tub resistor at 25 and 100 C. The
400 m and W = 12 m.
drawn resistor dimensions are L
m=
m
The two-port parameters for the distributed RC circuit
are fully specified by the short-circuit parameters
and
since the circuit is reciprocal:
and
For a lumped two-section model, with two series resistors,
two end capacitors, and one center capacitor, the input admittance and transadmittance of the shorted line are given
by
(31)
and
(32)
where
is the ratio of the central capacitance to the total
capacitance. The choice
gives low frequency
(31)
and
(32) equal to
(26) and
(30) of the ideal
RC transmission line, respectively. We use this partitioning
for the full resistor model.
Segmenting a large resistor into
stages, each of
which is implemented as a two-section model, will improve
the frequency response further. The total number of sections is
In this case, the capacitance is partitioned unequally
The three terminal resistor model has been successfully
used to characterize different types of ion-implanted resistors
processed in several CMOS technologies. Fig. 4(a) shows the
fit of the model to measurements of current in an n-tub resistor,
at two temperatures. Fig. 4(b) shows the large-signal resistance
for the same model parameter and measurement data sets. The
measurements were taken with the tub/substrate terminal fixed
at 0 V, one resistor body terminal stepped in increments of 1.5
V from 0 V to 7.5 V, while the other resistor body terminal
is swept from 0 V to 7.5 V. The data where the resistor
voltage is small
V) have been removed for clarity
on the plot, since division by small values of current amplifies
the measurement errors. The drawn resistor dimensions are
m and
m As the figure shows,
the model accuracy is good over both temperature and bias
variation of the resistors. Geometry variation is not shown in
the figure for clarity, but the model fit was established using
data from a larger resistor together with the data shown in the
figure.
Fig. 5 shows the fit of the model to capacitance measurements of two different area/perimeter ratio n-minus resistors.
The devices have drawn lengths of
m, and
two different widths
m The measurement
frequency is 200 KHz. The model is in excellent agreement
with the capacitance measurements. To establish the parasitic
resistances, capacitance measurements are taken over several
frequencies, and independent measurements of contact resistance are taken.
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 5, MAY 1997
IV. CONCLUSIONS
In this paper, we have presented a new semi-physical
3-terminal model for diffused and ion-implanted resistors.
The model includes two resistive sections, with the body
to tub/substrate distributed over three capacitances in a way
that models distributed behavior well over the widest possible
frequency range.
ACKNOWLEDGMENT
The authors would like to thank G. Zaneski and R. Wister
for performing dc and ac measurements of integrated resistors.
Many useful ideas originated from discussions with K. Singhal, J. Morgan, D. Nelson, B. Meyer, P. Barnes, B. Morris,
and K. Lakshmikumar.
REFERENCES
[1] P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated
Circuits. New York: Wiley, 1977.
[2] G. Krieger and P. Niles, “Diffused resistor characteristics at high
current density levels—Analysis and applications,” IEEE Trans. Electon
Devices, vol. 36, pp. 416–423, Feb. 1989.
[3] C. Auricchio, R. Bez, and A. Grossi, “Narrow width effects in CMOS
n(p)-well resistors,” in Proc. 1996 IEEE Int. Conf. Microelectronic Test
Structures, Mar. 1996, vol. 9, pp. 13–16.
[4] C. C. McAndrew, B. K. Bhattacharyya, and O. Wing, “A single-piece
C -continuous MOSFET model including subthreshold conduction,”
IEEE Electron Device Lett., vol. 12, pp. 565–567, Oct. 1991.
, “A C -continuous depletion capacitance model,” IEEE Trans.
[5]
Computer-Aided Design, vol. 12, pp. 825–828, June 1993.
[6] C. Jacoboni, C. Canali, G. Ottaviani, and A. A. Quaranta, “A review of
some charge transport properties of silicon,” Solid-State Electron., vol.
20, no. 2, pp. 77–89, Feb. 1977.
[7] J. F. White, Microwave Semiconductor Engineering. New York: Van
Nostrand, 1982.
[8] M. L. Gupta and A. B. Bhattacharya, “Single-section lumped models
for integrated circuit resistors,” Solid-State Electron., vol. 16, no. 12,
pp. 1506–1509, Dec. 1973.
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[9] Y. V. Rajput, “Modeling distributed RC lines for the transient analysis
of complex networks,” Int. J. Electron., vol. 36, no. 5, pp. 709–717,
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[10] J. M. Khoury and Y. P. Tsividis, “Analysis and compensation of highfrequency effects in integrated MOSFET-C continuous-time filters,”
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Richard V. H. Booth received the B.S. degree
in electrical engineering from the University of
Maryland, College Park, in 1980, and the M.S.
and Ph.D. degrees in electrical engineering from
Lehigh University, Bethlehem, PA, in 1983 and
1988, respectively.
While attending the University of Maryland, he
was an Engineering Intern at Harry Diamond Laboratories, Adelphi, MD. He was an Associate Engineer with Westinghouse Electric Corporation, Baltimore, MD, from 1980 to 1981, working on CMOS
analog and digital integrated circuit design and testing. He was with IMEC,
vzw, Leuven, Belgium, between 1989 and 1992, working on process and
device simulation for process optimization. He is now a Member of Technical
Staff at AT&T Bell Laboratories, Allentown, PA, working on compact models
for circuit simulation, and semiconductor device characterization.
Colin C. McAndrew (S’82–M’84–SM’90) received the B.E. degree in
electrical engineering from Monash University, Melbourne, Vic., Australia,
in 1978, and the M.A.Sc. and Ph.D. degrees in systems design engineering
from the University of Waterloo, Waterloo, Ont., Canada, in 1982 and 1984,
respectively.
Since 1995, he has been the Manager of the Statistical Modeling and
Characterization Laboratory at Motorola, Tempe, AZ. From 1987 to 1995,
he was a Member of Technical Staff at AT&T Bell Laboratories, Allentown,
PA. From 1978 to 1980 and 1984 to 1987, he was an Engineer at the Herman
Research Laboratory of the State Electricity Commission of Victoria.
Dr. McAndrew was awarded the Ian Langlands Medal of the I.E. Australia
for 1978.