IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 8, AUGUST 2005
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A New Poly-Si TG-TFT With Diminished
Pseudosubthreshold Region: Theoretical
Investigation and Analysis
Ali A. Orouji, Member, IEEE, and M. Jagadesh Kumar, Senior Member, IEEE
Abstract—In this paper, we have proposed a new poly-Si triplegate thin-film transistor (TG-TFT) where the front gate consists of
two materials and three sections in order to reduce the OFF state
leakage current without affecting the ON state voltage. We have
used one and three grain-boundaries in the channel for analyzing
the electrical characteristics of the poly-Si TG-TFT. The key idea
in this paper is to make the dominant conduction mechanism in
the channel to be controlled by the accumulation charge density
modulation by the gate and not by the gate-induced grain barrier
lowering. As a result, we demonstrate that the TG-TFT exhibits a
highly diminished pseudosubthreshold region resulting in a substantial OFF state leakage current without any significant change
in the ON voltage when compared to a conventional poly-Si TFT
(C-TFT). Using two-dimensional and two-carrier device simulation, we have examined various design issues of the TG-TFT and
provided the reasons for the improved performance.
Index Terms—Grain boundary, leakage current, polysilicon,
pseudosubthreshold, thin-film transistor (TFT), traps, two-dimensional (2-D) simulation.
I. INTRODUCTION
P
OLY-SILICON thin-film transistors (TFTs) have been
studied extensively in recent years for their application in
flat panel active-matrix liquid crystal displays (AMLCD) [1],
[2]. For these applications, scaled-down poly-Si TFTs with
high performance and high reliability are required [3]. One of
the problems of poly-Si TFTs is the large OFF-state leakage
current due to the presence of the grain boundaries in the
channel [4] resulting in poor switching characteristics. Various
solutions such as the offset gate, the p-n-p gate, and the lightly
doped drain (LDD) poly-Si TFT structures have been proposed
to reduce the OFF-state leakage currents [5]–[8].
In keeping with the general trends of the CMOS technology,
the channel lengths of the poly-Si TFTs are now aggressively
scaled down to submicrometer lengths [9], [10]. Also, by scaling
the channel of the device down to a length comparable to the
poly-Si grain size, using modern metal-induced lateral crystallization or excimer laser annealed methods to control the grain
growth, it is possible to create devices where only a single or
small number of discrete grain boundaries exist in the channel
of the poly-Si TFT [11], [12]. This ability to control the grain
Manuscript received January 14, 2005; revised May 16, 2005. The review of
this paper was arranged by Editor C.-Y. Lu.
A. A. Orouji is with Semnan University, Semnan, Iran.
M. J. Kumar is with the Department of Electrical Engineering, Indian Institute
of Technology, Delhi 110 016, India (e-mail: mamidala@ieee.org).
Digital Object Identifier 10.1109/TED.2005.852169
Fig. 1. Typical transfer characteristic of a conventional poly-Si TFT operated
in linear region [18].
size to form the well-arranged grains in the channel has resulted
in high performance polysilicon TFTs [13]–[15] typically with
one or fewer grain boundaries in the channel [11], [15]. However, the OFF-state leakage currents in these advanced poly-Si
TFTs are orders of magnitude larger than those observed in conventional single-crystal silicon-on-insulator (SOI) MOSFETs.
The conventional SOI MOSFET exhibits a steep subthreshold
slope and a clear turn-on region in its transfer characteristic.
The dominant conduction mechanism is due to the inversion
charge density modulated by the gate [16]. On the other hand,
there are two regions in the transfer characteristic of a poly-Si
TFT as shown in Fig. 1. The region below threshold condiis called the subthreshold region and the region betion
tween
and the turn-on condition
is called the pseudosubthreshold region. Unlike in the case of SOI MOSFETs,
curve is very sharp and quickly
in which the
becomes linear, in the case of poly-TFTs, the transition from
the exponential to the linear region is much more gradual [17],
[18]. The dominant conduction mechanism below the turn-on
is due to the gate-induced grain barrier lowering
region
(GIGBL) and is not controlled by the accumulation charge density modulation by the gate (ACMG) [17]. The challenge that we
have addressed in this paper, therefore, is to examine if we can
convert the dominant conduction mechanism in a poly-Si TFT
with fewer grain boundaries, from GIGBL to ACMG so that
the pseudosubthreshold region is significantly diminished in the
transfer characteristic. In this paper, therefore, we have considered only one and three grain boundaries in the channel of the
poly-Si TFT [11]–[15]. If we succeed in realizing a diminished
pseudosubthreshold region, the poly-Si TFT should behave almost like the conventional single-crystal SOI MOSFET with a
steep subthreshold slope resulting in a significant reduction in
the OFF state leakage current.
0018-9383/$20.00 © 2005 IEEE
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Fig. 2.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 8, AUGUST 2005
Cross-sectional view of the TG-TFT.
Based on the above idea, the aim of this paper is therefore to
propose for the first time, a new device structure called the triple
gate poly-Si TFT (TG-TFT) in which the front gate consists of
two side gates on both sides of the main gate. The work function
of the side gates is different from that of the main gate resulting
in a modified channel potential. Using two-dimensional (2-D)
simulation [19], we demonstrate that this leads to a highly diminished pseudosubthreshold region in the transfer characteristics of the TG-TFT resulting in a significantly reduced OFF
state leakage current compared to the conventional poly-Si TFT
(C-TFT). The effects of varying the side gate parameters, trap
density at the grain boundaries, number of grain boundaries in
the channel and temperature of the device are investigated. Our
results demonstrate that the proposed TG-TFT exhibits significantly reduced leakage current thus making it a more reliable device configuration than the C-TFT for high-performance poly-Si
TFT circuit applications.
II. TG-TFT STRUCTURE
A schematic cross-sectional view of the TG-TFT implemented in the 2-D device simulator MEDICI is shown in
Fig. 2. The gate region consists of p -poly and n -poly for the
side gates and the main gate, respectively. The channel of the
device is undoped poly-Si with a single grain boundary (GB)
in the center. The regions on both sides of GB are assumed
to be completely defect-free meaning all the defect states are
localized in the GB. The capture and emission processes are
handled by the simulator using Shockley–Read–Hall recombination model and a conventional drift-diffusion method is
used to model the carrier transport. Also, we have employed
the Caughey–Thomas model [20] for the mobility based on the
work of Kitahara et al. [21].
The doping in the n source/drain regions is kept at
cm . The effective trapping density at the grain boundary is
cm and the trap energy relative to the
taken to be
conduction and valence bands are 0.51 eV and 0.51 eV for electron and hole traps, respectively. The capture rate for electrons
cm /sec [9]. It
and holes are identical and equal to
is assumed that the trap density of the acceptor-like states and
donor-like states are identical. The donor-like state is defined as
a trap state that is positively charged when holes are captured
and the acceptor-like state is negatively charged when electrons
are captured. The width of the GB (i.e., distance between the two
grains) is 10 nm [22]. The silicon thin film and the gate oxide
thicknesses are 50 and 10 nm, respectively. The main gate and
and ) are identical and the channel
the side gate lengths (
Fig. 3. Conduction band potential distribution for (a) C-TFT (V
= 0 V),
(b) TG-TFT (V = 0 V), and (c) TG-TFT (V = 0:52 V) with V = 0 V.
length
is kept constant at 0.4 m in our simulations. The work functions of the p -poly and the n -poly gates
are chosen as 5.25 and 4.17 eV, respectively. All the device parameters of the TG-TFT are equivalent to those of the C-TFT
unless mentioned. A similar simulation approach has been used
by Walker et al. [9] to prove the validity of their model. The
polarity between source and drain in poly-Si TFTs in AMLCD
applications is required to be altered to reduce the dc stress of
liquid crystals [23]. Therefore, for such applications it is advantageous to have a symmetrical poly-Si TFT structure by having
identical side gates on both sides of the main gate as suggested
in the proposed TG-TFT.
III. SIMULATION RESULTS AND DISCUSSION
A. Modifying Channel Potential Distribution
The key idea behind the TG-TFT operation is to modify the
channel potential so that the channel conduction is controlled
by the accumulation charge density modulation by the gate
(ACMG) and not by GIGBL. A typical MEDICI simulated 2-D
conduction band potential distribution for TG-TFT and C-TFT
V is shown
structures for the drain to source voltage
in Fig. 3. It can be seen from Fig. 3(a) that a potential barrier
(central barrier) is formed at the GB because the carriers are
immobilized by the traps due to the strain and the dangling
bonds located at the grain boundary [24], [25]. Therefore, the
dominant conduction mechanism of the C-TFT is determined
by GIGBL. But, in the proposed TG-TFT due to its triple-gate
structure, in addition to the central barrier, two extra barriers
(side barriers) are created in the side gate regions due to the
OROUJI AND KUMAR: POLY-Si TG-TFT WITH DIMINISHED PSEUDOSUBTHRESHOLD REGION
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Fig. 4. Comparison of the transfer characteristics of TG-TFT, C-TFT, and
C-SOI structures.
Fig. 5. Transfer characteristic of TG-TFT structure for different work
functions of side gates.
work function difference between the side gate and the main
gate as shown in Fig. 3(b) in which the side and central barriers
not only differ in their height but also in their shape. Therefore,
the dominant conduction mechanism of the TG-TFT should
now be controlled by the side barriers since the central barrier
does not play any significant role. In that case, we should have
a steep subthreshold slope in the transfer characteristic of the
device just as observed in a typical single crystal SOI MOSFET.
With increasing gate voltage, however, the height of the side
,
barrier will decrease and at some critical gate voltage
the side barrier height will become equal to the central barrier
V. After this
height as shown in Fig. 3(c) for
condition is reached, the channel
critical gate voltage
conduction mechanism will be determined by GIGBL.
hence the reduction in the OFF-state leakage current. If the critis near to zero or negative, the TG-TFT
ical gate voltage
structure is not very useful in improving leakage current and will
behave like the C-TFT. An important parameter that determines
is the work function of the side gate
.
the value of
Fig. 5 shows the transfer characteristic of the TG-TFT for different work functions of the side gate region. It can be seen from
the figure that as the work function of the side gate decreases,
will reduce forcing the behavior
the critical gate voltage
of TG-TFT approach that of the C-TFT. This is because if the
work function of the side gate decreases for a given work function of the main gate, the height of the side barriers will also
decrease. Therefore, it is very important to choose appropriate
work function for the side gate for given main gate work func.
tion
B. Diminished Pseudo-Subthreshold Region
D. Effect of Channel Length
In Fig. 4, the transfer characteristics of the TG-TFT are
compared with that of the C-TFT and the single crystal SOI
MOSFET. We notice from this figure that as speculated above,
for all gate voltages less than the critical gate voltage
(
V), the subthreshold slope of the TG-TFT is very steep
similar to that commonly observed in SOI MOSFETs. For gate
, the transfer characteristic of the
voltages greater than
TG-TFT matches with that of the C-TFT since now the height
of the central barrier is larger than that of the side barriers.
Therefore, it is clear that because of the steep subtrheshold
slope, the TG-TFT will have several orders of magnitude lesser
OFF-state leakage current when compared to the C-TFT. This
has become possible by nullifying the effect of the central
barrier associated with the grain boundary on the channel
conduction mechanism so that the pseudosubthreshold region
is almost eliminated.
Fig. 6 shows the transfer characteristics of the TG-TFT compared with that of the C-TFT for channel lengths ranging from
0.3 to 1.0 m. Just as is commonly observed in the case of the
single crystal SOI-MOSFET [16], the slope of the subthreshold
region will improve as the channel length increases. What is important to note is that there is no significant change in the critwith increase in the channel length because
ical voltage
the interaction between side and central barriers will reduce as
the channel length increases. However, it is important to note
that the short channel effects in the TG-TFT structure need to
be investigated further to understand how the improvement will
hold good for shorter channel versions of TG-TFT.
C. Effect of Side Gate Work Function on
The value of critical gate voltage
at which the central barrier height becomes equal to the side barrier height is
very important in controlling the pseudosubthreshold region and
E. Effect of Trap Density
The conductivity in polycrystalline TFT is strongly dependent on the trap density at the GBs and has been described by
many authors [24]–[27]. Fig. 7 shows the transfer characteristics of TG-TFT and C-TFT structures for different trap densities. It can be seen from the figure that the pseudosubthreshold
region will be more gradual with increasing trap density at the
will increase. However, the subthreshold slope of
GB and
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 8, AUGUST 2005
Fig. 6. Transfer characteristics of TG-TFT and C-TFT for different channel
lengths.
Fig. 8. Transfer characteristics of TG-TFT and C-TFT for different
temperatures.
Fig. 7. Transfer characteristics of TG-TFT and C-TFT for different grain
boundary trap densities.
Fig. 9. Transfer characteristics of TG-TFT for different side gate lengths. L
and L are the main and side gate lengths, respectively.
the TG-TFT remains unchanged giving rise to a substantial reduction in the OFF-state current even if the trap density is large.
F. Effect of Temperature
One of the important concerns in the operation of poly-Si
TFTs is the temperature dependence of their performance. Due
to the gradual subthreshold slope, the C-TFTs show stronger
temperature dependence compared to the conventional SOI
MOSFETs. Fig. 8 shows the temperature dependence of the
TG-TFT and the C-TFT structures. We notice that even at 400
K, the OFF-state current of the TG-TFT is much smaller and the
subthreshold slope is steeper than that of the C-TFT. This is an
important advantage of the TG-TFT over that of the C-TFT at
higher ambient temperatures.
It is worth noting that in a real device it is difficult to control the position of the GB relative to the source and drain and
therefore the position dependence of the GB in the channel is
very important in conventional poly-Si TFTs. However, our simulation results suggest that there is no significant change in the
transfer characteristic of TG-TFT even if there is a 20% shift in
the position of the GB with respect to the center of the channel.
IV. DESIGN ISSUES OF TG-TFT
A. Choice of Side Gate Length
In all our simulations above, we have chosen the main gate
length
equal to the side gate length
as proposed by
Kumar et al. for the dual material gate SOI MOSFET [28]–[31].
They showed that if the side gate length is equal to the main gate
length, the OFF-state leakage current is very small. To examine
the effect of the side gate length on the leakage current, we have
compared the transfer characteristic of the TG-TFT for different
side gate lengths as shown in Fig. 9. As can be seen from the
figure, there is no significant change in the critical gate voltage
when the side gate length is reduced with respect to the
OROUJI AND KUMAR: POLY-Si TG-TFT WITH DIMINISHED PSEUDOSUBTHRESHOLD REGION
Fig. 10. Transfer characteristics of TG-TFT and C-TFT for three grain
boundaries in the channel with all three grain boundaries present under the
main gate.
main gate length. However, we conclude that the subthreshold
slope is steeper and the leakage current is the lowest when the
side gate length is equal to the main gate length for the fixed
channel length.
B. Effect of Multiple Grain Boundaries
To examine the behavior of the TG-TFT in the presence of
multiple grains in the channel, we have investigated the performance of the TG-TFT structure with three GBs in the channel.
Fig. 10 shows a comparison of the transfer characteristic of the
TG-TFT with the C-TFT with three GBs present in the main
channel and for different distances between these grains. Three
conclusions can be drawn from the figure. First, the TG-TFT
structure works very well even in the presence of multiple grain
boundaries in the channel. Second, when the distance between
the GBs is large, due to an increase in the interaction between
the side barriers and the trap barriers, the slope of transfer characteristic of the TG-TFT will increase. However, even in this
case, the transfer characteristic of the TG-TFT is significantly
better than that of the C-TFT. Third, in the presence of multiple
GBs in the channel, the pseudosubthreshold slope in the C-TFT
further deteriorates.
and
values, if the distance between
For the chosen
grain boundaries further increases, it is quite possible that GBs
may appear under the side gates as shown in Fig. 11. Even in
and
this case, we observe that by choosing appropriate
values, we can still realize diminished pseudosubthreshold region in the TG-TFT making its subthreshold slope very steep as
can be seen from the transfer characteristic shown in Fig. 11.
V. CONCLUSION
To reduce the leakage current and for improving the performance of poly-Si TFT in AMLCD or other applications, we
have proposed a novel poly-Si TG-TFT. In this structure, two
side gates on either side of the main gate whose work functions are different from the main gate are used so that the dominant conduction mechanism in the channel is controlled by the
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Fig. 11. Transfer characteristics of TG-TFT and C-TFT for three grain
boundaries in the channel with one grain boundary present under each side
gate.
ACMG and not by the GIGBL. The performance of the proposed TG-TFT has been evaluated using 2-D simulation and
compared with that of a conventional poly-Si TFT. Based on
our simulation results, we demonstrate that due to the presence
of side barriers which are more dominant than the central potential barrier associated with the grain boundaries, the pseudosubthreshold region is significantly diminished resulting in
several orders of magnitude reduction in the OFF state leakage
current with no detectable change in the ON voltage. We have
also studied the different aspects of the device design such as
the effect of varying the channel length, number of grain boundaries, trap density at the grain boundaries, temperature and the
work function of the gate material, and the reasons for the improved performance are presented. The significantly reduced
leakage current in the TG-TFT due to the diminished pseudosubthreshold region is expected to provide the incentive for experimental verification.
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Ali A. Orouji (M’05) was born in Neyshabour, Iran,
in 1966. He received the B.S. and M.S. degrees in
electronic engineering from the Iran University of
Science and Technology (IUST), Tehran, Iran. He is
currently pursuing the Ph.D. degree in the Department of Electrical Engineering, Indian Institute of
Technology, Delhi, India.
Since 1992, he has been working at the Semnan
University, Semnan, Iran as a faculty member. His
research interests are in modeling of SOI MOSFET,
novel device structures, and analog integrated circuits
design.
M. Jagadesh Kumar (SM’99) was born in Mamidala, Andhra Pradesh, India. He received the M.S.
and Ph.D degrees in electrical engineering from the
Indian Institute of Technology (IIT), Madras, India.
From 1991 to 1994, he did his post-doctoral
research in modeling and processing of high-speed
bipolar transistors in the Department of Electrical
and Computer Engineering, University of Waterloo,
Waterloo, ON, Canada. While with the University of
Waterloo, he also did research on amorphous silicon
TFTs. From July 1994 to December 1995, he was
initially with the Department of Electronics and Electrical Communication Engineering, IIT, Kharagpur, India, and then joined the Department of Electrical
Engineering, IIT, Delhi, India, where he became an Associate Professor in July
1997 and a Professor in January 2005. His research interests are in VLSI device
modeling and simulation for nanoscale applications, IC technology, and power
semiconductor devices. He has been a Reviewer for the IEE Proceedings on
Circuits, Devices and Systems, IEE Electronics Letters, and IEE Solid-State
Electronics. His teaching has often been rated as outstanding by the Faculty
Appraisal Committee, IIT, Delhi.
Dr. Kumar is a Fellow of the Institute of Electronics and Telecommunication
Engineers (IETE) of India. He has been a Reviewer for the IEEE TRANSACTIONS
ON ELECTRON DEVICES. He was Chairman, Fellowship Committee, The 16th
International Conference on VLSI Design, New Delhi, India, in 2003. He is
Chairman of the Technical Committee for High Frequency Devices, International Workshop on the Physics of Semiconductor Devices, New Delhi, India,
2005.