Application note
--LV4924VH--
Application note
Schematics
--LV4924VH--
ON Semiconductor
Version: 2.02E
1/29
Application note
--LV4924VH--
Contents
■
Specifications ...................................................................................................... 3
Maximum Ratings ........................................................................................ 3
Operating Conditions ................................................................................... 3
Electrical Characteristics ............................................................................. 4
■
Pin Equivalent Circuit .......................................................................................... 5
■
Pin layout ............................................................................................................ 8
■
Block Diagram and Application Circuit ................................................................. 9
Application (RL=8ohm) ............................................................................... 9
Application (RL=6ohm) ............................................................................. 10
Application (RL=4ohm) ............................................................................. 11
■
Pin Function ...................................................................................................... 12
■
Operation Mode Summary ................................................................................. 13
STBY mode ................................................................................................ 13
MUTE mode................................................................................................ 13
Operation mode ......................................................................................... 13
■
Sequences ......................................................................................................... 14
ON sequence ............................................................................................. 14
OFF sequence ............................................................................................ 14
■
Variable Protection Circuits ............................................................................... 15
Supply voltage drop protection circuit ....................................................... 15
Over current protection circuit ................................................................... 16
Thermal protection circuit.......................................................................... 17
Output offset detection protection circuit .................................................. 18
■
MPG(Minimum Pulse Generator)Function .......................................................... 19
■
LV4924VH bread board rev.1.0 using parts ........................................................ 20
■
Parts selection................................................................................................... 21
High frequency noise rejection capacitors .................................................. 21
Output filter............................................................................................... 21
Output inductor ......................................................................................... 21
■
PCB layout ......................................................................................................... 22
Each Terminal Application.......................................................................... 22
Parts layout (Output side) ......................................................................... 25
2 layer PCB layout ..................................................................................... 26
■
Package ............................................................................................................ 27
Mounting Pad Sketch ................................................................................. 28
■
Speaker Cable ................................................................................................... 29
2/29
Application note
--LV4924VH--
■ Specifications
Maximum Ratings
Ta=25C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Maximum supply
voltage
VD
Externally applied voltage
---
---
22
V
Maximum PWM pin
voltage
VIN
PWM_A1,PWM_A2,PWM_B1,PWM_B2
---
---
6
V
Maximum pull-up pin Vpup
voltage
max
NPN Open collector pin
---
---
20
V
Allowable power
dissipation
Pd max
Our substrate, with mounting on the
backside *1
---
---
4.6
W
Maximum junction
temperature
Tj max
---
---
150
C
Operating
temperature
Topr
-25
---
75
C
Storage temperature
Tstg
-50
---
150
C
* PCB size: 90mm×70mm×1.6mm, Material: 2-layer glass epoxy printed circuit board
Back surface copper foil: 90% of the circuit board area, with 21 through holes in the IC exposed Die-Pad area for connection to the layers.
Pdmax - Ta
6
Pdmax [W]
5
4
Exposed Die-Pad
Soldered
4.6
Exposed Die-Pad
Not Soldered
3.2
2.7
3
1.9
2
1
0
-25
0
25
50
75
100
Ta [°C]
Operating Conditions
Ta=25C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Recommended
VD
supply voltage range
Externally applied voltage
9
13
20
V
Recommended PWM
pin voltage
VIN
PWM_A1,PWM_A2,PWM_B1,PWM_B2
0
3.3
5
V
Recommended
pull-up supply
voltage
Vpup
NPN Open collector pin
18
V
Recommended load
resistance
RL
Speaker load
3/29
---
--4
8
---

Application note
--LV4924VH--
Electrical Characteristics
VD=13V, RL=8Ω, L=22μH(TOKO:A7040HN-220M), C=0.33μF(Matsuo:553M6302-334K), Ta=25C
Parameter
Symbol
Conditions
__________________
Quiescent current
ICCO
Imute
Typ.
Max.
Unit
__________________
STBY=H, MUTE=H,
fIN=384kHz, Duty=50%
30
38
45
mA
2
4
6
mA
---
10
μA
2.3
---
5.5
V
0
---
1.0
V
---
60
μA
__________________
__________________
Current at MUTE
Min.
STBY=H, MUTE=L,
VIN=GND
__________________
__________________
STBY=L, MUTE=L,
VIN=GND
PWM_A, PWM_B,
---
Standby current
Ist
H input voltage
VIH
__________________
L input voltage
VIL
__________________
H input current
IIH
VIN=5V
L input current
IIL
VIN=GND
Output pin leakage
current
IOFF
NPN Open collector output
OFF-stage 5.0V pull-up
Output pin current
IOL
NPN Open collector output
ON-stage, VOL=0.4V
*2
Rds ON
Id=1A
---
220
Turn ON delay time
td ON
fIN=384kHz, Duty=50%
---
30
50
ns
Turn OFF delay time
td OFF
fIN=384kHz, Duty=50%
---
30
50
ns
Rise-up time
tr
fIN=384kHz, Duty=50%
---
5
20
ns
Fall time
tf
fIN=384kHz, Duty=50%
---
5
20
ns
Power Tr. ON resistance
__________________
S T B Y , MUTE
PWM_A, PWM_B,
__________________
S T B Y , MUTE
---20
--0.5
---
---
---
μA
1
---
μA
---
mA
---
mΩ
*2: For the Power Tr ON resistance (RdsON), the design guarantee value is maximum 270 m
The table below shows the reference value when FPGA equivalent to the reference model is used.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Output 1
PO1
THD+N＝10%,
fIN=1kHz, AES17
---
10
---
W
Output 2
PO2
VD=16V, THD+N＝10%
fIN=1kHz, AES17
---
15
---
W
Total harmonic
distortion
THD+N
PO=1W,
fIN =1kHz, AES17
---
0.1
---
%
Note: Characteristics indicate values obtained under our measuring environment and may vary depending
on the pattern layout, parts used, etc.
4/29
Application note
--LV4924VH--
■ Pin Equivalent Circuit
Pin
No
Pin symbol
I/O
Description of functions
Equivalent circuit diagram
150kΩ
PVD
STBYB
I
Standby mode control
1
10kΩ
100kΩ
1
GND
VDDA
50kΩ
PVD
2
MUTEB
I
Muting control
2
10kΩ
GND
PVD
3
SOSB
O
Internal protection circuit
detection output (OR output of
the thermal detection,
over-current, voltage drop
protection, offset detection
circuit) of an NPN open collector
output type
500Ω
GND
NC1
NC2
NC3
NC4
―
―
―
―
Non
Non
Non
Non
connection
connection
connection
connection
8
PWM_A1
I
PWM input (plus input) of
OUT_CH1_P
9
PWM_B1
I
PWM input (negative input) of
OUT_CH1_N
100kΩ
100kΩ
4
5
6
7
5/29
3
Application note
Pin
No
FIN
GND
―
ground
10
PWM_B2
I
PWM input (negative input) of
OUT_CH2_N
11
PWM_A2
I
PWM input (plus input) of
OUT_CH2_P
12
13
14
15
16
17
18
19
20
NC5
NC6
NC7
NC8
NC9
NC10
NC11
PVD2
PVD2
―
―
―
―
―
―
―
―
―
Non connection
Non connection
Non connection
Non connection
Non connection
Non connection
Non connection
Power pin
Power pin
21
OUT_CH2_P
O
Output pin, Channel 2 plus
22
OUT_CH2_P
O
Output pin, Channel 2 plus
23
BOOT_CH2_P
I/O
Pin
No
Pin symbol
I/O
I/O
Description of functions
Equivalent circuit diagram
100kΩ
100kΩ
Pin symbol
--LV4924VH--
Bootstrap I / O pin,
channel 2 plus
Description of functions
6/29
Equivalent circuit diagram
Application note
25
BOOT_CH2_N
I/O
--LV4924VH--
Bootstrap I / O pin,
channel 2 minus
PVD
26
OUT_CH2_N
O
Output pin, Channel 2 minus
26
GND
PVD
27
OUT2_CH_N
O
Output pin, Channel 2 minus
27
GND
FIN
GND
―
ground
PVD
28
OUT_CH1_N
O
Output pin, Channel 1 minus
28
GND
PVD
29
OUT_CH1_N
O
Output pin, Channel 1 minus
29
GND
30
BOOT_CH1_N
31
VDDA1
32
BOOT_CH1_P
I/O
O
I/O
Bootstrap I / O pin,
channel 1 minus
Internal power supply decoupling
capacitor connection
Bootstrap I / O pin,
channel 1 plus
7/29
5
6
NC3
27
11
8/29
12
13
14
15
16
17
18
NC5
NC6
NC7
NC8
NC9
NC10
NC11
PVD2
Power pin
Power pin
19
-
OUT_CH2_P
PVD1
PVD1
PVD2
35
36
20
Output pin, Channel 1 plus
21
O
OUT_CH2_P
OUT_CH1_P
22
34
VDDA2
Output pin, Channel 1 plus
BOOT_CH2_P
O
23
OUT_CH1_P
BOOT_CH2_N
33
Description of functions
24
I/O
OUT_CH2_N
Pin symbol
25
OUT_CH2_N
Pin
No
26
10
OUT_CH1_N
PWM_B2
OUT_CH1_N
28
GND
PWM_A2
BOOT_CH1_N
29
OUT_CH1_P
BOOT_CH1_P
33
32
30
OUT_CH1_P
34
VDDA1
PVD1
35
31
PVD1
36
GND
9
PWM_B1
8
4
NC1
NC2
7
3
SOS
NC4
2
PWM_A1
1
STBY
MUTE
Application note
--LV4924VH--
Equivalent circuit diagram
■ Pin layout
Application note
■ Block Diagram and Application Circuit
--LV4924VH--
Application (RL=8ohm)
Microcomputer
&
PWM Generator
――――――――――――――――――――――――――――――――――――――――――――――――
LV4924VH Application (RL=8ohm)
This application circuit is one of examples.
9/29
Application note
--LV4924VH--
Application (RL=6ohm)
Microcomputer
&
PWM Generator
――――――――――――――――――――――――――――――――――――――――――――――――
LV4924VH Application (RL=6ohm)
This application circuit is one of examples.
10/29
Application note
--LV4924VH--
Application (RL=4ohm)
Microcomputer
&
PWM Generator
――――――――――――――――――――――――――――――――――――――――――――――――
LV4924VH Application (RL=4ohm)
This application circuit is one of examples.
11/29
Application note
--LV4924VH--
■ Pin Function
Pin No
Pin name
I/O
Function explanation
1
STBYB
I
Standby control pin
2
MUTEB
I
Mute control pin
3
SOSB
O
Alarm monitor pin
4
NC
―
Non connection
5
NC
―
Non connection
6
NC
―
Non connection
7
NC
―
Non connection
8
PWM_A1
I
Input CH1 plus
9
PWM_B1
I
Input CH1 minus
FIN
GND
―
Ground
10
PWM_B2
I
Input CH2 minus
11
PWM_A2
I
Input CH2 plus
12
NC
―
Non connection
13
NC
―
Non connection
14
NC
―
Non connection
15
NC
―
Non connection
16
NC
―
Non connection
17
NC
―
Non connection
18
NC
―
Non connection
19
PVD2
―
Supply pin
20
PVD2
―
Supply pin
21
OUT_CH2_P
O
Output terminal , CH2 plus
22
OUT_CH2_P
O
Output terminal , CH2 plus
23
BOOT_CH2_P
I/O
24
VDDA2
O
25
BOOT_CH2_N
I/O
26
OUT_CH2_N
O
Output terminal , CH2 minus
27
OUT_CH2_N
O
Output terminal , CH2 minus
FIN
GND
―
Ground
28
OUT_CH1_N
O
Output terminal , CH1 minus
29
OUT_CH1_N
O
Output terminal , CH1 minus
30
BOOT_CH1_N
I/O
31
VDDA1
O
32
BOOT_CH1_P
I/O
33
OUT_CH1_P
O
Output terminal , CH1 plus
34
OUT_CH1_P
O
35
PVD1
―
Output terminal , CH1 plus
Supply pin
36
PVD1
―
Supply pin
Boot strap terminal , CH2 plus
Digital 5VDC pin
Boot strap terminal , CH2 minus
Boot strap terminal , CH1 minus
Digital 5VDC pin
Boot strap terminal , CH1 plus
12/29
Application note
--LV4924VH--
■ Operation Mode Summary
STBY mode
[STBYB = L, MUTEB = L]
Each bias becomes off state when the regulator in IC has been turned off.
The most of circuits becomes off state.
The supply current : 1uA (typ.)
MUTE mode
[STBYB= H, MUTEB= L]
Each bias becomes on state when the regulator in IC has been turned on.
When more than half of the circuits are active, the amplifier in the output stages become off.
The supply current : 4mA (typ.)
Operation mode
AD modulation
1V/DIV.
PWM_A1
1
PWM_B1
2
BD modulation
1V/DIV.
PWM_A1
1
PWM_B1
2
13/29
Application note
--LV4924VH--
■ Sequences
ON sequence
To reduce the pop noise, turn ON power supply while controlling in the following timing
(PWM=BD modulation).
In particular, all of inputs of PWM must be held at "L" at canceling of MUTE function.
OFF sequence
To reduce the pop noise, turn OFF power supply while controlling in the following timing
(PWM=BD modulation).
PVD
(Vpup)
Duty=50%
T5
>3ms
PWM Input
BD mode
(PWM_A1,2
PWM_B1,2)
STBY
VDDA
T6
>3ms
T7
>800μs
MUTE
SOS
Tj>150
SOS
PWM
Output
Vpup
SOS
Hi-z
Hi-z
14/29
Application note
--LV4924VH--
■ Variable Protection Circuits
Supply voltage drop protection circuit
To avoid unstable operation at low voltages, this circuit monitors the PVD pin voltage and turns
ON the amplifier when this voltage exceeds the Attack voltage (VD=7V typ.). In addition, to
avoid unstable operation when the PVD pin voltage has dropped because of certain reasons,
the Recover voltage (VD=6V typ.) is set. Both Attack and Recover voltages have the hysteresis
(about 1 V) to prevent continuous ON / OFF operation of the supply voltage drop protection
circuit.
Function image
Also, this IC is designed to turn off AMP in the same sequence that the MUTE is on as a pop
noise measures when the plug of products are put off.
In the demo board of our company, the above process can be executed by a charge retained
in the power supply capacitor of 470uF adds to the power supply line.
In the actual board, the power supply line is connected with other block, please note that it is
highly possible that the time constant of the falling edge is different.
15/29
Application note
--LV4924VH--
Over current protection circuit
This circuit is a protection circuit* to protect the output transistor from the over-current and
compatible with any mode of lightning, ground fault, and load short-circuit.
Protection is done when the detection current value (about 6A) set inside IC is reached, forcing
the output transistor to remain OFF for about 20μs. After forced OFF, the transistor returns
automatically to the normal operation and performs protection again if the over-current
continues to flow.
OUTPUT current
Protection Normal
operation operation
Internal current
Function image
IDETECT
output current
HOLD TIME
Internal control signal
Close up
* The over current protection circuit is a function to avoid the abnormal state like the output
short-circuit temporarily. Unfortunately, we cannot guarantee that IC is not destroyed.
16/29
Application note
--LV4924VH--
Thermal protection circuit
This circuit detects the temperature (150C or more) inside LSI for protection. While this
protection circuit is active, the output Tr is turned OFF on both high- and low-sides, putting the
output in the high-impedance state. This operation is also provided with the hysteresis.
Recovery
Attack
Hysterisis
temperature (Tj) rise
Internal
TSD DET.
Shut down
PWM
Internal
TSD DET.
temperature (Tj) fall
Shut down
PWM
40
50
60
70
80
90
100 110 110 130 110 150 160 170 180 190 200
Junction temperature T [
]
Function image
* The thermal protection circuit is a function to avoid the abnormal state temporarily.
Unfortunately, we cannot guarantee that IC is not destroyed.
17/29
Application note --LV4924VH-Output offset detection protection circuit
This circuit is a protection circuit intended to alleviate burn of the loudspeakers when DC
outputs to the BTL output for a certain period or more.
The circuit detects the case in which each BTL input of each channel continues to disagree (for
about 300 ms), turns OFF the output Tr. on both high- and low-sides, and puts the output in
the high-impedance state.
In addition, this system detect it when only one side of the differential PWM output of PWM
generator does continuation (more than 300msec.) and stopped.
The operation image is as follows.
100msec./Div.
PWM+
1
PWM2
DETECT
DETECT
MUTE
MUTE
INTERNAL
SIGNAL
OFFSET
DETECT
3
SOSB
4
300msec.
300msec.
BTL OUT
5
Disagreement of the differential PWM
100msec./Div.
PWM+
100msec./Div.
PWM+
1
1
PWM-
PWM2
2
DETECT
OFFSET
DETECT
DETECT
INTERNAL
SIGNAL
3
DETECT
DETECT
MUTE
MUTE
INTERNAL
SIGNAL
OFFSET
DETECT
3
SOSB
MUTE
4
SOSB
MUTE
4
300msec.
BTL OUT
300msec.
BTL OUT
5
300msec.
5
300msec.
The differential PWM stopped only one side. ”L”
18/29
The differential PWM stopped only one side. “H”
Application note
■ MPG (Minimum Pulse Generator) Function
--LV4924VH--
The PWM signal now reaches the minimum pulse circuit, which ensures that the minimum
pulse length will not exceed 75ns typically. If a pulse occurs with less duration than 75ns, the
pulse will be prolonged to 75ns.
In addition, this function cannot remove setting because IC protection is a purpose.
Internal block diagram
200usec./DIV.
Positive short pulse
High frequency
IN
Negative short pulse
MP
MP
MP
OUT
Operation image figure
19/29
MP
MP
MP
MP
Application note
■ LV4924VH bread board rev.1.0 using parts
Parts No.
--LV4924VH--
PWM-IN
Maker
―
Type
―
Note
Input connector
C1,C2,C3,C4
muRata
GRM21BR71H105K
High frequency rejection for PVD
C5,C6,C7,C8
muRata
GRM21BR71H104K
Boot strap capacitor
C9,C10
muRata
GRM21BR71H105K
Decoupling capacitor for VDD
L1,L2,L3,L4
TOKO
A7040HN-220M
Output inductor
C11,C12,C13,C14
Matsuo
553M6302-334K
Output capacitor
C17
nichicon
UKW1E471MPD
Decoupling capacitor for PVD
R1
MCR10_1002
―
SOS Pull-up resistor
D1
Rohm
―
SOS LED for monitor
SW1
nikkai
A-12HP
Switch for STBY
SW2
nikkai
A-12HP
Switch for MUTE
Board image
20/29
Application note
--LV4924VH--
■ Parts selection
High frequency noise rejection capacitors
The high frequency noise rejection capacitors in this application note need to select the low
ESR and the low ESL type. The high frequency noise rejection capacitors are one of the most
important parts in the D-class application.
Especially between PVD and GND capacitor has to select the low ESR and the low ESL type.
Capacitor equivalent circuit
There is no perfect capacitor. ESR value will decide performance of attenuation and not only
the capacitance value. L value will affect max operating frequency for the capacitor.
The impedance of a capacitor is: XC= 1 / (2*π*f *C). The low ESR capacitor reduces the heat
consumption.
Output filter
The output filter attenuates the switching frequency of a Class-D amplifier.
The cut off frequency of the output LC filter need to be selected no fewer than the internal
oscillator frequencies, nor more than 20kHz.
In this application note, the cut off frequency introduces an example with about 30kHz.
Output inductor
The output inductor influences the Audio performance. The current rating of the inductor has
to be equal to or larger than the maximum output current of a Class-D amplifier. The inductor
must not be saturated. If the inductor saturates the inductance will decrease and the output
ripple will increase.
The characteristic found to an inductor is as follows
√
Superposition characteristics of DC current
√
Audio distortion
√
Efficiency
√
EMI performance
21/29
Application note
--LV4924VH--
■ PCB layout
Each Terminal Application
◊
STBYB terminal and MUTEB terminal (STBYB and MUTEB)
5VDC
5VDC
STBYB
MUTEB
Control
AGND
AGND
AGND
* Please control the control terminal by a microcomputer
(Commonly-used circuit example in dashed line should be used only as a guide.)
◊
SOSB terminal(SOSB)
The power supply line of the microcomputer can
monitor an abnormal state by making pulling up.
Micom
VDD
To Micom
◊
SOSB
Input terminal (PWM_A1, PWM_B1, PWM_A2, PWM_B2)
Straight&short
FROM SOC
PWM_A1
PWM_B1
PWM_B2
PWM_A2
To prevent the influence of noise,
please layout this line as short as possible
* To maintain a high common-mode rejection ratio, it is necessary to set the layout of this line
as same as possible with the input pin plus.
22/29
Application note
◊
--LV4924VH--
Power supply terminal (PVD1 and PVD2)
Capacitors for high-frequency rejection must
be inserted, as close as possible to IC.
13VDC
PVD1
PVD2
0.1uF
1uF
470uF
A power supply capacitor must be inserted at the
midpoint of both channels.This capacitor is able
to split(220uF×2).
(Commonly-used circuit example in dashed line should be used only as a guide.)
◊
Output terminal(OUT_CH1_P, OUT_CH1_N, OUT_CH2_P, OUT_CH2_N)
We recommend a coil for digital amplifier
that is released by each coil manufacturer.
OUT_CH1_P
OUT_CH1_N
OUT_CH2_P
OUT_CH2_N
◊
To SPK
22μH
0.33μF
Boot terminal(BOOT_CH1_P, BOOT_CH1_N, BOOT_CH2_P, BOOT_CH2_N)
BOOT_CH1_P
BOOT_CH1_N
Boot capacitors must be inserted,
as close as possible to IC.
The high-frequency current loop
is reduced by this measure.
BOOT_CH2_P
BOOT_CH2_N
0.1μF
OUT
* Please reconfirm the pop noise when the capacity value is varied.
23/29
Application note
◊
--LV4924VH--
VDD terminal(VDDA1, VDDA2)
The VDD capacitors must be inserted,
as close as possible to IC.
The high-frequency current loop is
reduced by this measure.
VDDA1
VDDA2
◊
1μF
GND terminal(GND)
For the design of GND line, please refer
to “ About PCB Layout”.
◊
NC terminal (14pin~22pin)
Both sides of the input line become the GND line when these pins are connected with AGND.
Therefore, it is effective in reduction of noise
24/29
Application note
--LV4924VH--
Parts layout (Output side)
Generally D-class amplifier has the high switching frequency. Therefore Radiation-field
immunity measures are very important. All parts for high-frequency noise rejection must be
inserted, as close as possible to IC.
Layout image figure
The capacitor of high-frequency rejection for PVD is one of the most important parts in all
components. Please do not perform variable of the value for prevention of malfunction
In order to achieve good ripple damping it is necessary to keep the ESR value of the capacitor
as low as possible. Examples of suitable types of capacitor for this filter application are ceramic
capacitors.
* Small surface-mount capacitors can be located as close as possible to the D-class amplifier.
The switching current flows through the print pattern on PCB. When this current flows over a
long print pattern of the wiring length, a surge occurs by wiring inductance. A short pattern
can hold a surge in check small.
When you cannot do it in an ideal layout, overshoot and under shoot grows big than our
evaluation board. We recommend that we make rand to be able to add SBD beforehand.
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Application note
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2 layer PCB layout
PCB Layout Recommend Image Figure (surface)
PCB Layout Recommend Image Figure (reverse side)
* To lower GND impedance, GND of the upper side and reverse side must be connected at the
through hole as much as possible.
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Application note
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(3.5)
(1.5)
1.7max
0.5
7.6
5.6
■ Package
Package Outline [ HSSOP36(275mil)]
The exposed Die-Pad is not the NC terminal. Since these are electrically connected, please
make sure to connect with GND. This package has the highest temperature of exposed Die-Pad.
When the area of GND that is wired with the exposed Die-Pad is increased as much as possible,
the maximum effect of radiation is achieved. The FIN is similar, too.
Also, largely-ensured the area of GND makes a shielding effectiveness and an unnecessary
radiation noise is reduced.
* To reduce unnecessary radiation noise, the circumferentially-arranged parts must be
mounted on the surface side, as much as possible.
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Application note
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eE
l1
Mounting Pad Sketch
Caution : Dimensions are reference values, and there is not it with the guarantee value.
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Application note
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■ Speaker Cable
The level of unnecessary radiation noise is improved by the following order.
case1→ case2 → case3 → case4
Please select the speaker cable according to the set that you would like to use.
Case1
Case2
Case3
Case4
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