European Patent Office
© Publication number:
Office europeen des brevets
©
EUROPEAN
0
087
707
A2
PATENT
APPLICATION
©Int. CI.3: H 03
© Application number. 83101627.4
K 5/13
© Date of filing: 21.02.83
© Priority: 26.02.82 US 352671
© Applicant: Hewlett-Packard Company
Mail Stop 20 B-0 3000 Hanover Street
Palo Alto California 94304IUS)
© Date of publication of application:
07.09.83 Bulletin 83/36
© Inventor: Hardage, Phillip Kent
10 Sandra Lane
Manitou Springs Colorado 80829(US)
© Designated Contracting States:
DE FR GB
© Inventor: Peurifoy, Stephen W.
3115 East Uintah Street
Colorado Springs Colorado 80909(US)
© Representative: Schulte, Knud, Dipl.-lng.
c/o Hewlett-Packard GmbH Europ. Patent- und
Lizenzabteilung Postfach 1430 Herrenberger Strasse 130
D-7030 Bdblingen(DE)
© Pulse delay circuit.
A
(57) A pulse delay circuit uses a cascaded series of inverting
elements with input thresholds to delay the transitions of an
input pulse as it progresses through the series. The output of
each inverter charges a capacitance in one polarity, but
cannot discharge it. The discharge is achieved by current
sources connected to the capacitors, charging them in a
direction opposite to that of the inverter outputs. This
produces a ramp which subsequently produces an abrupt
transition aslhe
as/he ramp eventually crosses the input threshold.
In this way every other inverter delays the leading edge,
while the alternate intervening inverters delay the trailing
edge. A final capacitance-tolerant inverting element with a
threshold produces abrupt transitions for each transition as
^ its input, to create a delayed replica of the input pulse.
Asymmetries in the relative delay of the leading and trailing
edges are corrected either by independently controlling one
Q of the current sources or one of the thresholds.
rs
00
o
o
Q.
UJ
Croydon Priming Company ltd
This
invention
state
relates
to
pulse
characteristic
that
time,
in the
in the
data
acquisition
sition
path.
This
delay,
which
realized
in the
past
cable
additional
duction.
Circuits
input
reduced
a pulse
is
ted
the
delay
the
to
cable
for
time
the
by the
invention
of 20 n s ,
as g r e a t
extremely
prodelay,
the minimum
as the
in view of t h i s
requires
a
to produce
of r e q u i r i n g
least
analy-
during
probes
of
length
requiring
it
of
acqui-
and the
of
can be used
which
clock
order
probe
individual
of t h e
introduction
and of making
to be at
immediately
an a p p r o p r i a t e
disadvantage
circuit
the
disadvantages
width
delay
solved
according
to the
disclosed
produces
of a s i n g l e
resistor,
with
of no more than
70% of the
be i n t e g r a t e d
An even
the
hold
on the
acquisition
circuit
A particular
to
by p l a c i n g
data
changes
respect
typically
of l o g i c
time.
delay
art
prior
is
a significantly
width.
pulse
object
by means
pulse
is
state
requires
multivibrators
have
solved
object
to provide
This
logic
hold-
zero
of a set
non-zero
with
path
has
the
using
typically
acceptable
A major
method
to o p t i m i z e
these
the
volume for
large
difficult
but
This
circuitry.
relatively
between
the
is
analyzer
state
the
analyzer
delay
been
the
if
even
In p r a c t i c e ,
circuitry
state
to record
transition
transition.
acquisition
of a logic
ability
a clock
the
after
the
is,
at
signals
zer
for
analysis.
A desirable
has
especially
circuits,
delay
number of
in s e r i e s
(as
total
delay
channel
inverting
threshold
coupled
a delay
which
time.
of claim
part
is a d j u s t a b l e
a minimum r e q u i r e d
in m u l t i p l e
in cascade
characterizing
pulse
The c i r c u i t
is
form on a m o n o l i t h i c
circuit
elements
amplifiers).
designed
chip.
are
At the
width
connec-
output
of
1.
each
of
each
inverting
duce
the
This
is
these
abrupt
circuit
for
in the
second
abrupt
transition
when the
Each a b r u p t
inverter's
verters
edge.
delayed
then
Figure
leading
edge while
A final
circuit
element
1 is
final
provides
its
at
input
a block
rent
of
2 is
the
3 is
with
is
6 is
for
for
its
at
both
and
abrupt
both
of t h e
ramp
with
circuit
delay
capacitances
a preferred
and c u r -
embodiment
to
means
of the
of f i g u r e
of t h e
signals
of f i g u r e
circuit
the
of f i g u r e
1,
capacitances
1 when t h a t
circuit;
of the
inverting
of a n o t h e r
of the
inverting
and
3;
pulse
with
zero
circuit
and
3;
block
the
obtain
operation
of o b t a i n i n g
of c e r t a i n
schematic
of f i g u r e
of the
as an i n t e g r a t e d
schematic
a generalized
state-data
diagram
implemented
incorporating
the
1;
sources
a detailed
order
of d r i v i n g ,
pulse
elements,
illustrating
specific
a detailed
elements
Figure
in a c c o r d a n c e
a more d e t a i l e d
elements
5 is
the
present
in-
of
pair
threshold.
inverting
of f i g u r e
circuit
Figure
that
delays
final
of an a d j u s t a b l e
a waveform diagram
and c u r r e n t
4 is
inverter.
invention;
illustrating
Figure
its
other
chain,
a ramp at
transitions
as those
a delayed
next
capacitance
output
edges
cross
diagram
sources,
circuit
Figure
abrupt
discharge
in the
successive
capable
nominal
and t r a i l i n g
constructed
Figure
the
produce
produces
the
pro-
a ramp t r a n s i t i o n
of t h a t
each
of
polarity.
inverter
input
within
way,
opposite
will
threshold
an i n v e r t e r
at
cannot
produces
next
the
leading
transitions
the
through
of t r a n s i t i o n ,
polarities
of the
output
In t h i s
one delays
trailing
output
in the
output.
which
The ramp t r a n s i t i o n
polarity.
transition
of the
to
rapidly
but
of one p o l a r i t y ,
source,
The o u t p u t
source.
capacitance
transitions
current
ramp passes
the
charge
output
by the
done
can
transitions
output
capacitance
is
and a c u r r e n t
a capacitance
of a Logic
diagram
delay
circuit
respect
hold-time.
State
of f i g u r e
to c l o c k - d a t a
Analyzer
3 to
signals
delay
in
1 is
a block
signals
that
Figure
gital
is
be r e a d i l y
apparent
principles
of the
that
has
for
width
varies,
8,4
approximately
circuit
The delay
elements
prising
gate
1 includes
circuit
either
That
1 is
includes
elements
10 and
is,
for
that
on the
natively,
of U3, U4,
additional
may be i n s e r t e d
elements
it,
that
characteristic
signal
of
width
pulse
the
is,
state
1 were f a b r i -
delay
selected
state
delay
minimum
from
delay,
directly
as the
stage
or,
multiply
input
delay
delay
may
on the
repeated
a minimum range
com-
sources
of the
operation
The
capacitors
current
9 of a d d i t i o n a l
to the
delay
associated
adjustable
6
7 and 8.
sources
9 of a d d i t i o n a l
11 (U3 and U4),
gate
5 and
capacitors
current
one stage
the
comprising
associated
adjustable
providing
of delay
the
of U5, without
other.
output
the
C4 and c u r r e n t sources 14 and 15. A l t e r s t a g e s of delay s i m i l a r or i d e n t i c a l to stage
C3,
between
Each of gate
provided
a basic
one hand,
of U2 may be connected
existence
of the
become a p p a r e n t
circuits
That
delay.
and a s s o c i a t e d
explained
be absent
circuits
an a d j u s t a b l e
U2 and U5),
1 also
It will
digital
28 n s .
to
12 and 13 (C3 and C4),
14 and 15.
application
a minimum r e q u i r e d
selected
and a s s o c i a t e d
circuit
with
a function
3 and 4 (U1,
2,
(C1 and C2),
delay
40 ns,
as
ns
such delay
to provide
chip,
70% of the
of no more than
ten
a
as an i n t e -
of a logic
probes
the
upon e i t h e r
circuit
is an a d j u s t a b l e
It w i l l
that
however,
constructed
by the
in
circuit.
depend
integrated
di-
1 for
fabrication
art,
1 do not
measured
application
12 ns to
approximately
in the
or upon being
useful
signals
upon a s i n g l e
pulse
skilled
of f i g u r e
especially
In t h a t
analyzer.
cated
circuit
for
upon an i n t e g r a t e d
One m u l t i - c h a n n e l
proved
circuit
delay
those
configuration
circuit.
grated
to
circuit
delay
suited
well
especially
configurations
multiple-channel
multi-channel
of an a d j u s t a b l e
diagram
U2 and U5.
U1 through
a certain
of gate
U5 i n v e r t s
threshold
elements
is
the
signal
traversed.
U1 through
U4 is
applied
to
An i m p o r t a n t
that
each
of t h e i r
9
will
outputs
readily
other.
In the
U4 are
emitter
a capacitive
time
transition
becomes
directly
and i n v e r s e l y
external
number of
even
and t r a i l i n g
from the
the
varied)
the
1,
or the
output,
by t h e
therefrom
By using
gate.
both
the
an
leading
separate
times
If
the
currents
extracted
if
(or,
equally,
the
can be a d j u s t e d
idealized
include
not
delayed
to emphasize
be d e -
thresholds
over a c o n -
finite
by the
by the
circuit
of the
within
for
invenelement
a gate
rise-times
1
dia-
D. The timing
operation
delay
propagation
caused
delay
is
pulse
amount of delay
some p a r t i c u l a r
to f i g u r e
negative-going
are
within
current
determines
the
carried
gate
ramps
of U2.
two input
Positive-going
element
Ul.
positive-
by c u r r e n t
elapses
Once t h a t
source
before
threshold
are
7.
resulted
in abrupt
positive
leading
edges
L
C1 p r o d e t e r m i n e d , in p a r t ,
The slope
ramp p o r t i o n s
is
of U2 q u i c k l y charges C2 and produces
DL. Meanwhile, when the n e g a t i v e going input
they
of d i f f e r i n g
pulses
input
L and
edges
and c a p a c i t a n c e
RL whose slopes
action
occured
leading
positive-going
T for
edges
how much time
threshold
of
as f o l l o w s .
negative-going
by the
each
2,
trailing
delayed
inverted
duces
the
at
delay
propagation
at
transitions.
According
width
varied
how an input
2 is
and does
going
overall
for
gram of f i g u r e
itself,
each
transition
will
same amount.
are
next
in s e r i e s ,
signal
transition
and the
extracted
not
range.
of f i g u r e
tion,
input
of a gate
capacitance
of the
input
elements
gate
of the
2 illustrates
Figure
the
and the
inverting
capacitances
siderable
are
current
by a p p r o x i m a t e l y
layed
are
the
to
off
into
in a
a negative
turns
to the
current
resulting
that
during
proportional
source
edges
hand,
essentially
proportional
current
other
follower
than
greater
in t h e
not
of U1 t h r o u g h
a large
transition,
a positive
On the
of each
stages
of s u p p l y i n g
significantly
emitter
output
time
not
output
capable
during
loaded.
capacitively
the
followers
load
the
case
present
but
in one d i r e c t i o n ,
current
pass
reached
of these
RL t r a v e r s e
the
inverting
delayed
leading
trailing
edges
transitions
ramps
T at
edges
T
the
output
of U1.
However,
inverted
cnce
by U2 those
transitions
produce
C2 at the o u t p u t of U2 n e g a t i v e - g o i n g ramps RT. A f u r t h e r
i n v e r s i o n by a c a p a c i t a n c e - t o l e r a n t gate element would produce a
across
inverted
delayed
but
element
would
produce
from t h e i r
disconnected
connected
If
further
the
the
where
delay
1 as shown
circuit
and the
capacitance
leading
edges
the
with
become,
threshold
the
traverse
transitions
layed
from U4 is
at
or p o s s i b l y
signal,
is
it
of Us
input
further
action
provided
delayed
of
by U3
positive
de-
U3 g e n e r a t e s
ramps
become a b r u p t
to U4 t h e s e
RDT. As t h e y
and doubly
of U5. Meanwhile,
a positive-going
DDL
the
and the
corres-
output
of Us is
another
abrupt
transi-
is
a doubly
delayed
replica
of the
input
depending
upon
its
inverse,
the
DDL
U4 produces
signal,
by any ramp a c t i o n ,
de-
the
DDL. The r e s u l t
tion,
these
output
unaffected
transition
ponding
the
signal.
DT. Once a p p l i e d
edges
of U5,
DOT at
from the
negative-going
C4,
RDL. Because
from ramps
output
of
the
RDL. Meanwhile,
trailing
help
the
1. The i n v e r s i o n
ramps
input
been.
of C3 g e n e r a t e
abrupt
and
consider
figure
DL n e g a t i v e
positive
layed
in
gate
of U3 and Us w e r e
inputs
locations
then
desired,
of the
replica
the
of U3 had
input
is
if
present
A non-inverting
input.
a delayed
simply
be o b t a i n e d
could
results
These
of the
version
chosen
output
from U5.
2 demonstrates
Figure
by an amount
pulse
guarantees
this
the
clearly
figure
long
to
enough
cross
is
the
than
ability
shows
threshold
of the
capability
greater
to permit
the
the
that
the
3 is
a more d e t a i l e d
delay
circuit
1 of f i g u r e
pulse
to cascade
the
1.
width.
stages.
minimum pulse
slow f a l l i n g
(Vref)
Figure
the
circuit
1 to delay
The f a c t o r
Inspection
width
edge of each
and switch
the
need
gate
following
schematic
diagram
In this
integrated
of the
a
that
of
only
be
element
gate
element.
particular
circuit
embodiment
C1 through C4 of f i g u r e 1 are the b a s e - c o l l e c t o r
and b a s e - e m i t t e r c a p a c i t a n c e s of r e l a t i v e l y l a r g e t r a n s i s t o r s 16-19
the
capacitors
(Q7 through
1 are
figure
in
with
current
of each
current
supplied
transistors
associated
of these
resistors
current
to a d i o d e - c o n n e c t e d
drawn
is
current
integrated
circuit
embodiment
it
permanent
one-time
adjustment
of the
In o t h e r
trimming.
be e q u i v a l e n t
to,
The a d j u s t a b l e
many a p p l i c a t i o n s
lines
lay
as a j u n c t i o n
loop
to
an a p p r o p r i a t e
This
in which
value
in
such
as by
be,
actually
would
is
to the
response
can be made
resistance,
a control
example,
adjusted
dynamically
results
in
de-
of a d j u s t a b l e
set
for
delay
or
be useful
R1 a v o l t a g e - v a r i a b l e
the
a
perform
The device
would allow,
29
resistance.
invention
circuit.
by making
FET.
be e s t a b l i s h e d
R1 could
matched
a well
integrated
adjustable
such
of the
requiring
on a s i n g l e
electrically
to
circuit
delay
circuit
to
of R1,
readjustable
a repeatedly
That
In a m o n o l i t h i c
may be d e s i r a b l e
applications
by t h e
28 (Q2).
adjustment
value
Q6)
The c o l l e c t o r
controlled
30 (R1).
an a d j u s t a b l e
of
(Q3 through
transistor
from a c u r r e n t
resistance
20-23
is
7-15
sources
24-27.
sources
containing
laser
current
adjustable
with
implemented
conjunction
supplied
the
Also,
Q10).
of an i n t e r n a l
test.
Within
a multi-channel
the
fourth
nel
is
(or
smaller
a point
otherwise
than
By a d j u s t i n g
tween
this
negative
that
last)
the
edge
of the
of a p o s i t i v e
edge.
and
31 (R3)
to
Figures
4 and 5 show the
U1-U4 and U5,
details
respectively.
circuit
to
brought
other
delay
chanchan-
be-
of a
independently
any u n d e s i r a b l e
of the
of
each
connected
the
can be a d j u s t e d
allows
is
in the
locations
-V EE supply,
resistor
15 (Q6) for
sources
of a r e s i s t o r
signal
This
emitter
small
asym-
be e l i m i n a t e d .
metries
within
other
32 and the
input
the
source
corresponding
value
common point
current
of the
those
32 common to the
nels.
circuit
integrated
configuration
of
The p r o p a g a t i o n
5 used
with
the
effect
rising
current
should
of Q3-Q6)
over
of R2 to
and so responds
be chosen
is
that
signals
A clock
probe
measured
fiedby
the
depending
state
values
an o v e r a l l
give
under
is
decreases
coefficient
of V1 c a n
of
are
fed
to g e n e r a t e
to
upon the
a clock
clock
clock
and the
possesses
Analyzer.
34
circuit
35 upon
signal
can be complex
the
speci-
or t r i v i a l ,
of the
sophistication
The
signals.
some c r i t e r i o n
signals,
criterion
circumstance
clock
qualification
a qualified
The s p e c i f i e d
to the
analyzer
State
by the
be u t i l i z e d
to
signals
the
depicted)
explicitly
logic
analyzer.
the
state-data
signals
to be measured.
By d e l a y i n g
state-data
probe
pod 33 the
The q u a l i f i e d
fed
in
coefficient
of a Logic
diagram
pod 36 connects
is
ratio
to an i n c r e a s e
temperature
probe
tures
the
by a l t e r i n g
block
(not
test
in the measured
user.
A state-data
probe
ac-
voltage
V1 leads
drop
a generalized
signals
of,
base-emitter
temperature
voltage
pod 33 connects
whose f u n c t i o n
occurrence
the
and s t a t e - d a t a
clock
is
to z e r o .
equal
A system
Analyzer.
clock
to
6 illustrates
Figure
This
temperature.
currents
Q2. Q1 is on the same chip as the delay c i r c u i t 1
to the same t e m p e r a t u r e changes. The r a t i o of R2
into
current
collector
this
R2,
of n e g a t i v e
a range
the
for
and R4' C i r c u i t 29 p r o d u c e s
equal to the b a s e - e m i t t e r v o l t a g e
29 by Q1,
1,6 mV/°C,
to compensate
hence
with
slightly
A decreasing
R4'
R4 can
In order
to Q2 (and
supplied
increase
at a p p r o x i m a t e l y
be v a r i e d
U1-U5 of f i g u r e s 4 a n d
1 of f i g u r e s 1 and 3 i n c r e a s e s
elements
V1 a p p r o x i m a t e l y
( 1 + ( R 2 / R 4 ) ) . Since the
of Q1 times
delay
circuit
drop
a voltage
to
gate
temperature.
in c i r c u i t
complished
the
the
to c o n s t r u c t
slightly
of the
delay
the
pod 36 with
Logic
clock
measured
State
signal
to the
respect
Analyzer
is
state-data.
used
to
to
the
output
of t h e
output
of the
clock
strobe
control
analyzer
the
can achieve
From there
to a memory 38 and a t r i g g e r
state
logic
zero
a latch
the
37 t h a t
measured
circuit
hold
39.
time.
cap-
state-data
When c e r -
user-selected
tain
the
control
trigger
The
inset
nal
circuitry
of
of the
circuit
pod 36 d e p i c t e d
the
attenuator
use
by the
connected
cuit
ten
a suitable
the
dis-
This
43.
levels
the
reduces
that
will
threshold
of t h e i r
reference
reference
voltage
the
There
suitable
that
the
a ten-channel
for
43 i s
defines
logic
levels
not
be c o n -
pulse
are
42
to a c o m p e n s a -
should
voltage
1 and 3.
is fed to
outputs
between
probe
wire
attenuator
voltage
Vref w i t h i n
in f i g u r e s
test
to a level
signal
distinguish
The l o g i c
state-data
under
One end of the
logic
use of t h e
a probe
input
system
the
circuits.
as shown
itself,
each
inter-
concerning
3. The p a r t i c u l a r
in the
signal
detail
pod 36 and its
probe
inputs..For
an a d j u s t a b l e
delay
ten
cir-
attenuators
integrated
cir-
45.
within
Each channel
tor
46 to
lay
circuitry
driver
pair
has
and f a l s e .
and each
cuit
to
with
fused
occur
into
acquisition
additional
of f i g u r e
comparison
voltage
of true
data
40 c r e a t e s
generator
state-data
desired
ted
the
39 h a l t s
6 provides
figure
delay
connects
circuit
state-data
in the
a CRT 41.
upon
pulse
conditions
and a d i s p l a y
memory 38,
play
trigger
discriminate
47 to
cable
the
to
integrated
between
as p r e v i o u s l y
send
the
the
state-data
portion
consists
levels,
logic
described,
delayed
remaining
circuit
of a c o m p a r a -
a channel
of pulse
and an ECL output
signals
of the
logic
over
state
line
a twisted
anaylzer.
de-
1. A
circuit
delay
pulse
first
inverter
pulse
to be delayed
to
threshold
threshold
does
inverter
first
current
first
inverter
tance
means
ducts
that
re-crossing
the
input
internal
impedance
that
essentially
of the
second
capacitance
second
inverter
second
current
means
for
that
caused
by signal
output
circuit
second
inverter
to
the
first
capacitance
11)
having
internal
(6,
in
output
that
connected
polarity;
of t h e
in response
an input
that
con-
to a s i g n a l
threshold
input
does
essentially
the
to
threshold
readily
response
between
oppo-
to o u t p u t s
the
re-crossing
impedance
13)
not
of t h e
output
and an AC g r o u n d ;
(8,
means
capacitance
transitions
means,
crossing
impedance
its
at
polarity
supplying
means
polarity
capaci-
first
delivering
an output
first
of the
coupled
inputs
of t h e
in a d i r e c t i o n
means
transitions
pulse
a low i n t e r n a l
means
source
means,
a current
opposite
current;
of t h e
outputs
supplying
producing
higher
between
outputs
of the
and for
charges
polarity
the
and having
through
conduct
that
input
to
(3,
means
a substantially
inverter
to
response
connected
by input
means
signal
transition
that
impedance
14)
(7,
that
charges
caused
current
an i n p u t
an AC g r o u n d ;
for
means
transition
an output
response
crossing
in
connected
12)
means
source
inverter
a signal
(5,
means
means and
inverter
first
in
delivering
polarity
and f o r d e l i v e r i n g
higher
an i n p u t
current;
first
to that
for
receiving
a low i n t e r n a l
through
a substantially
capacitance
second
of a f i r s t
signal
for
an input
an output
of an o p p o s i t e
not conduct
by
having
having
current
first
site
and
an output
transitions
pulse
10)
transitions
conducts
readily
(2,
means
pulse
input
characterized
(4)
transitions
of e i t h e r
an a b r u p t l y
transitioning
connected
to
a current
means
of the
having
for
15)
output
the
the
first
an input
output
second
in a d i r e c t i o n
polarity;
coupled
to
means
to t h a t
and
the
output
its
input
that
signal
whose
leading
upon
of t h e
capacitance
opposite
its
at
delivering
polarity
to
output
in response
cross
of t h e
to
a threshold
and t r a i l i n g
2.
each
edges
are
edges
of the
A pulse
by the
(7,
14)
as
the
to
applied
circuit
first
A pulse
10)
pulse
delay
corresponding
the
in claim
and second
of the
input
1 wherein
(8,
15)
and t r a i l i n g
leading
first
the
inverter
currents
current
sources
means.
supplied
are
inde-
variable.
pendently
3.
from
delayed
circuit
delay
and second
(3,
as
11)
in claim
inverter
1 or claim
means
2 wherein
possesses
emitter
the
first
follower
(2,
out-
puts.
4.
A plurality
of pulse
delay
circuit
an i n t e g r a t e d
of t e m p e r a t u r e
the
circuits
as
and incorporating
currents
supplied
in claim
means
by the
3 fabricated
to vary
within
as a f u n c t i o n
and second
first
current
sources.
5.
Application
introduce
the
of the
delay
acquisition
pulse
into
the
of clock
delay
circuit
acquisition
data.
of claim
1 or claim
of s t a t e - d a t a
with
2 to
respect
to