Experiment 9- Single
Stage Amplifiers with
Passive Loads - MOS
D. Yee, W.T. Yeung,
M. Yang, S.M. Mehta,
and R.T. Howe
UC Berkeley EE 105
1.0 Objective
This is the second part of the single stage amplifier lab. We will be dealing with MOS
amplifiers in this experiment.
To show your understanding of the lab, your write-up should contain:
• A table showing the input resistance, output resistance, and gain
• A discussion on trade-offs issues among the three parameters Av, Rin, and Rout
• A discussion explaining the advantages and disadvantages of the different amplifiers
• A discussion of the differences between similar MOS and BJT amplifier stages
2.0 Prelab
• H&S: Chapter 8.3, 8.9
• You will now consider biasing issues with FETs. Below is an NMOS transistor that
will be configured as a Common Source Amplifier. For the figure below, bias the circuit so that VOUT = 2.50 V. Determine the proper bias voltage VBIAS needed to achieve
this. What can you say about the value of VBIAS when compared to VBIAS for the common emitter amplifier? Use the following MOS parameters for hand calculation and
for SPICE, in which you should plot VOUT vs. VBIAS.
VTO = 0.9 V, Kp = 20 x 10-6 A/V2, λ = 0.05 V-1
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Procedure
FIGURE 1.
NMOS Transistor in the Common Source Configuration
V DD = 5V
R C = 5kΩ
V OUT
W/L=93/9
v in
V BIAS
3.0 Procedure
FIGURE 2.
Common Drain with Biasing Circuit (Lab Chip 4 SF = source follower)
V DD = 5V
PIN 28
PIN 20
W
46.5
----- = ---------L
1.5
10 µF vIN
vOUT
PIN 21
v in
RBIAS
IBIAS
BIAS
PIN 22
IBIAS
PIN 14
Many of the amplifiers will contain special biasing current sources to set the collector
currents of the npns or the drain currents of the FETs. The drain or collector currents
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Experiment 9- Single Stage Amplifiers with Passive Loads - MOS
Procedure
will be equal to the current in an external resistor RBIAS. The user provides RBIAS across
pin 28 and pin 22. The current through the resistor is equal to IBIAS which sets the ID for
the NMOS transistor. IBIAS can be found by use of a voltmeter across RBIAS.
3.1 Common Source Amplifier
3. Figure 3 shows a Common Source amplifier. Let RD = 50 kΩ
4. Let vin be a sinusoid with an amplitude of 100 mV at a frequency of 5 kHz.
5. Measure VOUT and verify that the transistor is operating in the constant-current (satu-
ration) region. Measure the value of the drain current and compare it with the calculated value.
FIGURE 3.
Common Source Amplifier (Lab Chip 1)
VDD = 5 V
PIN 28
RD
PIN 9
DRAIN
PIN 10
10 kΩ 10 µF GATE
v OUT
W
46.5
----- = ---------L
9
vg
v in
PIN 11
SOURCE
PIN 14
PIN 14
6. Use the oscilloscope to measure the voltage gain vout/vin. Make sure that the output
isn’t clipping. Also measure vg/vin. Find the gain. Compare the value of the gain to
that of the Common Emitter.
7. One major difference between bipolar and MOS transistors is that the MOS transistor has an infinite input impedance. Because of this high input impedance, there is no
voltage attenuation from the voltage source to the amplifier input, even if the voltage
source has a large source resistance. Verify that this is true by measuring vg/vin. You
can obtain an estimate of the input resistance of the common source amplifier from
the gain vg/vin.
8. Measure the output impedance using a technique similar to the method used to measure the output impedance of the bipolar amplifiers in Exp. 8.
Experiment 9- Single Stage Amplifiers with Passive Loads - MOS
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Optional Experiments
3.2 Common Drain Amplifier (Source Follower)
1. Figure 4 shows a Common Drain amplifier with a current source biasing. The cur-
rent source is really an NMOS transistor and its small-signal resistance is 1 / (λnID).
Its bias current is the current through RBIAS = 10 kΩ. Let vIN be a sinusoid with an
amplitude of 200 mV at a frequency of 5 kHz and a DC offset of 3 V. Repeat the
steps above to find the gain and output resistance. As with common collectors, common drains are also used as voltage buffers. IBIAS is the same current through RBIAS.
FIGURE 4.
Common Drain Amplifier (Lab Chip 4)
RBIAS
IBIAS
PIN 20
W
46.5
----- = ---------L
1.5
vIN
BIAS
PIN 22
vOUT
PIN 21
v IN
IBIAS
PIN14
PIN14
4.0 Optional Experiments
4.1 Common Source with Source Degeneration
1. Connect the circuit of figure 9. Let RD=5 kΩ, RS=500 Ω, and VBIAS=3 V. Find the
gain, input resistance and output resistance. Note: VTn will not equal VTOn because of
the backgate effect. Source degeneration in MOS amplifier stages is not as widely
used as emitter degeneration in bipolar circuits. The transconductance of MOS transistors is much lower than that of bipolar transistors so that further reduction in gm is
usually undesirable. Also, the beneficial effect of raising the input impedance of a
bipolar transistor is irrelevant for MOS transistors since the input impedance is infinite. Degeneration is occasionally useful for making the transconductance independent of the device characteristics.
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Experiment 9- Single Stage Amplifiers with Passive Loads - MOS
Optional Experiments
FIGURE 5.
Common Source with Source Degeneration (Lab Chip 1, NMOS2)
V DD = 5V
PIN 28
RD
DRAIN
PIN 6
GATE
PIN 7
v OUT
v IN
W
46.5
----- = ---------L
3
v in
SOURCE
PIN 8
VBIAS
RS
PIN 14
PIN 14
Experiment 9- Single Stage Amplifiers with Passive Loads - MOS
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