University of Waterloo
Electrical and Computer Engineering Department
Electronic Circuits and Integration
NE-344 Lab manual
Lab 6: Single-stage NMOS Amplifier
Spring 2009
© Nanotechnology Engineering
University of Waterloo
Waterloo, Ontario N2L 3G1, Canada
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1. Objective
The goal of this laboratory exercise is to compare the performance of the following four basic
single-stage NMOS amplifier configurations under identical bias conditions for the mid-band
frequency range:
-
Common Source (CS) with no Rs
Common Source (CS) with Rs
Common Gate (CG)
Common Drain (CD)
You need to first establish the DC bias (quiescent operating) conditions then follow with a
systematic comparison of the AC parameters, such as input resistance, output resistance and
voltage gain.
2. Background
It is recommended that you read the pertinent Sections of your textbook to familiarize yourself
with the basics so that the lab session can run smoothly completing all measurements and
documentation of results in about 3 hours.
Here is a reference to materials for study:
[1] Microelectronic Circuits, 5th Ed., Sedra/Smith
-
DC biasing – sections 4.3, 4.5 and example 4.2
Common Source Amplifier – Section 4.7.3, 4.7.4
Common Gate Amplifier – Section 4.7.5
Common Drain Amplifier – Section 4.7.6, 4.7.7
Amplifier types
Depending on the input and output type of signals, four different type of amplifiers can be
implemented as shown in figure 1.
Single-stage NMOS amplifier
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From a DC view point, the common Source amplifier, the common Gate amplifier and the
common Drain amplifier look the same (see Figure 2).
Figure 1. Amplifier types
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The common Source amplifier is best suited for obtaining the bulk of the gain required in an
amplifier. The Source follower or common Drain amplifier finds application as a voltage buffer
for connecting a high-resistance source to a low-resistance load and as the output stage of a
multistage amplifier. The low input resistance of the common Gate amplifier makes it useful for
specific applications that take advantage of its excellent high-frequency performance. Refer to
Table 4.4 in [1].
Figure 2. Universal single-stage NMOS amplifier
The resistors RG, RD, and RS are used to establish the desired DC bias (quiescent operating)
conditions of the circuit. The capacitors CG, CD, and CS are signal coupling or bypass capacitors
employed to connect the appropriate NMOS terminal to a signal source, a load, or to ground,
thus enabling the realization of the different amplifier configurations. The appropriate
connections are listed in Table 1 with the resulting circuit configurations shown in Figures 3, 4,
5, and 6.
The capacitors are relatively large in value (generally in the µF range) blocking DC but can be
treated as short circuits to signals in the mid-band and higher frequency range. These three
capacitors determine the low frequency response of the circuit. The transistor’s internal
capacitances are small (in the pF or fF range) and can be treated as open circuits at low and
mid-band frequencies. However, they determine the response of the circuit at high frequencies.
Table 1. Circuit connections for the amplifier configurations
Configuration
Input
Output
Ground
Common Source
X
Z
Y (bypass RS)
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X
Z
Y (bypass RS)
Common Gate
Y
Z
X (bypass RG)
Common Drain
X
Y
Z (bypass RD)
Common Source with
Figure 3. Common Source amplifier
Figure 4. Common Source amplifier with Source resistor
Design Criteria
Remember that rule of thumb design methods are often satisfactory for an initial design,
particularly considering the ±5% tolerance on resistors and (+100%, -50%) tolerance on gm
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discrete NMOS transistors. The circuit in Figure 2 employs a very common biasing arrangement
for a dual supply circuit. RS serves to provide negative feedback to stabilise the DC bias.
Figure 5. Common Gate amplifier
Figure 6. Common Drain amplifier
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-
The design of the bias circuit needs to minimize the sensitivity of ID to temperature
-
and Vt. This involves a trade off including a resistor
in the Source lead of the CS stage,
which improves some amplifier performance measures at the expense of reduced
voltage gain.
For this lab study the DC supply voltages are: VDD =+9 V and VSS =-9V.
The NMOSFET is Q2 on the CD4007 (or MC14007) DIP package (see Figure 7).
The resistor values are RG= 1.5 MΩ, RD=20 kΩ,
-
=1.8 kΩ,
=18 kΩ with RS =
+
-
.
The load resistor is R=47 kΩ which is connected as specified in Table 1.
The AC input signal (mid-band) frequency is 1 kHz at 30 mVP-P, the signal source
resistance is R=50 Ω.
All signal coupling capacitors are 47µF and assumed to be short circuits for AC
signals at the operating frequency of 1 kHz. (An electrolytic capacitor can explode if
connected with the wrong polarity.)
Figure 7. IC MC14007 pin connections
3. Pre Lab
In all your calculations, assume Threshold voltage (Vt) of 1.65 V, Early voltage (VA) of 51 V, and
transconductance parameter
are supplied above.
. Values for the various components
Complete the hand analysis column in Table 2 amplifier bias circuit data. Assume equal voltage
drops across RD, NMOS, and RS as start point.
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(1) With reference to the above circuits (see Figures 3, 4, 5, and 6), calculate Rin, Rout, Av and
fill in Table 3-Key Amplifier Performance Parameter Hand Analysis Calculations.
(2) Calculate the reactance of a 47 µF signal coupling capacitor at the 1 kHz operating
frequency and comment on its significance relative to the resistances and voltage gain
you have computed.
Table 2. Amplifier bias circuit data
Hand
Measured
Item
analysis
analysis
RD
RG
RL
VD
ID
VG
VS
gm
VD/ RD=
Table 3. Key amplifier performance parameter hand analysis calculation
Parameter
Common-Source
Common-Source with RS
Common-Gate
Common-Drain
Rin
Rout
Av=Vo/Vi
Pre-wire the DC bias circuit.
4. In Lab Procedure
Complete the measured results column in Table 2 amplifier bias circuit data.
(1) Measure Rin, Rout, Av using a mid-band frequency of 1 kHz and fill in Table 4-Key
Amplifier Performance Parameter Measured Results. Comment on the possible
differences between the numbers in the two tables of 3 and 4.
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Some laboratory stations will require the attenuator circuit (see Figure 8) for the signal source
(or function generator). This circuit is added to the input if the signal voltage level is too high.
Observe the sinusoidal output waveform on the oscilloscope and look for distortion due to
clipping or the transistor leaving saturating (see Figure 9)
Figure 8. Attenuator
(a) Distortion due to clipping
(b) Distortion due to cut-off
Figure 9. Distortion due to (a) Clipping, (b) Cut-off
Table 4. Key amplifier performance parameter measured results
Parameter
Common-Source
Common-Source with RS
Common-Gate
Common-Drain
Rin
Rout
Av=Vo/Vi
The input and output resistances may be measured using the circuits shown in Figure 10. Use a
suitably chosen resistance value RTEST between nodes A and B (that is comparable to the small
signal resistance you have estimated).
This results in an input resistance
Similarly
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Here, it is important that you connect the amplifier input to AC ground via a 51 Ω resistor for
the output resistance measurement.
(a) Input resistance measurement circuit
(b) Output resistance measurement circuit
Figure 10. Resistance measurement circuit: (a) Input, (b) Output
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