MOS IC Amplifiers
• MOSFETs are inferior to BJTs for analog design in terms of quality per
silicon area
• But MOS is the technology of choice for digital applications
• Therefore, most analog portions of mixed-signal designs are MOS
• Most MOS amplifiers will be IC amplifiers with “active” loads
• Resistors and decoupling capacitors are too expensive on ICs
Token Ring LAN
JSSC 12/89
Lecture 24-1
NMOS Amplifier --- Active Load
• Natural extension of amplifier with resistor pull-up
• Size M2 and bias M1 so that M1 is in saturation
• This is a digital NMOS logic gate when large input signals are applied
VDD
M2
iD2
vo
M1
iD1
vi
Lecture 24-2
Load Line View
• “Load line” is nonlinear
M2-NMOS
+
VDD
15V
L=10U
W=2U
0
D
vo
10
20
20
S
mA
ID2
10
ID1
VC27
3V
-+
M1-NMOS
L=2U
W=10U
D
S
+
VO
+
VO
VGS=3v
-
0
ID2
ID1
Lecture 24-3
NMOS Amplifier Example
• For a larger dc input bias voltage M1 is no longer in saturation
M2-NMOS
+
VDD
15V
L=10U
W=2U
0
D
vo
10
20
20
S
VGS=5v
mA
ID2
10
ID1
VC27
5V
-+
M1-NMOS
L=2U
W=10U
D
S
+
VO
+
VO
VGS=3v
-
0
ID2
ID1
Lecture 24-4
Small Signal Model
• M2 behaves like a resistor in the small signal model
• Why?
VDD
M2
iD2
vo
M1
iD1
vi
g m1 v i
ro1
g m2 v gs2
ro2
vi
Lecture 24-5
Small Signal Model
vi
g m1 v i
ro1
g m2 v o
ro2
Lecture 24-6
NMOS Amplifier Example
• We would tend to lower the “resistance” of the pull-up transistor (increase
K2), or decrease the current levels of the amplifier transistor (decrease K1) to
keep M1 in saturation
• But these changes tend to lower the gain
0
vo
10
20
20
mA
K1
K2
10
K2
K1
0
ID2
ID1
Lecture 24-7
NMOS Amplifier Example
• Design objective is to make K1 as large as possible, and K2 as small as
possible, to get a reasonable gain
M26-NMOS
+
VDD
15V
L=10U
W=2U
e2
D
e3
e4
frequency
e5
e6
S
ID2
13
4.47 v/v
ID1
M1-NMOS
L=2U
W=10U
D
VIN
SIN
-+
+
VO
-
S
DB(VO)
• Why the deviation from ideal gain?
Lecture 24-8
Body Effect
• For discrete FETs there is no body effect since the source is tied to the body
• For ICs, all of the NFET body nodes are tied to the lowest potential in the ckt
• The source of our load transistor is not at the same potential as the substrate
• Source voltage partially modulates the channel --- back gate effect
VGS > Vt
VDS > 0
VS>0
+
n+
QI
QB0
n+
VB
• For large signal behavior this is captured by the change in Vt based on the
parameter, gamma
V t = Vt0 + γ ( 2φ f + V SB – 2φ f )
Lecture 24-9
Body Effect
• The impact on the small signal model is a function of same parameters
• The change in vo (which is the source voltage) modulates the back gate
VDD
M2
+
+
vo
M1
D
G
iDS1
M2
vgs2
_
g m2 v gs2
ro2
vds2
g mb v bs2
+
vbs2
_
_
B
S
vi
Lecture 24-10
Common Source CMOS Amplifier --- Active Load
• Body effect is not as significant a problem for CMOS
• Current sources are used as pull-ups instead of resistors or load-transistors
• Having complementary types of transistors simplifies the implementation
• Is the body effect a factor for this amplifier?
IREF
+
+
vi
_
vo
_
+
IREF
+
vi
_
vo
_
Lecture 24-11
Common Source Small Signal Model
• Load line is now nearly a constant current --- huge gain
• What does the small signal model look like?
+
IREF
+
vi
_
vo
_
Lecture 24-12
Common Source Small Signal Model
+
IREF
+
vi
_
vo
_
Lecture 24-13
CMOS High Gain Region
• Input-output relation is very similar to a CMOS inverter
Vt = 1v K=100µA/V2 lamda=0.01
+
VDD
10V
M3-PMOS1
L=10E-6
W=10E-6
S
0
D
IDS
IREF
400UA
M1-NMOS
L=10U
W=10U
D
VI
3V
VO
-+
S
2
3
4
5
11
VO 10
9
8
7
6
5
4
3
2
1
0
M2-PMOS1
L=10E-6
W=10E-6
S
D
1
+
VI
-
Lecture 24-14
CMOS High Gain Region
• What is the allowable range for vo and vi ?
1
2
3
4
11
10
VO
9
8
7
6
5
4
3
2
1
0
VI
Lecture 24-15
ac Response
Vt = 1v K=100µA/V2 lamda=0.01
• Using an ac input with a 3 volt offset:
+
M3-PMOS1
L=10E-6
W=10E-6
S
VDD
10V
M2-PMOS1
L=10E-6
W=10E-6
S
D
e2
414.800 µA
-+
e5
frequency
e6
36
IDS
VSSIN
SIN
e4
37
D
IREF
400UA
e3
35
M1-NMOS
L=10U
W=10U
D
S
34
VO
33
+
3.568 V
-
32
31
30
DB(VO)
Lecture 24-16
Common Drain (Source Follower) Amplifier
• Source Followers are used for output stages
• Gain less than unity, but provides low output resistance to drive loads
100µA
vi
vo
Lecture 24-17
Common Drain (Source Follower) Amplifier
100µA
vi
vo
Lecture 24-18
Common Drain (Source Follower) Amplifier
Lecture 24-19
Source Follower
• For an emitter follower, the gain is the voltage division of input resistance and
emitter resistance
• But the source follower is somewhat different from an impedance reflection
standpoint
VDD
vs
I
RL
-VSS
• Small signal impedance looking into the gate appears as an infinite resistor,
while that from the perspective of the source is finite
Lecture 24-20
Small Signal Model
• Assuming that RLis infinite?
Lecture 24-21