ENT 162 – Analog Electronics
Laboratory Module
LABORATORY MODULE
ENT 162
Analog Electronics
Semester 2 (2005/2006)
EXPERIMENT 4 : The Common–Drain Amplifier (Source-Follower)
Name
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Matrix No.
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PUSAT PENGAJIAN KEJURUTERAAN MEKATRONIK
KOLEJ UNIVERSITI KEJURUTERAAN UTARA MALAYSIA (KUKUM)
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ENT 162 – Analog Electronics
Laboratory Module
EXPERIMENT 4
The Common–Drain Amplifier (Source-Follower)
1. OBJECTIVE:
1.1
To demonstrate the operation and characteristics of a self-biased Common–Drain
Amplifier.
1.2
To investigate what influences its voltage gain by using the JFET parameter.
2. PARTS AND EQUIPMENT:
2.1
Resistor 1/4W 1 kΩ
- 2 Pcs
2.2
Resistor 1/4W 100 kΩ
- 1 Pc
2.3
Capacitor 25V 2.2 µF
- 2 Pcs
2.4
MPF102 n – Channel JFET
- 1 Pc
2.5
0 – 15V DC Power Supply
- 1 Unit
2.6
Signal Generator
- 1 Unit
2.7
Dual Trace Oscilloscope
- 1 Unit
2.8
Breadboard
- 1 Unit
2.9
Multimeter
- 1 Unit
2.10 Jumper Wire
3. INTRODUCTION:
The Common–Drain Amplifier, often referred to as a Source-Follower is characterized by
application of the Amplifier input signals to the Gate lead while its output is taken from the
Source, the output signal is never larger than the input but is always in phase with the input.
The output follows the input.
Useful formulas:
1. Av =
Vout
Vin
- Voltage gain
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ENT 162 – Analog Electronics
2. Av =
Laboratory Module
g m Rs
1 + g m Rs
3. VGS(off) =
- Voltage gain
2 I DSS
gm0
4. ID = 2 IDSS [
- Dc Gate to Source cutoff voltage
( R S g m 0 + 1) − ( 2 R S g m 0 + 1)1 / 2
]
( RS g m 0 ) 2
- Dc Drain (Source) current
5. VS = IDRS
- Dc Gate to Source Voltage
6. VS= - VGS
- Dc Gate to Source Voltage
7. VDS = VDD - IDRS
- Dc Drain to Source Voltage
8. gm = gm0 [ 1 –
VGS
]
VGS (off )
- JFET forward transconductance
4. PROCEDURE:
4.1
Wire the circuit shown in Figure 4.1. Do not connect the Signal Generator and the
Power Supply yet.
4.2
Check all connection. Apply only the 15 V supply voltage to breadboard. With a
multimeter, individually measure the JFET’s quiescent Drain current, ID and Gate to
Source voltage, VGS. Record your values in Table 4.1. Base on the given values for
gm0 and IDSS. Calculate the JFET’s tranconductance, gm (Equation 8) at this quiescent
point and record your result in Table 4.1. Compare your measured values with what
you would expect to measure. Use Equation 4 to calculate the expected value for ID.
4.3
Connect Channel 1 of your Oscilloscope to the Amplifier’s input, Vin and Channel 2 to
the 1kΩ load resistor, Vout. Then connect the Signal Generator to the circuit as shown
in Figure 4.1 and adjust the sine wave output level of the Generator at 1V peak-topeak at a frequency of 5 kHz.
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ENT 162 – Analog Electronics
Laboratory Module
Figure 4.1: Experiment Setup
4.4
Calculate the expected voltage gain from Equation 2 using the transconductance value
determined in Step 4.2. Record this value in Table 4.2. Measure the actual circuit
voltage gain by dividing the peak-to-peak output voltage, Vout by the peak-to-peak input
voltage, Vin (Equation 1).Record your result in Table 4.2.
4.5
Remove RL. As in Step 4.4, determine the voltage gain by measuring Vout and Vin.
Compare your measured result with the expected value (Rs = RS). Record your results
in Table 4.2.
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ENT 162 – Analog Electronics
Laboratory Module
Name
:
______________________________
Matrix No
:
______________________________
Date : ______________
5. RESULTS:
Table 4.1: DC Values
MPF102 Data
VGS =
Parameter
ID
VGS
gm
IDSS =
Measured Value
gm0 =
Expected Value
% Error
Table 4.2: Amplifier Gain
Condition
Vin
Vout
Measured
Gain
Expected
Gain
%
Error
Normal Circuit
(Step 4)
No Load
(Step 5)
6. CALCULATIONS:
Instructor Approval :
____________________
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Date :
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ENT 162 – Analog Electronics
Laboratory Module
Name
:
______________________________
Matrix No
:
______________________________
Date : ______________
7. QUESTIONS:
1. For the circuit in Figure 4.1 with IDSS = 10mA and gm0 = 5000µS, the voltage gain from
Gate to Source is approximately
…………………………………………………………………………………………
2. The signal at the Source is out-of-phase with the Gate signal by
…………………………………………………………………………………………
3. If the JFET forward transconductance in the circuit is increased, the voltage gain will
…………………………………………………………………………………………
4. If the load resistor RL in the circuit is decreased, the voltage gain will
…………………………………………………………………………………………
5. The Common-Drain Amplifier is similar in operation to a bipolar transistor
……………………………………………………………………………………
Instructor Approval :
____________________
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Date :
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ENT 162 – Analog Electronics
Laboratory Module
Name
:
______________________________
Matrix No
:
______________________________
Date : ______________
8. DISCUSSION:
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9. CONCLUSION:
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