◆ Cadence
OrCAD V16.6 Capture What’s New
Cadence推出最新版本OrCAD Capture V16.6，新增New Function
如:Close All Tabs、Lock Reference，SI Analysis更可在SigXplorer設定的
拓樸結構及 Constraints 可直接回編到電路圖上，大幅簡化與縮短
Pre-Sim 的作業流程。如何快速了解有哪些實用的新功能及用法。
請參考以下OrCAD Capture V16.6各種新功能介紹。
．Date： 2012 / 11 / 7
．Author： Allis/Mark
．Revision： 1.0
．Version： V16.6
．備註:
http://www.graser.com.tw
◆ OrCAD

Capture V16.6 新增功能:
Configuring Menus and Toolbars:
自訂 Menu 和 Toolbars。如:改變 Menu item 位置和名稱、功能封鎖、功能圖案更改。
(註:右鍵選單無法修改)。
檔案位置<Cadence_installation>\share\orResources
修改 XML File

Enhanced Save Function for Design and Library:
修改過的 Design or Page or Library 會在未 Save 前，標示 Mark(*)星號。

Enhancements in the Find Function:
1. Property Name=Value：可指定找尋某一個 Property 的 Value，Ex：pcb footprint=PLCC28
Note：Property name 需為完整字串，萬用字元(*)只支援 Value 字串。
2. Regular Expressions:搜尋區間範圍的零件，Ex：U4[1-4]
Note : 當兩個功能都被開啟時，Regular Expressions 搜尋只支援 Property Value 的字串。

Global Replace for OffPage:
一次性替換相同 Net Name 的 OffPage，將 A 名稱換成 B 名稱。

Enhancements in Cache Updates:
可在 Design Cache 中一次選取多個零件，透過 Replace Cache 換成同一個零件。

Setting the User Assigned Flag:
1. Preserve Designator：當 Reference 清成”?”時，同類型複合式零件可保留 Section。
2. Preserve User Assigned Valid References：可以保留 User 自訂的 Reference。
註:保留 Part Reference 可透過
1.Edit Property
2.直接修改 Part Reference Value
3.從 PCB Board 修改完後 Back Annotate 回線路圖
Preserve Designator(保留原本的 Section)
Preserve User Assigned Valid References(修改過的 Reference 會加上( _ )底線)

Design Level Auto Reference:
在階層式電路中擺放零件時，可依照整份 Project 自動編號，避免零件編號重複。

Browsing Designs Created Using Earlier Versions:
可直接 View 舊版本的線路圖，當執行存檔動作時，才會跳出警示訊息是否要 Update Design。

Closing all Tabs:
可以利用菜單或是在分頁上，選擇一次關閉所有開啟的 Page 或是關閉所有 Page 但保留當前 view 的
這一頁。

Design Rule Check (DRC) Enhancements:
可以透過 TCL/TK 編寫客製的 DRC 檢查。

Project Save As Enhancements
對於 Project 的 Save as 除了 OPJ 檔外，現在能把 DSN 或是 Output File 一併存入指定的資料夾中。

Enhancements in the NetGroup Use Model:
Assign a NetGroup to a Bus:
可以在 BUS 線上，直接放上 NetGroup 名稱
Reorder Pins in an Unnamed NetGroup:
可針對 Unname NetGroup 裡的成員調整順序。
Add and Remove Pins from a NetGroup:
NetGroup Block pin 腳，可直接從 NetGroup 中選擇要接的 NetGroup 及不想接的。
Visible NetGroup References:
現在不論 Port 或是 Offpage 也能清楚辨識屬於哪一個 NetGroup。
Find NetGroup References:
可以利用 Find 功能尋找 NetGroup Pin。

OrCAD Capture V 16.6 正式支援連動 SigXplorer 進行訊號完整性分析作業
以往RD或 SI 工程師若要進行 Constraint 規範的制訂時 , 往往必須使用 SigXplorer或進行
Pre–Simulation . 但是要進行此操作必須請 PCB Layout 工程師來協助作業 , 相當不方便.
由16.6 版開始 , Capture正式支援與SigXplorer可直接雙向連動作業. RD或SI工程師要進行
Constraint 規範評估與設定時不需要再去麻煩PCB Layout 工程師 , 我們可由線路圖直接產生電路拓
樸結構並帶入到SigXplorer 環境中進行訊號完整性的分析。
Analyze / Edit Topology
SI Model Association
Topology Extraction
Topology Association
Netlist to
PCB Editor
Audit / Refine Topology & Constraints
工程師在分析完畢後可在 SigXplorer 裡面設定 Constraint 後再回編到 Capture .
當 PCB Layout 工程師在 netin 完成後 , 這些 Constraint 設定也隨著 netlist 的導入而自動帶到
Allegro / OrCAD PCB Layout 的 Constraint Manager 環境中.
且爾後當該份電路圖被再次利用時 , 工程師無須再去重複先前的作業 , 所有的拓樸結構 , T 點 , Xnet
及 Constraint 資料都已經存在電路圖上.

Fixed CCRs
CCR ID Description
12577 Resetting part references to ? resets the package designation
13642 Problems with replace cache when parts are copied to new DSN
20701 Annotation only change designator, treat reference as hard
28078 connectivity incorrectly re-evaluated when port mirrored
33956 Ability to set gate id, annotate, keep gate assign, set refs
35310 copying parts to a heirachal page does not auto reference
55359 two grid gap appears while placing wires
74510 Ability to turn off specific DRC markers.
111399 TCL: option of invisible net alias
114709 Wire is missing at the the starting upto 1.5 grid (approx.)
115833 Placing Sections of Hetrogeneous parts need enhancement.
124736 Enhancement in DRC report
153574 option of display enable/disable for Net Alias
158361 Capture Place wire looks unconnected
163978 DRC exception table or ignore option at pin level
176359 ABLE TO IGNORE DRC ON SELECTED NETS/ PINS
196584 drawing wires taking lots of time
232731 Why capture places Hetrogeneous parts wrongly?
258906 make net alias invisible in Capture
270946 Wanted to lock some Part Reference values during annotation
273524 Duplicate references in Capture 10.3
294858 Capture hangs due to any operation on this design
337644 Edit while Place does not work for hetrogeneous part
338235 TCL: Automatic synchronization for externally refrenced designs
339378 Automatic synchronization for externally refrenced designs
361079 Cannot see lengthy paths in "Select Directory" while File >> New >> Project
373714 Reference"SATA0" will become "SATA"
377353 Performance issue in Capture while working with big design
381773 Why does CIS hourglass when copy pasting 1 part
381801 Method to lock "Designator"
385581 Option to lock refdes
396374 Hard_Location for part references
397503 Edit while Place does not work for hetrogeneous part
435034 Auto reference placed parts does not work for hierarchical designs (DSN)
464453 Getting DSM0020: Unable to Paste Object Error
477438 Allegro Design Entry operating very slowly
479199 Replace cache doesnot work on same library path
480002 Global replace for Off page connector
509528 Replace Cache is not updating the timestamp resulting error DSM0020 : Unable to paste
object.
533895 TCL: DRC A method to check the Reference Designator Prefex
536039 Why capture places Hetrogeneous parts wrongly?
542653 Slow Capture Performance while selecting multiple nets
545360 Global Replace command not working for a bus
570012 Global replace for Off page connectors and Power/Gnd
585841 Add PARTGROUP to Annotation and to the Heterogeneous part itself
620319 Automatic synchronization for externally refrenced designs
621054 Renamed net in netlist isolates components from the rest of the net.
628823 enahncement to enlarge select directory window size horizontally.
650011 Add PARTGROUP to Annotation and to the Heterogeneous part itself
650130 TCL:Option to disable power nets from cross probing
652202 Update the Select Directory window to current Windows look and feel
653792 ALG0078 while creating netlist
656562 Enhancement : Capture.ini path should be user's home location
673323 Star in tab system not functioning in same way for library and design
682645 Add PARTGROUP to Annotation and to the Heterogeneous part itself
691018 Option to lock refdes
691502 Option to lock refdes
692025 TCL:close all the schematic pages
693632 Property similar to hard location which when put on a part will be skiped while annotation even
with Unconditional refer
694609 Property similar to hard location which when put on a part will be skiped while annotation even
with unconditional refer
702468 Enhancement for advanced search parts with specific property values.
713626 TCL:Closing Multiple Schematic Pages at once
726621 TCL:Command to close all open tabs of a design except “Project Manager”.
736980 Add PARTGROUP to Annotation and to the Heterogeneous part itself
740538 Enhancement : TCL:Option to close all opened schematic pages only in Capture.
743894 Add PARTGROUP to Annotation and to the Heterogeneous part itself
750501 Method to lock "Designator"
751388 TCL:Function to close all open tabs of a design except "Project Manager".
756925 Capture update file or directory browser to new Windows style
767749 Graphic line property like color does not change after save
776027 Enhancement: Ability to re-size the “Select directory” for netlist window.
788944 Add PARTGROUP to Annotation and to the Heterogeneous part itself
790111 Why capture gives "could not find .dsn" message when opening pspice design for the
second time?
790414 P-CAD schematics get crash when converted to Capture.
791392 TCL:DRC check where two terminals of any discrete part tied to same POWER/GND net
795861 Add PARTGROUP to Annotation and to the Heterogeneous part itself
797862 Ability to open 16.2 design (only to view) in v16.3 without converting it
797898 TCL:Option to retain schematic level property while linkdatabase part.
800346 Way to auto increment refdes across schematic folders within design
819020 Getting DSM0020: Unable to Paste Object Error
821994 Move Pin Text when creating a new symbol
834091 ENH: Ability to move pin name and pin numbers at library level
845314 Ability to ignore parts during annotation
846373 TCL:Date format under Design Properties
848582 TCL: Command to close all open tabs of a design except "Project Manager"
849408 Designator doesn't gets assigned to heterogeneous part if designator is changed after
selecting part
850844 exclude a selection within a page from annotation
851830 Ability to disable cross-probing for specific net in one direction (Allegro to Capture).
852836 Ascend hierarchy option grayed out
854472 Select Directory window is very narrow. Directory selection is difficult for long directory names
858454 Component gets locked if project closed with Part Editor open
866699 Ability to crossprobe with filter like parts / nets
866784 ENH: Ability to move pin name at library level
869528 Refdes increment on copying part is not with respect to occurence value.
872379 TCL:Closing schematic windows or tabs all in one
873521 Could not find *.dsn warning when opening project
873550 ENH: TCL:Function to sort parts by library name in Design Cache
879218 Copying a pin with help of CTRL key is giving error for overlapping pins
882575 Option to disable cross probing for power/ground nets.
884192 Enhancement: TCL: DRC for H-pin and H-Port mismatch
887096 Editing excel doc(OLE object) after zooming into schematic affects size of spreadsheet
on schematic
887202 ENH:TCL:Intersheet reference for H-ports should be like as of offpage connectors
889816 Cross probing of power nets from Allegro causes Capture to hang
889826 TCL: Diff Pairs not being created automatically even with _P & _N net syntax
890720 ENH: TCL Script to place the entire Orcad library in one DSN file at once
894726 TCL:ISO 8601 for naming archive
895496 Enhancement: Capture should remember the docked position for a project
896315 heterogeneous part's section not updated on changing it
896817 New TCL/TK commands help for attached file containing CIS TCL intefaces
898029 ENH: TCL:To show net alias clearly in print out if alias has underscore
904366 Junction dots get added or deleted which changes in the net name when rotating the design
905538 User should be able to change the bundle block
907977 ENH: Cadence Product Choices dialogue box is not wide enough to display entire
name of products
908810 ENH: Web reources link are not pointing to correct pages
908893 TCL:Waiving DRC's in Capture as being done in PCB Editor
914262 ENH: Disable CIS warning Cannot place database part
921919 ENH: The H block reference msut be picked from occurence value
925830 Option to lock refdes
930217 Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.
931719 Option to lock refdes
931781 For Link “selected occurrence only” - DoNot Display Update Symbol Dialog
935147 ORCAD Suppress Warning in Create Netlist>Setup issue while creating Netlist
938730 While auto referencing the parts to be placed, Capture doesn't look for similar refdes existing in
the lower hierarchy
942514 Docking state of Project manager window is not remembered when a project is closed and
reopened
944045 User would like to be able to replace cache on several parts at once
952741 ENH: Uprev process should save the existing 16.2 design on open
964950 Modifying pin names using Split part command is not updating the part.
968679 ENH: Option to close all open shcematic pages.
969564 Waive DRC option in Capture, as is available in PCB Editor
970133 ENH: Properties displayed in datatip should be customizable
975684 ENH: Reviewing lower version design on higher version should not change the database
format
977238 ENH: Last column in browse spreadsheet can't be increased in width till other columns are
narrowed
979770 Update netgroup box at change
982720 ENH: Option to preserve section of homogeneous package in annotation.
985385 ENH: Data-tip of pins shouldbe more informative
988097 ENH: Add Off paeg connector in Global Replace dialogue box.
989103 How to create a new menu with TCL script in Capture
992941 ERROR(ORCAP-19005) occurs when user tries to open second Capture application
997521 Back annotation doesn’t work if user renames refdes as per grid based
998469 Add 'NET_SHORT=YES' as default in allegro.cfg
999421 Enclosed Polyline goes black and white when moved
1000127 Incremental annotation creates duplicate refdes
1000419 Net properties to be displayed on tooltip
1000506 Replace part in Design Cache not updating the values when same library is selected
1001684 backannotation does not work if refdes is lowercase
1005805 Project Manager not docked as set
1010988 ENH: ADD ISO 8601 Date Time format to Capture
1011871 ENH: The H block reference msut be picked from occurence value
1012008 Enh: Option to remove symbols (! and ^) from Irefs.
1012459 E1: The error message "ERROR(ORCAP-19005)" is not descriptive
1014750 Bus shown as bundle in netgroup
1019868 Warning(ORCAP-1589) Net has two or more aliases
1023433 ENH: Finer mouse zooming
1024471 DRC doesn’t report if both the pins of a 2 pin device are connected to same net.
1029589 drawing diagonal wires in Fisheye view mode causes crash
1031521 While auto referencing the parts to be placed, Capture doesn't look for similar refdes existing
inThe lower hierarchy
1033179 Finding Power\GNDs in Capture highlights other power and GND symbols.
1033822 ENH: Function to only annotate newly added parts in bottom design of hierarchy
1041492 Enh: Pin names of pins palced on right boundary of part must start from same X location
1044724 Suppress warning feature not working correctly.