8 Extracting PCB Netlists.............................................................................................................................8-1
8.1 Schematic Packaging..........................................................................................................................8-1
8.1.1 Using Pkgr...................................................................................................................................8-2
8.2 Extracting a Netlist for CapFast-PCB and PADS-PCB ......................................................................8-3
8.2.1 Assigning Reference Designators and Pin Numbers....................................................................8-4
8.2.2 Properties Used with Sch2pcb .....................................................................................................8-4
8.2.3 Using the Sch2pcb Netlister ........................................................................................................8-5
8.2.4 Back-Annotating Your Design ....................................................................................................8-6
8.2.5 CapFast-PCB File Format ...........................................................................................................8-6
8.3 Preparing A Schematic for Netlisting in Racal-Redac’s CDI Format.................................................8-7
8.3.1 Assigning Reference Designators and Pin Numbers....................................................................8-7
8.3.2 Properties Used with Sch2red .....................................................................................................8-7
8.3.3 Using the Sch2red Netlister.........................................................................................................8-8
8.3.4 Redac CDI File Format ...............................................................................................................8-8
8.4 Preparing a Schematic for Netlisting in Scicards Format ...................................................................8-9
8.4.1 Assigning Reference Designators and Pin Numbers....................................................................8-9
8.4.2 Properties Used with Sch2sci ....................................................................................................8-10
8.4.3 Using the Sch2sci Netlister........................................................................................................8-10
8.4.4 Scicards Netlist File Format ......................................................................................................8-11
8.5 Preparing a Schematic for Netlisting to Tango-PCB Format............................................................8-11
8.5.1 Assigning Reference Designators and Pin Numbers..................................................................8-12
8.5.2 Properties Used with Sch2tgo....................................................................................................8-12
8.5.3 Using the Sch2tgo Netlister for Tango-PCB .............................................................................8-13
8.5.4 Sch2tgo Output File Format ......................................................................................................8-13
8.5.4.1 Component Section.............................................................................................................8-14
8.5.4.2 Net Section .........................................................................................................................8-14
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Chapter
8
Extracting PCB Netlists
This chapter shows you how to use the CapFast schematic packaging utility and describes
netlist extraction with the CapFast netlisters. The material in this chapter is an overview
of the procedures and tools that interface the CapFast schematic design system to printed
circuit board tools.
This chapter describes the following CapFast tools:
1.
Component Packager (Pkgr) — automatically annotates your design with pin
numbers and reference designators.
2.
PADS-PCB Interface (Sch2pcb) — extracts netlists in the CapFast-PCB and
PADS-PCB format and writes information to a file with the .asc extension.
This tool then takes information from PCB layout-generated .eco files and
automatically back-annotates your schematics.
3.
Racal-Redac Interface (Sch2red) — extracts netlists in the Redac Redboard
CDI format and writes the information to two files with .cdi extensions:
comp.cdi and conn.cdi.
4.
Scicards Interface (Sch2sci) — extracts netlists in the Scicards SCI format
and writes the information to a file with the .sci extension.
5.
Tango-PCB Interface (Sch2tgo) — extracts netlists in the Tango-PCB Series
II software format and writes the information to a file with a .net extension.
8.1 Schematic Packaging
The CapFast schematic packager, Pkgr, assigns reference designators and pin numbers to
all primitive symbols in the design, resulting in an association between each primitive
symbol and a physical package.
When you run the packager, the results are back-annotated (written) into your schematics.
Before back-annotation occurs, the current schematics are copied into a subdirectory
named ~/bak. If ~/bak does not exist, it will be created.
An important feature of Pkgr is that the number of schematic pages and hierarchical
levels it can handle is limited only by the amount of available memory. Please note that
no hierarchical schematic or hierarchical symbol representing a schematic may appear
more than once in the design. If it does, Pkgr produces an error message and stops the
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processing. Should this occur, the current schematics remain unchanged and no
schematics are copied in ~/bak. To work around this problem, each schematic that is
used multiple times, and its corresponding hierarchical symbol, must be copied to a
unique filename for each use. These new symbols can then be substituted for the
originals. Pkgr will then package the designs.
Pkgr will honor any pin number reference designator or information you put into the
schematics. Any pre-packaging you have done will be checked for consistency with the
information in the symbol. Any oddities found will cause Pkgr to produce the
appropriate warnings and stop the packaging process for that symbol. Pkgr does not
change any properties in the symbol that you have assigned.
Every property that is modified or added to the design by Pkgr will have the qualifier
(PKGR) prepended to it by default. See Chapter 6: Properties for more information on
property qualifiers. Unlike most CapFast tools, Pkgr does not recognize its own qualifier
by default. This makes it easier to re-package a design when you choose reference
designators and pin numbers. For example, a design may have already been run through
Pkgr when you decide the packaging must be modified. You can change reference
designators and pin numbers in the design with Schedit, making sure that any modified
properties do not have the (PKGR) qualifier. This creates a new set of packaging
information that incorporates your changes.
By default, if Pkgr assigns values to reference designator (ref) properties or pin
properties, the display status of those properties is set to Value Only.
The option -Q PKGR has been added to the cad.rc file entry for all of the PCB interface
tools. This ensures that the properties that Pkgr has added to the schematics will be used
by the netlisters.
8.1.1 Using Pkgr
To start Pkgr in Windows, double-click on the Pkgr icon in the CapFast for Windows
group, and then enter the options and filename. On UNIX, type:
pkgr [OPTIONS] FILENAME
where FILENAME must either be a design or a schematic file. The options that you may
use with Pkgr are described below.
-Q QUALIFIER-LIST
8-2
Specifies one or more qualifiers which are in effect for the
current run. The program matches qualifiers against the
properties in the schematic files and only those properties
which have matching qualifiers, or are not qualified, are
recognized by the program. See Chapter 6: Properties for
more information. There is no default qualifier.
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-v
Verbose output. Displays messages telling you what Pkgr is
doing. Also turns on the -f option.
-p PATHNAME
Specifies the path you want the program to use when searching
for data files, such as schematic or symbol files. See Appendix
A: Customizing CapFast for more information.
-A
Back-annotate to the properties without prepending the
qualifier (PKGR).
-B
Do not back-annotate the schematic.
-f
List the free gates.
-l LOG_FILE
Direct output messages to LOG_FILE, as well as to standard
output.
-S
The display status of new pin and reference designator
properties is set to the display status of current property, if one
existed, or OFF.
-rds
Place each gate into a different package. This is necessary for
interfacing to Royal Digital Scepter Systems PCB layout tools.
-ref STR1,#1...
Specifies the starting index for reference designators. For
example, giving Pkgr the option -ref U,100,R,50 causes
Pkgr to assign the first U reference designator as U100, the
second, as U101, etc. It also causes Pkgr to assign the first R
reference designator as R50, the second R51, etc. This option
will only affect those symbols with a reftype property that
has a value that is the same as STR1. For example, a STR1 of R
will only affect those symbols with a reftype R.
-u
Used to unpackage schematics. All (PKGR)-qualified
properties are removed. When used with the -A option, the
ref property becomes ref:*opt*. pin properties are set to 0
if there is a pinnumber property for them.
-d
Displays debugging messages.
8.2 Extracting a Netlist for CapFast-PCB and PADS-PCB
To generate a netlist to and back-annotate from CapFast-PCB and PADS-PCB, you use
the CapFast program Sch2pcb. Throughout this section when describing how to use
Sch2pcb, all references to CapFast-PCB will apply equally to PADS-PCB.
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Note: If you have used symbols from libraries other than those on the default path, you
must specify the path to those libraries in the control file called cad.rc. See Appendix
A: Customizing CapFast for more information on the cad.rc file.
8.2.1 Assigning Reference Designators and Pin Numbers
Before running a design through this netlister, be sure to assign reference designators and
pin numbers to all the components in the design. You can do this by hand or with the
CapFast packaging utility Pkgr. If reference designators are missing from the design, the
netlister generates errors and, in extreme cases, aborts.
8.2.2 Properties Used with Sch2pcb
Sch2pcb uses several symbol and wire properties to control extraction.
primitive
The value of a component’s primitive property is the name
of the component. The name identifies the component to the
PCB layout tool, which will use that name when looking for the
given component in its parts library. The component’s name
must match a name in the layout tool’s parts library or the
component is ignored.
value
The value of the value property specifies the value of certain
linear components to the PCB layout tool. The two main linear
components that use the value property are resistors and
capacitors. The value is appended to the name of the
component.
ref
All wiring in the netlist refers to a component by its reference
designator. The reference designator of a component is taken
from the value of its ref property. If the ref property of a
component has no value or does not exist, then the netlister
assumes the value UNKN. This assumption allows the netlist
generation to continue, but if too many components have the
reference designator UNKN, the layout tool becomes confused
and complains. You can use up to six alpha-numeric characters
to specify the value of the ref property; however, the first
character must be alphabetic.
pin, ppin
Wires are attached to the pins of components. To specify
which pin on a component has a wire attached to it, the pin’s
number is used. The number of the given pin is taken from the
value of its pin property or ppin property. If the desired pin
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property does not exist or has no value, an error is generated
and the netlister halts.
width
The trace width of a wire is specified by adding a width
property to the wire and then assigning the property a value
equal to the desired trace width. The default trace width output
by Sch2pcb is 12 units, except for power traces whose default
trace width is 50 units.
section, order
pinnumber, swap
These properties are used to check the validity of changes made
to the design during back-annotation.
For general information on these and other properties, see Chapter 6: Properties.
8.2.3 Using the Sch2pcb Netlister
When you have finished packaging your design, you can extract a netlist from it by
invoking Sch2pcb. You must use the following syntax.
sch2pcb [OPTIONS] FILENAME
where FILENAME is a design or a schematic file. The result of invoking Sch2pcb on your
design will be a netlist file, either FILENAME.asc, or NETLIST_FILE.asc, if you used
the -net NETLIST_FILE option. If the .asc file already exists, then Sch2pcb copies it
to the ~/bak subdirectory before it generates new output.
This netlist file can be read by the PADS-PCB layout tool using the “Ascii In” menu
command.
The options for Sch2pcb are described below.
-Q QUALIFIER-LIST
Specifies one or more qualifiers which are in effect for the
current run. The program matches qualifiers against the
properties in the schematic files and only those properties
which have matching qualifiers, or are not qualified, are
recognized by the program. See Chapter 6: Properties for
more information. The default qualifier, ASC, is always in
effect.
-v
Verbose output. Displays messages telling you what the
program is doing.
-p PATHNAME
Specifies the path you want the program to use when searching
for data files, such as schematic or symbol files. See Appendix
A: Customizing CapFast for more information.
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-net NETLIST_FILE
Causes Sch2pcb to produce a netlist file with the specified
name, first saving the previous copy of the named netlist file, if
it exists, in the ~/bak subdirectory.
-log LOG_FILE
Causes Sch2pcb to save error messages, reference designator
and node renaming messages, and any other information to the
specified LOG_FILE named. If a file of the same name exists,
the old file will be saved in the ~/bak subdirectory.
8.2.4 Back-Annotating Your Design
If an ECO file is generated during layout, any pin swapping, gate swapping, or reference
designator renaming information can be back-annotated to your schematics using
Sch2pcb with the -eco option. The syntax is as follows:
sch2pcb -eco ECO_FILE [OTHER OPTIONS] FILENAME
where FILENAME is a schematic or design file. [OTHER OPTIONS] can be any of the
options described in the Sch2pcb section. ECO_FILE is the name of the ECO file
generated during layout. The old schematics and netlist file are saved to the ~/bak
subdirectory.
8.2.5 CapFast-PCB File Format
Running Sch2pcb creates a file FILENAME.asc, where FILENAME is the schematic
filename argument to Sch2pcb. The file has two parts: the parts list and the netlist. The
parts list format is:
*PADS-PCB
*Part*
REF_DESIGNATOR
.
.
.
PART_IDENTIFIER
.
.
.
where REF_DESIGNATOR is the value of the ref property for a specific part,
PART_IDENTIFIER is the value of the primitive property. The netlist format is:
*Net
*Sig NODENAME
WIDTH
REF_DESIGNATOR.PIN_NUMBER
.
.
.
.
.
.
*End
8-6
REF_DESIGNATOR.PIN_NUMBER...
.
.
.
.
.
.
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where NODENAME is the connector or wire name, WIDTH is the value of the width
property or the default value described in the width property section, REF_DESIGNATOR
is the value of the ref property described above, and PIN_NUMBER is the appropriate pin
number.
8.3 Preparing A Schematic for Netlisting in Racal-Redac’s
CDI Format
This section explains how to prepare your schematic for translation to the Redac CDI
format. The CapFast program Sch2red extracts your design and creates a netlist.
Note: If you have used symbols from libraries other than those on the default path, you
must specify the path to those libraries in a special control file called cad.rc. See
Appendix A: Customizing CapFast for more information on the cad.rc file.
8.3.1 Assigning Reference Designators and Pin Numbers
Before running a design through this netlister, be sure to assign reference designators and
pin numbers to all the components in the design. You can do this by hand or with the
CapFast packaging utility Pkgr. If reference designators are missing from the design, the
netlister generates errors and, in extreme cases, aborts.
8.3.2 Properties Used with Sch2red
The schematic extractor Sch2red uses several symbol and wire properties to control
extraction.
pack
The value of a component’s pack property specifies the type of
package the PCB layout tool uses for the component. The type
of package specified must match one of the types the layout
tool has in its library.
ref
All wiring in the netlist refers to a component by its reference
designator. The reference designator of a component is taken
from the value of its ref property. If the ref property of a
component has no value or does not exist, then the netlister
assumes the value UNKN. This assumption allows the netlist
generation to continue, but if too many components have the
reference designator UNKN, the layout tool becomes confused
and complains. You can use up to six alpha-numeric characters
to specify the value of the ref property; however, the first
character must be alphabetic.
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pin
ppin
Wires are attached to the pins of components. To specify
which pin on a component has a wire attached to it, the pin’s
number is used. The number of the given pin is taken from the
value of its pin property or ppin property. If the desired pin
property does not exist or has no value, an error is generated
and the netlister halts.
code
The trace width of a wire is specified by adding a code
property to the wire and then assigning that property a value
equal to the desired trace width. The default trace width output
by Sch2red is 2 units, except for power traces whose default
trace width is 5 units.
For more information on these and other properties, see Chapter 6: Properties.
8.3.3 Using the Sch2red Netlister
The Sch2red utility translates schematic files to the Redac CDI format. The syntax is:
sch2red [OPTIONS] FILENAME
where FILENAME is the top-level schematic or design file. Sch2red reads either
schematic or design files and produces netlist files that have the .cdi suffix.
The following options are available:
-Q QUALIFIER-LIST
Specifies one or more qualifiers which are in effect for the
current run. The program matches qualifiers against the
properties in the schematic files and only those properties
which have matching qualifiers, or are not qualified, are
recognized by the program. See Chapter 6: Properties for
more information. The default qualifier is RED.
-v
Verbose output. Displays messages telling you what the
program is doing.
-p PATHNAME
Specifies the path you want the program to use when searching
for data files, such as schematic or symbol files. See Appendix
A: Customizing CapFast for more information.
8.3.4 Redac CDI File Format
Two files with the extension .cdi are created, conn.cdi and comp.cdi. The file
comp.cdi contains a list of the schematic component parts and their shapes, and has the
following format:
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.pcb
.com
REF_DESIGNATOR
.
.
.
.EOD
Extracting PCB Netlists
PACKAGE_TYPE
.
.
.
where REF_DESIGNATOR is the value of the ref property for a specific part,
PACKAGE_TYPE is the value of the pack property, and the .EOD signifies the end of the
component file. The file conn.cdi contains the list of connections for the design in the
following format:
.pcb
.con
.cod TRACE_CODE
.rem NODENAME
REF_DESIGNATOR PIN_NUMBER
.
.
.
.
.
.
.EOD
REF_DESIGNATOR PIN_NUMBER...
.
.
.
.
.
.
where NODENAME is the connector or wire name, TRACE_CODE is the value of the code
property or the default value described in the section on code in Chapter 6: Properties.
REF_DESIGNATOR is the value of the ref property, and PIN_NUMBER is the appropriate
pin number.
8.4 Preparing a Schematic for Netlisting in Scicards Format
This section explains how to prepare a schematic for extraction to the Scicards SCI
format using the CapFast program Sch2sci.
Note: If you have used symbols from libraries other than those on the default path, you
must specify the path to those libraries in a special control file called cad.rc. See
Appendix A: Customizing CapFast for more information on the cad.rc file.
8.4.1 Assigning Reference Designators and Pin Numbers
Before running a design through this netlister, be sure to assign reference designators and
pin numbers to all the components in the design. You can do this by hand or with the
CapFast packaging utility Pkgr. If reference designators are missing from the design, the
netlister generates errors and, in extreme cases, aborts.
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8.4.2 Properties Used with Sch2sci
Properties recognized by the Sch2sci netlister are:
pack
The value of a component’s pack property specifies the type of
package the PCB layout tool uses for the component. The type
of package specified must match one of the types the layout
tool has in its library.
ref
All wiring in the netlist refers to a component by its reference
designator. The reference designator of a component is taken
from the value of its ref property. If the ref property of a
component has no value or does not exist, then the netlister
assumes the value UNKN. This assumption allows the netlist
generation to continue, but if too many components have the
reference designator UNKN, the layout tool becomes confused
and complains. You can use up to six alpha-numeric characters
to specify the value of the ref property; however, the first
character must be alphabetic.
pin
ppin
Wires are attached to the pins of components. To specify
which pin on a component has a wire attached to it, the pin’s
number is used. The number of the given pin is taken from the
value of its pin property or ppin property. If the desired pin
property does not exist or has no value, an error is generated
and the netlister halts.
For more information on these and other properties see Chapter 6: Properties.
8.4.3 Using the Sch2sci Netlister
The Sch2sci utility translates the schematic file to the SCI format.
The syntax is:
sch2sci [OPTIONS] FILENAME
where FILENAME is the top level schematic or design file. Sch2sci reads either schematic
or design files and produces netlist files which have the .sci suffix.
The following options are available:
-Q QUALIFIER-LIST
8-10
Specifies one or more qualifiers which are in effect for the
current run. The program matches qualifiers against the
properties in the schematic files and only those properties
which have matching qualifiers, or are not qualified, are
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recognized by the program. See Chapter 6: Properties for
more information. The default qualifier is SCI.
-v
Verbose output. Displays messages telling you what the
program is doing.
-p PATHNAME
Specifies the path you want the program to use when searching
for data files, such as schematic or symbol files. See Appendix
A: Customizing CapFast for more information.
8.4.4 Scicards Netlist File Format
A file with the extension .sci is created. It has two parts, the parts list and the net list.
PARTS LIST
PART_IDENTIFIER PACKAGE_TYPE REF_DESIGNATOR
.
.
.
.
.
.
.
.
.
EOS
where PART-IDENTIFIER is the value of the primitive property, PACKAGE_TYPE is
the value of the pack property, and REF_DESIGNATOR is the value of the ref property
for a specific part. EOS signifies the end of part list.
NET LIST
NN NODENAME $
REF_DESIGNATOR PIN_NUMBER
NN NODENAME $
REF_DESIGNATOR PIN_NUMBER
.
.
.
.
.
.
EOS
REF_DESIGNATOR
PIN_NUMBER...$
REF_DESIGNATOR
.
.
.
PIN_NUMBER...$
.
.
.
where NODENAME is the connector or wire name, REF_DESIGNATOR is the value of the
ref property, and PIN_NUMBER is the appropriate pin number. There may be up to five
REF_DESIGNATORS on one line in the parts list section.
8.5 Preparing a Schematic for Netlisting to Tango-PCB
Format
The CapFast Sch2tgo allows you to interface your CapFast schematic with the TangoPCB Series II software. The netlister automatically generates a list of connections found
within your CapFast schematic in a format that can be understood by Tango. This section
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shows you the properties recognized by the CapFast Sch2tgo and how to use the
command line options when you invoke the interface program.
Note: If you have used symbols from libraries other than those on the default path, you
must specify the path to those libraries in a special control file called cad.rc. See
Appendix A: Customizing CapFast for more information on the cad.rc file.
8.5.1 Assigning Reference Designators and Pin Numbers
Before running a design through this netlister, be sure to assign reference designators and
pin numbers to all the components in the design. You can do this by hand or with the
CapFast packaging utility Pkgr. If reference designators are missing from the design, the
netlister generates errors and, in extreme cases, aborts.
8.5.2 Properties Used with Sch2tgo
The Tango-PCB extractor uses several symbol and wire properties to control extraction as
explained below.
ref
All wiring in the netlist refers to a component by its reference
designator. The reference designator of a component is taken
from the value of its ref property. If the ref property of a
component has no value or does not exist, then the netlister
assumes the value UNKN. This assumption allows the netlist
generation to continue, but if too many components have the
reference designator UNKN, the layout tool becomes confused
and complains. You can use up to six alpha-numeric characters
to specify the value of the ref property; however, the first
character must be alphabetic.
pin
ppin
Wires are attached to the pins of components. To specify
which pin on a component has a wire attached to it, the pin’s
number is used. The number of the given pin is taken from the
value of its pin property or ppin property. If the desired pin
property does not exist or has no value, an error is generated
and the netlister halts.
For more information on these and other properties see Chapter 6: Properties.
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8.5.3 Using the Sch2tgo Netlister for Tango-PCB
When you have finished packaging your design, either by hand or by using the Pkgr
utility, you can extract a netlist from it by invoking Sch2tgo. You must use the following
syntax.
sch2tgo [OPTIONS] FILENAME
where FILENAME is a design or schematic file. The result of invoking Sch2tgo on your
design will be a netlist file, named either FILENAME.net, or if you used the -net
NETLIST_FILE option, NETLIST_FILE.net. This netlist file can be read by the
Tango-PCB layout tool using the “Net/Load” menu command. The .net file is
described in the next section.
The options for Sch2tgo are described below.
-Q QUALIFIER-LIST
Specifies one or more qualifiers which are in effect for the
current run. The program matches qualifiers against the
properties in the schematic files and only those properties
which have matching qualifiers, or are not qualified, are
recognized by the program. See Chapter 6: Properties for
more information. The default qualifier, TGO, is always in
effect.
-v
Verbose output. Displays messages telling you what the
program is doing.
-p PATHNAME
Specifies the path you want the program to use when searching
for data files, such as schematic or symbol files. See Appendix
A: Customizing CapFast for more information.
-net NETLIST_FILE
Causes Sch2tgo to produce a netlist file with the specified
name, first saving the previous copy of the named netlist file, if
it exists, in the ~/bak subdirectory.
-log LOG_FILE
Causes Sch2tgo to save error messages, reference designator
and node renaming messages, and any other information to the
specified file. If a file of the same name exists, the old file will
be saved in the ~/bak subdirectory.
8.5.4 Sch2tgo Output File Format
The output .net file is divided into two sections: the component section and the net
section.
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8.5.4.1 Component Section
The component section contains the description of each component in the design. The
beginning and end of each component’s description is marked by square brackets as
shown below.
[
REFDES
PACKAGE
TYPE
]
where REFDES is the component’s reference designator, taken from the value of its ref
property, PACKAGE is the component’s package, taken from the value of the pack
property, and TYPE is the component’s type, taken from the value of the primitive
property.
Note: As of January, 1990, Tango-PCB Series II ignores the component section of the
.net file.
8.5.4.2 Net Section
The net section of the output immediately follows the component section. A net is a list
of all nodes that are connected together. The beginning and end of each net’s description
is marked by parenthesis as shown below.
(
NET_NAME
REFDES, PIN_NUM
REFDES, PIN_NUM
.
.
.
REFDES, PIN_NUM
)
where NET_NAME is the name of the net (usually the name of the wire or connector which
connects the listed pins), REFDES and PIN_NUM are the reference designator and pin
designator, respectively, of a component connected to the node. Note that REFDES is
taken from the value of the component’s ref property and PIN_NUM is the value of one
of the component’s pin or ppin properties.
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