Vol 5 Issue 8 Sept 2015
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Indian Streams Research Journal
ISSN 2230-7850
Impact Factor : 3.1560(UIF)
Volume - 5 | Issue - 8 | Sept - 2015
ANALYSIS OF VARIABLE SPEED PFC BUCK–BOOST
CONVERTER-FED PMBLDC MOTOR DRIVE
1
2
K. Raghavareddy and K. Satish Kumar
M.Tech
2
Assistant Professor, Dept of EEE ,Brahmaiah College of Engineering,
SPSR Nellore,A.P.
1
ABSTRACT
This paper presents an analysis of variable speed low power drive with PFC at supply ends by
using BLDC PM motor fed from buck-boost converter. The speed control of BLDC achieved by simply
control the DC link voltage of VSI converter which is taken as reference signal. This facilitates the
operation of VSI at fundamental frequency switching by using the electronic commutation of the BLDC
motor which offers reduced switching losses. A PFC buck–boost converter is designed to operate in
discontinuous inductor current mode (DICM) to provide an inherent PFC at ac mains. The performance
of the proposed drive is evaluated over a wide range of speed control and varying supply voltages
(universal ac mains at 170–270 V) with improved power quality at ac mains. The obtained power
quality indices are within the acceptable limits of international power quality standards such as the IEC
61000-3-2. The performance of the proposed drive is simulated in MATLAB/Simulink environment,
and the obtained results are validated experimentally on a developed prototype of the drive.
KEYWORDS :buck–boost converter, brush less direct current (BLDC) motor, discontinuous inductor
current mode (DICM), power factor corrected (PFC), power quality.
INTRODUCTION :
The many advantages of PMBLDC motors,
combined with their rapidly decreasing
cost, have led to their widespread
applications in many variable-speed drives.
Their high power density makes them ideal
candidates for applications such as robotic
actuators, computer disk drives, and office
equipment. With their high efficiency, high
power factor, and maintenance-free
operation, domestic appliances and
heating, ventilating, and air conditioning
(HVAC) equipment are now increasingly
employing BLDC motors in preference to DC
and induction motors. They are also being developed for automotive applications such as electric
power steering, power accessories, and active suspension, in addition to vehicle propulsion.
A PMBLDCM which is a kind of three-phase synchronous motor with permanent magnets
(PMs) on the rotor and trapezoidal back EMF waveform operates on electronic commutation
accomplished by solid state switches. It is powered through a three-phase voltage source inverter
(VSI) which is fed from single-phase AC supply using a diode bridge rectifier (DBR) followed by
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ANALYSIS OF VARIABLE SPEED PFC BUCK–BOOST CONVERTER-FED PMBLDC MOTOR DRIVE
smoothening DC link capacitor. The low power drive exerts constant torque (i.e. rated torque) on the
PMBLDCM and is operated in speed Control mode to improve the efficiency of the low power drives.
Since, the back- emf of the PMBLDCM is proportional to the motor speed and the developed torque is
proportional to its phase current [1-4], therefore, a constant torque is maintained by a constant
current in the stator winding of the PMBLDCM whereas the speed can be controlled by varying the
terminal voltage of the motor. Based on this logic, a speed control scheme is proposed in this paper
which uses a reference voltage at DC link proportional to the desired speed of the PMBLDC motor.
However, the control of VSI is only for electronic commutation which is based on the rotor position
signals of the PMBLDC motor.
The PMBLDCM drive, fed from a single-phase AC mains through a diode bridge rectifier (DBR)
followed by a DC link capacitor, suffers from power quality (PQ) disturbances such as poor power factor
(PF), increased total harmonic distortion (THD) of current at input AC mains and its high crest factor
(CF). It is mainly due to uncontrolled charging of the DC link capacitor which results in a pulsed current
waveform having a peak value higher than the amplitude of the fundamental input current at AC mains.
Moreover, the PQ standards for low power equipment’s such as IEC 61000-3-2 [5], emphasize on low
harmonic contents and near unity power factor current to be drawn from AC mains by these motors.
Therefore, use of a power factor correction (PFC) topology amongst various available topologies [6-14]
is almost inevitable for a PMBLDCM drive.
Most of the existing systems use a boost converter for PFC as the front-end converter and an
isolated DC-DC converter to produce desired output voltage constituting a two-stage PFC drive [7-8].
The DC-DC converter used in the second stage is usually a fly back or forward converter for low power
applications and a full-bridge converter for higher power applications. However, these two stage PFC
converters have high cost and complexity in implementing two separate switch-mode converters,
therefore a single stage converter combining the PFC and voltage regulation at DC link is more in
demand. The single-stage PFC converters operate with only one controller to regulate the DC link
voltage along with the power factor correction. The absence of a second controller has a greater impact
on the performance of single-stage PFC converters and requires a design to operate over a much wider
range of operating conditions. [7-8].
The DC-DC converter used in the second stage is usually a fly back or forward converter for low
power applications and a full-bridge converter for higher power applications. However, these two stage
PFC converters have high cost and complexity in implementing two separate switch-mode converters,
therefore a single Stage converter combining the PFC and voltage regulation at DC link is more in
demand. The single-stage PFC converters operate with only one controller to regulate the DC link
voltage along with the power factor correction.
The absence of a second controller has a greater impact on the performance of single-stage PFC
converters and requires a design to operate over a much wider range of operating Conditions. For the
proposed voltage controlled drive, a half bridge buck boost DC-DC converter with HF isolation is
selected because of its high power handling capacity with high degree of reduction transformer losses
as compared to the single switch converters. Moreover, it has switching Losses comparable to the single
switch converter as only one switch is in operation at any instant of time. It can be operated as a singlestage power factor corrected (PFC) converter when connected between the VSI and the DBR fed from
single-phase AC mains, besides controlling the voltage at DC link for desired speed of the low power
factor drive. Detailed modeling design and performance evaluations of the proposed drive are
presented for a low power factor drive driven by a PMBLDC motor of 2.5KW, 1500 rpm rating.
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ANALYSIS OF VARIABLE SPEED PFC BUCK–BOOST CONVERTER-FED PMBLDC MOTOR DRIVE
III.PROPOSED SPEED CONTROL SCHEME OF PMBLDC MOTOR FOR LOW POWER DRIVES
The proposed speed control scheme (as shown in Fig.1)controls reference voltage at DC link as
an equivalent reference speed, thereby replaces the conventional control of the motor speed and a
stator current involving various sensors for voltage and current signals. Moreover, the rotor position
signals are used to generate the switching sequence for the VSI as an electronic commutator of the
PMBLDC motor. Therefore, rotor-position information is required only at the commutation points, e.g.,
every 60°electrical in the three-phase [1-4]. The rotor position of PMBLDCM is sensed using Hall effect
position sensors and used to generate switching sequence for the VSI as shown in Table-I.
The DC link voltage is controlled by a half-bridge buck DC-DC converter based on the duty ratio
(D) of the converter. For a fast and effective control with reduced size of magnetics and filters, a high
switching frequency is used; however, the switching frequency (fs) is limited by the switching device
used, operating power level and switching losses of the device. Metal oxide field effect transistors
(MOSFETs) are used as the switching device for high switching frequency in the proposed PFC converter.
However, insulated gate bipolar transistors (IGBTs) are used in VSI Bridge feeding PMBLDCM, to reduce
the switching stress, as it operates at lower frequency compared to PFC switches. The PFC control
scheme uses a current control loop inside the speed control loop with current multiplier approach
which operates in continuous conduction mode (CCM) with average current control. The control loop
begins with the comparison of sensed DC link voltage with a voltage equivalent to the reference speed.
The resultant voltage error is passed through a proportional-integral (PI) controller to give the
modulating current signal. This signal is multiplied with a unit template of input AC voltage and
compared with DC current sensed after the DBR. The resultant current error is amplified and compared
with saw-tooth carrier wave of fixed frequency in uni polar scheme (as shown in Fig.2) to generate the
PWM pulses for the half-bridge converter.
Fig.1. Control schematic of Proposed Bridge-buck boost PFC converter fed PMBLDCM Drive
The proposed PFC buck half-bridge converter is designed for a PMBLDCM drive with main
considerations on PQ constraints at AC mains and allowable ripple in DC link voltage. The DC link voltage
of the PFC converter is given as,
Vdc = 2 (N2/N1) Vin D and N2= N21=N22
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(1)
3
ANALYSIS OF VARIABLE SPEED PFC BUCK–BOOST CONVERTER-FED PMBLDC MOTOR DRIVE
where N1, N21, N22 are number of turns in primary, secondary upper and lower windings of the
high frequency (HF) isolation transformer, respectively
Fig. 2. PWM control of the buck half-bridge Converter
Vin is the average output of the DBR for a give
AC input Voltage (VS) related as
Vin=2√(2
)
Vs/π
(2)
A ripple filter is designed to reduce the ripples introduced in the output voltage due to high
switching frequency for constant of the buck half-bridge converter. The inductance (L0) of the ripple
filter restricts the inductor peak to peak ripple current (ΔIL0) with in specified value for the given
switching frequency (fs), where, the capacitance (Cd) is calculated for a specified ripple in the output
voltage (ΔVCd) [7-8].
The output filter inductor and capacitor are given as,
L0 = (0.5-D) Vdc / {fs(ΔIL0)
(3)
Cd=I0/ (2ωΔVCd)
(4)
TABLE I: VSI SWITCHING SEQUENCE BASED ON THE HALL EFFECT SENSOR SINGNALS
Available online at www.lsrj.in
Ha
Hb
Hc
Ea
Eb
Ec
S1
S2
S3
S4
S5
S6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
-1
0
0
0
1
1
0
0
1
0
-1
0
1
1
0
0
0
0
1
1
-1
0
1
0
0
1
0
1
0
0
1
0
-1
1
0
0
0
0
1
1
0
1
1
-1
0
1
0
0
1
0
0
1
1
0
0
1
-1
0
0
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
4
ANALYSIS OF VARIABLE SPEED PFC BUCK–BOOST CONVERTER-FED PMBLDC MOTOR DRIVE
IV. MODELLING OF THE PROPOSED PMBLDCM DRIVE:
The main components of the proposed PMBLDC drive are the PFC converter and PMBLDC drive,
which are modeled by mathematical equations and the complete drive is represented as a combination
of the these models.
A.PFC Converter:
The modeling of the PFC converter consists of the modeling of a speed controller, a reference
current generator and a PWM controller as given below.
1)Speed Controller:
The speed controller, the prime component of this control scheme, is a proportional-integral
(PI) controller
Which closely tracks the reference speed as an equivalent reference voltage. If the Kth instant of
time, V*dc(k) is reference DC link voltage,Vdc(K) is sensed DC link voltage then the voltage error
Ve(K) is calculated as
Ve(k)=V*dc(k)-Vdc(k)
(5)
The PI controller gives desired control signal after processing this Violated error. The output of
the controller Ic(k) at k th instant is given as,
Ic(k) = Ic (k-1) + Kp {Ve (k) – Ve (k-1)} + KiVe (k)
(6)
Where Kp and Ki are the proportional and integral gains of the PI controller.
2) Reference Current Generator: The reference input current of PFC converter is denoted by idc* and
given as,
I*dc = Ic (k) uVs
(7)
Where uVs is the unit template of the voltage at input AC mains, Calculated as,
uVs-vd/Vsm, vd = mod (v); vs = Vsm sinùt
(8)
where Vsm is the amplitude of the voltage and ? is frequency rad/sec at AC mains.
3) PWM Controller:
The reference input current of the buck half-bridge converter (idc*) is compared with its sensed
current (idc) to generated the current error ? idc = (idc* - idc). This current error is amplified by gain kdc and
compared with fixed frequency(fs) saw-tooth Carrier waveform md(t) (as shown in Fig.2) in uni polar
switching mode [7] to get the switching signals for the MOSFETs of the PFC buck half-bridge converter
as
If
kdc ? idc > md(t)
then SA=0
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(9)
5
ANALYSIS OF VARIABLE SPEED PFC BUCK–BOOST CONVERTER-FED PMBLDC MOTOR DRIVE
If - kdc ? idc > md(t)
then SB=0
(10)
Where SA, SB are upper and lower switches of the half-bridge converter as shown in Fig. 1 and
their values ‘1’ and ‘0’ represented ‘on’ and ‘off’ position of the respective MOSFET of the PFC
converter.
B) PMBLDC drive:
The PMBLDCM drive consists of an electronic Commutator, a VSI and a PMBLDC motor.
1)Electronic Commutator: The electronic commutator uses signals from Hall effect position sensors to
generate the switching sequence for the voltage source inverter based on the logic in Table-I
2)Voltage source converter: Fig. 3 shows an equivalent circuit of a VSI fed PMBLDC. The output of VSI to
be fed to phase ‘a’ of the BLDC motor is given as,
va0 = (Vdc/2)
for S1 = 1
va0 = (-Vdc/2)
for S2 = 1
va0 = 0 for S1 = 0 and S2 = 0
van = va0 – vn0
(11)
(12)
(13)
(14)
where va0,vb0,vc0 and vn0 are voltages of the three-phases and neutral point (n) with respect to
virtual mid-point of the DC link voltage shown as ‘o’ in Fig, 3. The voltages van, vbn, vcn are voltages of
three phases with respect to neutral point(n) and Vdc is the DC link voltage. S=1 and 0 represent ‘on’ and
‘off’ position of respective IGBTs of the VSI and considered in a similar way for the other IGBTs of the VSI
i.e. S3 – S6. Using similar logic vb0,vc0, vbn, vcn are generated for the other two phases of the VSI feeding
PMBLDC motor.
3)PMBLDC Motor:
The PMBLDCM is represented in the form of a set of differential equations [3] given as,
Van = Ria + p?a + ean
Vbn = Rib +p?b + ebn
Vcn = Ric + p?c +ecn
(15)
(16)
(17)
Where p is a differential operator (d/dt), ia, ib, ic are three-phase currents, ?a, ?b, ?c are flux
linkages and ean, ebn, ecn are phase to neutral back emfs of PMBLDC, in respective phases, R is resistance
of motor windings/phase
Fig. 3. Equivalent Circuit of a VSI fed PMBLDCM Drive
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6
ANALYSIS OF VARIABLE SPEED PFC BUCK–BOOST CONVERTER-FED PMBLDC MOTOR DRIVE
The flux linkages are represented as,
ëa = Lia – M (ib+ic)
?b = Lib – M (ia+ic)
?c = Lic – M (ib + ia)
(18)
(19)
(20)
Where L is self-inductance/phase, M is mutual inductance of motor winding/phase. Since the
PMBLDC has no neutral connection, therefore,
ia + ib + ic = 0
(21)
From Eqs. (14-21) the voltage between neutral terminals (n) and mid-point of the DC link (0) is
given as,
Vn0 = {Va0 + Vb0 + Vc0 – (ean +ebn +ecn)}/3
(22)
From Eqs. (18-21), the flux linkages are given as,
?a = (L+M) ia, ?b = (L+M) ib, ?c = (L+M) ic,
(23)
From Eqs.(15-17 and 23), the current derivatives in Generalized state space form is given as,
Pix = (Vxn – ix R – exn)/(L+M)
(24)
Where x represents phase a, b or c.
The developed electromagnetic torque Te in the PMBLDC is given as,
Te = (ean ia + ebn ib + ecn ic)/?
(25)
Where ? is motor speed in rad/sec,
The back emfs may be expressed as function of rotor position (?) as,
Exn = Kb ?x(?)?
(26)
Where x can be phase a, b or c and accordingly ?x(?) represents function of rotor position with a
maximum value ±1, identical to trapezoidal induced emf Given as,
?a(?) = 1 form0 < ? < 2p/3
?a(?) = {(6/ p )( p - ? }-1 for 2p/3 < ? < p
?a(?) = -1 form p < ? < 5p/3
?a(?) = {(6/ p )( p - ? }+1 for 5p/3 < ? < 2p
(27)
(28)
(29)
(30)
The functions ?b(?) and ?b(?) are similar to ?a(?) with a phase difference of 1200 and 2400
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7
ANALYSIS OF VARIABLE SPEED PFC BUCK–BOOST CONVERTER-FED PMBLDC MOTOR DRIVE
respectively.
Therefore, the electromagnetic torque is expressed as,
Te = Kb{ ?a(?) ia + ?b(?) ib + ?c(?) ic}
(31)
The mechanical equation of motion in speed derivative form is given as,
P? = (p/2) (Te-TL - B? )/(J)
P? = ?
(32)
(33)
Where P is no. poles, TL is load torque in Nm, J is moment of inertia in kg-m2 and B is friction
coefficient in Nms/Rad.
These equations (15-33) represent the dynamic model of the PMBLDC motor.
V. PERFORMANCE EVALUATION OF PROPOSED PFC DRIVE:
The proposed PMBLDCM drive is modeled in Matlab-Simulink environment and evaluated for a
low power drive. The proposed drive performance is evaluated based on the performance of the BLDC
motor and BL buck–boost converter and also from the power quality indices achieved at ac mains. The
performance of present system completely analyzed by three different conditions. They are steady
state, transient state and supply voltage variation and their corresponding parameter evaluation. The
Simulink model for proposed system Shown in the figure 4. The Simulink parameters are shown in the
Table IV.
Fig. 4: Simulink model proposed analysis of variable Speed Buck-Boost
converter fed BLDC motor drive
1)Steady State Condition:
The speed control of the PMBLDCM driven low power drive under steady state condition is
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8
ANALYSIS OF VARIABLE SPEED PFC BUCK–BOOST CONVERTER-FED PMBLDC MOTOR DRIVE
carried out for different speeds and the results are shown in Figs. 5a-c and Current waveform at AC
mains and Harmonic spectra of the PMBLDCM drive under steady state condition at rated torque and
220 V AC at 900 rpm is shown in Fig.6.The effectiveness of the proposed drive in wide speed range with
various PQ parameters such as THDi, DPF, PF is summarized in Table-II .Nearly unity power factor (PF)
and reduced THD of AC mains current are observed in wide speed range of the PMBLDCM as shown in
Table-II. Figs.5a-c show voltage(Vss) and current (Iss) waveforms at AC mains, DC link voltage(Vdc), speed
of the motor (N), developed electromagnetic torque of the motor (Te), the stator current of the
PMBLDC motor for phase ‘a’ (Ia), and shaft power output (Po) at 300 rpm,900 rpm and 1500 rpm speeds.
Fig.5. Performance of the PMBLDCM drive under steady state condition at 220 V AC input
Fig.5a: Performance of the PMBLDCM drive at 300 rpm
Figure 5b: Performance of the PMBLDCM drive at 900 rpm
Figure 5c: Performance of the PMBLDCM drive at 1500 rpm
Since the reference speed is transformed into equivalent voltage which is further generates the
reference voltage at DC link, it is observed that the control of the reference DC link voltage controls the
speed of the motor instantaneously.
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ANALYSIS OF VARIABLE SPEED PFC BUCK–BOOST CONVERTER-FED PMBLDC MOTOR DRIVE
TABLE.II. PERFORMANCEOFDRIVEUNDER SPEED CONTROL AT 220V AC INPUT
Speed(r
pm)
V DC
(V)
T HD i
(% )
DPF
PF
ISS
3 00
1 06
5.18
0.99 99
0.99 935
2.6
4 00
1 31
3.85
0.99 99
0.99 921
3.2
5 00
1 57
2.95
0.99 99
0.99 940
3.9
6 00
1 83
2.98
0.99 99
0.99 958
4.6
7 00
2 09
2.69
0.99 99
0.99 963
5.3
8 00
2 36
2.45
0.99 99
0.99 965
5.9
9 00
2 63
2.3
0.99 99
0.99 966
6.6
1 00 0
2 88
2.22
0.99 99
0.99 972
7.2
1 10 0
3 14
2.05
0.99 99
0.99 980
8
1 20 0
3 42
2.03
0.99 99
0.99 980
8.7
1 30 0
3 68
2.04
0.99 99
0.99 978
9.4
1 40 0
3 94
2.06
0.99 99
0.99 980
10 .1
1 50 0
4 20
2.09
0.99 99
0.99 980
10 .8
Figure6. Current waveform at AC mains and Harmonic spectra of the PMBLDCM drive under
steady state condition at rated torque and 220 V AC at 900 rpm
1)Transient Condition:
Figs.7a-c show the performance of the drive during starting and the under speed control of the
low power drive. The reference speed is changed from 900 rpm to 1500 rpm for the rated load
performance of the low power drive; from 900 rpm to300 rpm for performance of the low power drive
at light load. It is observed that the speed control is fast and smooth in either direction i.e. acceleration
or retardation with power-factor maintained at nearly unity value.
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ANALYSIS OF VARIABLE SPEED PFC BUCK–BOOST CONVERTER-FED PMBLDC MOTOR DRIVE
Fig .7a. Starting performance of the PMBLDCM drive at 900 rpm
Fig.7b.PMBLDCM drive under speed variation from 900rpm to 1500 rpm.
Fig.7c.PMBLDCM drive under speed variation 900 rpm to 300 rpm
3) Performance under Variable Input AC Voltage:
Performance evaluation of the proposed PMBLDCM drive is carried out under varying input AC
voltage at rated load (i.e. rated torque and rated speed) to demonstrate the operation of proposed
PMBLDCM drive for low power system in various practical situations as summarized in Table-III.
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ANALYSIS OF VARIABLE SPEED PFC BUCK–BOOST CONVERTER-FED PMBLDC MOTOR DRIVE
TABLE III: VARIATION OF PQ PARAMETERS WITH AC INPUT VOLTAGE (VS) AT 1500 RPM
AT RATED VDC (420V)
V AC
(V)
T HD i
(%)
DPF
PF
CF
Is(A)
170
2.76
0.9999
0.9998
1.41
8.29
180
2.56
0.9999
0.99975
1.41
8.76
190
2.40
0.9999
0.99976
1.41
9.28
200
2.32
0.9999
0.99979
1.41
9.77
210
2.25
0.9999
0.99975
1.41
10.27
220
2.09
0.9999
0.99980
1.41
10.8
230
2.03
0.9999
0.99980
1.41
11.28
240
1.97
1.0000
0.99980
1.41
11.8
250
1.86
1.0000
0.99978
1.41
12.3
260
1.74
1.0000
0.99982
1.41
12.8
270
1.71
1.0000
0.99983
1.41
13.3
TABLE IV: Simulation Parameters
Rated power
Rated speed
Pole pairs
Stator resistance
Stator inductance(L+M)
Inertia constant(J)
Dc link capacitor
2.5 KW
1500 rpm
4
2.875Ù/ph
8.5mH/ph
2
0.00125Kgm
6000µf
PI controller gains
Kp =0.1,Ki=1
CONCLUSION
A new speed control strategy of a PMBLDCM drive is validated for a low power drives which uses
the reference speed as an equivalent reference voltage at DC link. The speed control is directly
proportional to the voltage control at DC link. The additional PFC feature to the proposed drive ensures
nearly unity PF in wide range of speed and input AC voltage. Moreover, power quality parameters of the
proposed PMBLDCM drive are in conformity to an International standard IEC 61000-3-2 [5]. The
proposed drive has demonstrated good speed control with energy efficient operation of the drive
system in the wide range of speed and input AC voltage. The proposed drive has been found as a
promising candidate for a PMBLDCM driving load in 2-2.5kw power range.
REFERENCES
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oct. 2003.
Available online at www.lsrj.in
12
ANALYSIS OF VARIABLE SPEED PFC BUCK–BOOST CONVERTER-FED PMBLDC MOTOR DRIVE
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Design,” John Wiley, USA, 1995.
[8]A. I. Pressman, Switching Power Supply Design, McGraw Hill, New York, 1998.
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[12]A. Fernandez, J. Sebastian, M.M. Hernando and P. Villegas, “Small signal modelling of a half bridge
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frequency isolation on-line UPS system for low power applications,” in Proc. IEEE APEC’08, 2008,
pp.1296 – 1302.
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