TI Precision ADC Solutions
Mete YASAN
EMPA
Agenda
• Key Terminology
• SAR Topology and Front End Signal Conditioning
• New SAR ADCs
• Delta Sigma Topology and Front End Signal Conditioning
• New Delta Sigma ADCs
• Isolated Delta Sigma Modulators
• Summary
Sampling Frequency and Resolution
• Sampling Frequency: Speed which samples are measured and converted.
– Sampling frequency is measured in samples per second (SPS)
– Remember Nyquist and Shannon? This is it!
• Resolution: Number of digital bits that the data converter will use.
– The resolution determines the granularity a data converter can identify an analog
signal. For instance, a 12-bit data converter will have 212 different voltage levels it
can identify.
• Throughput: Throughput is the amount of digital data a converter uses in a
given amount of time.
– A 12-bit converter running at 100kSPS has a 1.2Mbps throughput. This is also true
for a 10-bit converter running at 120kSPS.
AC Specifications
Six popular specifications for quantifying ADC dynamic
performance are:
•
•
•
•
•
•
SINAD (signal-to-noise-and-distortion ratio),
ENOB (effective number of bits),
SNR (signal-to-noise ratio),
THD (total harmonic distortion),
THD + N (total harmonic distortion plus noise),
SFDR (spurious free dynamic range).
Amplitude (dB)
AC Performance – SNR, SFDR, THD
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
Signal Being Digitized
SFDR
SNR
THD ––Total
Signal
Spurious
Harmonic
to Noise
Free Dynamic
Distortion
Ratio
Range
Harmonic Distortion
Noise Floor
0
1k
2k
3k
4k
5k
6k
7k
Frequency / Hz
8k
9k
10k
ADC Input Structures:
Muxed vs. Simultaneous Inputs
ADS8568 - Simultaneous
ADS795x – Mux’ed
Also, of interest for this ADS795X, the MX0 to AINP path, enables
you to consolidate common input signaling circuitry down to a
single instance. Look for this on other TI devices too!
ADC Input Structures:
Single-Ended (SE) & Differential (DE)
Single-Ended Input (SE)
+ fs
Input
Vcm
IN
ADC
- fs
IN
Differential Input (DE)
+ fs/2
Vcm
-fs/2
+ fs/2
Vcm
-fs/2
IN
ADC
IN
Vcm
Requires full input swing from +fs to –fs,
2x the swing compared to differential
Input signal at IN typically requires a
common-mode voltage for bias
Input signal at /IN also requires a
Vcm for correct dc-bias
Combined Differential inputs result in
full-scale input of +fs to –fs
Each input only requires 0.5x the
swing compared to single-ended
Both inputs require a Vcm for correct
dc-bias
ADC Input Structures:
Bipolar
• Allows input signals to go below “true” ground
– Example -10 to +10 input range centered around 0V
– To achieve a similar swing using unipolar inputs, requires DC biasing the
input to 10V, so the actual input swing would be +/-10 V around 10V (ie:
20V to 0V) … or more realistically a level translator/shifter circuit to 0 to 5V.
• You will typically find TI’s High-Voltage ADC products to have bipolar
inputs allowing a wide range of both bipolar and unipolar input voltages
Converter Resolution (bits)
ADC Technologies - SAR
Advantages
•Zero-cycle Latency
•Low Latency-time
•High Accuracy
•Typically Low Power
•Easy to Use
Disadvantages
• Max Sample Rates 2-5 MHz
24
20
Delta Sigma
Or Sigma Delta
16
(Oversampling)
SAR
12
Successive
Approximation
Pipeline
8
Conversion Rate 10
100
1K
10K
100K
1M
10M
100M
SPS
Converter Resolution (bits)
ADC Technologies - ΔΣ
Advantages
•High Resolution
•High Stability
(averages and filters out noise)
•Low cost
Disadvantages
•Cycle-Latency
•Low Speed
24
20
Delta Sigma
Or Sigma Delta
16
(Oversampling)
12
SAR
Successive
Approximation
8
Conversion Rate 10
100
1K
10K
100K
1M
Pipeline
10M
100M
SPS
Agenda
• Key Terminology
• SAR Topology and Front End Signal Conditioning
• New SAR ADCs
• Delta Sigma Topology and Front End Signal Conditioning
• New Delta Sigma ADCs
• Isolated Delta Sigma Modulators
• Summary
SAR Topology
SAR Input Driver Circuit
• Op-Amp: CMV Range, RR Out-swing to the rail,
Slew Rate, Output Impedance
• Filter: Charge Bucket Filtering
• A/D: Acquisition Time, Input Circuit Parameters
SAR Input Driver Circuit
Rail-to-Rail Output
OPA350
OPA350 is rated to swing
within 100mV of the rail!
SAR Input Driver Circuit
Solution circuit:
Since the op-amp can only swing 4.8Vp-p,
Set ADC FSR to 4.8V by reducing REF to 2.4V!
SAR Input Driver Circuit
V
A/D
RFLT
?
RSW
100W
t
CSH
S1
VS
CFLT
?
20pF- 50pF
S2
• Large charge distribution must settle during tACQ
• Added capacitor (and possibly resistor) can reduce spike
• Op amp must be capable of charging
•Capacitance (CSH + CFLT)
•Within acquisition time, tACQ
•From 0 V to (FSR - 0.5LSB)
SAR Input Driver Circuit
Guidelines:
Cflt > 20 * CSH
Ƞ = t ACQ / NTC
Rflt = t ACQ / 18 * Cflt
UGBW > 2 * (1/2π*Rflt*Cflt)
Multiply by 4 in practice!
SAR Input Driver Circuit
VS
½ LSB
VCSH(t)
VSH0
t0
tACQ
Time
Theoretical Time Constants to settle ADC input to ½ LSB during Tacq of ADC
Agenda
• Key Terminology
• SAR Topology and Front End Signal Conditioning
• New SAR ADCs
• Delta Sigma Topology and Front End Signal Conditioning
• New Delta Sigma ADCs
• Isolated Delta Sigma Modulators
• Summary
ADS9110
Industries’ Highest Precision 18-bit, 2-MSPS SAR ADC
Features
Benefits
• Best-in-class Linearity
•

DNL : +/- 0.75 LSB, INL : +/-1.5 LSB
• Best-in-class Noise performance

Excellent linearity and high throughput
SNR : 100-dB, THD : -120-dB
enable fast and precise control loop
•
Excellent noise performance reduces
• Low power/speed

oversampling and filtering requirements
•
15 mW @ 2-MSPS
Enhanced SPI Digital Interface
• SPI interface
 Enables low horsepower uC to run the ADC at its

Supports legacy SPI modes and daisy-chain

Options to achieve high throughput at lower
full throughput
 Programmable options allow easy interface to
SCLK speeds
variety of uC/DSP/FPGA
 Eases board layout and isolation design
Applications
• Test & Measurement
•
•
•
•
ATE PMU
Multi-meter
AWG/Digitizer
Source Measure Units
• Motor Control
• Precision Robotics
• CNC
 Eases timing constraints and simplifies firmware
• Medical Imaging
•
•
•
•
Digital X-RAY
Ultra Sound
CT Scanners
MRI
• Factory Automation
• Travelling Wave
• EtherCAT modules
Companion Devices:
• Precision Input Drivers
‒
OPA625. OPA2625
ADS9110
TPS7A4700 LDO
VIN+
• Precision Reference
‒
REF5045
VREF
VIN-
• Low Noise Supply
‒
AVDD
GND
ADS7044
Industry-Leading, Ultra-Low Power & Footprint SAR ADC | 12-bit | Fully Differential
Features
Benefits

NANO Power / NANO Package
o 900µW @ 1MSPS; 90µW @ 100kSPS
o X2QFN-8: 1.5mm x 1.5mm

Industry-leading low power operation and microscopic
size enable extended battery life and allow for usage in
high-density, space-constrained applications
o

Wide supply ranges accommodate most commonly-used
rails, resulting in design flexibility

Device combines extremely small footprint with performance
comparable to larger 8-bit ADCs

Low speed SPI clock can interface with smaller and simpler
MCUs, creating easier design developments

o
o
o

AVDD: 1.65–3.6V
Unipolar/Fully Differential
Temperature Range: -40˚C to +125˚C
Excellent Performance
o
o
o

VSSOP-8 (leaded): 2mm x 2.3mm
Wide Operating Range
±1 LSB INL (max); ±1 LSB DNL (max)
SNR: 71dB
Offset: ±2.2mV
Ease of Use
o
o
Simple SPI Interface: 16MHz
Only One Decoupling Capacitor!
Applications








Data Acquisition
Wearable Fitness
Motor Control
Portable Medical Equipment
Flow Meters
Hard Drives
Level Sensors
Glucose Meters
Single-Supply DAQ with ADS7044
ADS704x – Family Comparison
Industry-Leading, Ultra-Low Power & Footprint SAR ADCs
Specifications
ADS7040
ADS7041
ADS7042
ADS7043
ADS7044
Resolution (Bits)
8
10
12
12
12
Max Speed (kSPS)
1000
1000
1000
1000
1000
Package Size (mm2)
2.25
6
2.25
6
2.25
6
2.25
6
2.25
6
Pin-Package
8-QFN
8-VSSOP
8-QFN
8-VSSOP
8-QFN
8-VSSOP
8-QFN
8-VSSOP
8-QFN
8-VSSOP
Analog Supply Voltage (V)
1.8-3.6
1.8-3.6
1.8-3.6
1.8-3.6
1.8-3.6
Digital Supply Voltage (V)
1.65-3.6
1.65-3.6
1.65-3.6
1.65-3.6
1.65-3.6
@ 1MSPS/1.8V AVDD
189
207
234
261
306
@ 1MSPS/3V AVDD
555
600
690
780
900
@ 100kSPS/3V AVDD
56
60
69
78
90
@ 1kSPS/3V AVDD
<1
<1
<1
<1
<1
SCLK for Full Throughput
(MHz)
12
14
16
16
16
SNR (dB)
49
61
70
70
71
THD (dB)
-70
-75
-80
-80
-85
INL (LSB)
±0.5
±0.8
±1
±1
±1
Input Type
Unipolar/SE
Unipolar/SE
Unipolar/SE
Unipolar/Pseudo-Differential
Unipolar/Fully Differential
Input Range
0 to +AVDD
0 to +AVDD
0 to +AVDD
-AVDD/2 to +AVDD/2
-AVDD to +AVDD
Operating Temp Range (̊C)
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
Price | 1ku
$1.00
$1.60
$2.10
$2.10
$2.10
Power (µW):
ADS86xx Device Comparison Table
Number of
Channels
Resolution
12-Bit
14-Bit
4
ADS8664
ADS8674
ADS8684
ADS8684A
ADS8694
8
ADS8668
ADS8678
ADS8688
ADS8688A
ADS8698
4 Channel Diagram
16-Bit
18-Bit
8 Channel Diagram
ADS8698
18-bit | 8-Channel | Integrated AFE with MUX | Single +5V Supply
Features
Benefits
•
•
•
Supports bipolar input signals with single 5V supply
•
Analog Front End integration for direct sensor interface
•
low-drift reference enables accurate conversions
•
Exceptional AC and DC performance; making product
•
•
•
•
•
HV Unipolar/Bipolar inputs with single 5V supply
Input Structure:
‒ 8-SE channel MUX with auto/manual scan
‒ Constant Resistive 1MΩ Input Impedance
‒ Input Over Voltage Protection of ±20V
‒ S/W programmable input range (per channel):
 ±10.24V | ±5.12V | ±2.56V
 0-10.24V | 0-5.12V
VREF = 4.096V
‒ Accuracy = 0.025% | Drift = 10ppm/ºC (Max)
Precision SAR ADC Performance
‒ 500kSPS (aggregate)
‒ ±5 LSB INL and 18-bit NMC DNL
‒ AC Performance: SNR = 93dB; THD < -100dB
‒ DC Performance: Gain < 0.05%; Offset < 1mV
‒ 65mW power at 500KSPS
‒ SPI interface with Daisy-Chain
Enhanced Features:
‒ Auxiliary channel
‒ Input ALARM (Prog. Thresholds Per Channel)
Industrial Temperature Range: -40⁰C to 125⁰C
38 pin leaded package
Applications
• Power Monitoring
• Low Cost Industrial Data Acquisition
• Protection Relays
• Metrology
ideal for industrial applications
•
Small Footprint with Extended Industrial Temp range makes
the ADS8698 suitable for various industrial applications
SAR Considerations
• Very Popular Topology
• Useful for “Point in Time” or Multiplexed Measurements
– Acquires Signal During Sampling Time
• Very Low Power
• Very Low Latency
• Ease of Interface
• Analog Front End is Key to Performance
–
–
–
–
Handle Charge Injection from ADC Sample Capacitor
Enough Bandwidth to Settle During Sampling Time
Input Signal is Typically Buffered to Provide Low Impedance to ADC
Anti-Aliasing Filter is Typically Implemented at the Front End
• Typically Requires Support Circuitry (Buffer, PGA, MUX, Vref)
Agenda
• Key Terminology
• SAR Topology and Front End Signal Conditioning
• New SAR ADCs
• Delta Sigma Topology and Front End Signal Conditioning
• New Delta Sigma ADCs
• Isolated Delta Sigma Modulators
• Summary
Delta Sigma Topology
SAMPLE RATE (Fs)
Analog
Input
Delta-Sigma
Modulator
DATA RATE (Fd)
Digital
Filter
Decimator
Digital Decimating Filter
(usually implemented as a single unit)
Digital
Output
Fs / Fd = DR
(DR = Decimation Ratio)
Modulator Output
Analog
Input
Delta-Sigma
Modulator
Digital
Filter
Decimator
Digital Decimating Filter
(usually implemented as a single unit)
Digital
Output
1st Order Delta-Sigma Modulator
(FREQUENCY DOMAIN)
Higher Order Delta-Sigma Modulators
Third Order
 Modulator
Second Order
 Modulator
First Order
 Modulator
FS
Frequency
Delta-Sigma A/D Signal Path
Analog
Input
Delta-Sigma
Modulator
SAMPLE RATE (Fs)
DATA RATE (Fd)
Digital
Filter
Decimator
Digital Decimating Filter
(usually implemented as a single unit)
Digital
Output
Fs / Fd = DR
(DR = Decimation Ratio)
Normalized SINC Digital Filter Response
Fd
Normalized Output Data Rate (Hz)
Output Rate vs. Effective Resolution
SIGNAL
SIGNAL
Fs
Fd
QUANTIZATION
NOISE
Fd
QUANTIZATION
NOISE
Fs
Delta-Sigma Anti-Aliasing
Potential noisy
frequencies
Gain
Digital filter response
Digital filter response
These frequencies alias, but
are filtered
0
Fd
Fs/2
Frequency (Hz)
Fs
(modulator Sampling Frequency)
Delta-Sigma Anti-Aliasing
Potential noisy
frequencies
Gain
Anti-aliasing
Response
Front-end filterFilter
response
Digital filter response
Digital filter response
These frequencies
These frequencies alias, but
are aliased
are filtered
0
Fd
Fs/2
Decimation Ratio
(DR = Fs / Fd)
Frequency (Hz)
Fs
Typical Delta-Sigma Anti-Aliasing Filter
RFLT/2
+
RFLT/2
 ADC
CFLT

Delta-Sigma Resistor Recommendations
Maximum External Filter Resistor Value, R FLT (W)
100000000
10000000
1000000
18-BIT
100000
20-BIT
10000
22-BIT
1000
24-BIT
100
10
1
10
100
1000
10000
Data Rate, Fd (Hz)
100000
1000000
Easy Way for Filter Design
A simple spreadsheet can be used to help choose parameters.
Easy Way for Filter Design
Use Filter Design Tool under Webench if active filter is needed.
Delta Sigma Considerations
Pros:
• Useful for Lower Bandwidth Signals
• Very High Resolution
• Very High Linearity
• Typically Highly Integrated (Calibration, Buffer, PGA, MUX, Vref)
• Simple Anti-Aliasing Filter
Cons:
• Higher Latency
• Typically Requires Configuration of Registers
Agenda
• Key Terminology
• SAR Topology and Front End Signal Conditioning
• New SAR ADCs
• Delta Sigma Topology and Front End Signal Conditioning
• New Delta Sigma ADCs
• Isolated Delta Sigma Modulators
• Summary
ADS1262/3
Best-in-class Industrial ΔΣ ADC w/ Ultra Low Noise| 32-bit | 10/5 SE/Diff Channels
Features
Benefits






Highest Resolution ADC:
o 27 bit ENOB, 7nV Noise (@2.5SPS)
11 Flexible, Multiplexed Inputs:
o 10 Single-Ended OR 5 Differential
Highly Specified Performance:
o Offset Drift: 1nV/°C
o Gain Drift: 0.5ppm/°C
o INL: 3ppm
Highly Integrated Device:
o Low Drift Internal Reference: 2.5V
o GPIOs (8)
o Internal Clock: 7.3728MHz
o High Impedance PGA: 1/2/4/8/16/32
o SINC + 50/60Hz Digital Filter
Fault Detection/Input Diagnostics
Applications






Industrial PLC
High-End Panel Meters and Process Controllers
High Precision Weigh Scales
Industrial Strain Gauge Analyzers
Analytical Equipment
RTD Measurement





Wide dynamic range 32-bit ADC enables direct digitization of
low level sensors
High-resolution, low-drift architecture provides the industry’s
best performing ADC
A high level of integration eliminates the need for several
typical discrete components, decreasing necessary PCB
space and reducing costs
Wide sample rate allows this device to be adaptable to a
variety of applications
On-chip sensor bias current sources make the ADS1262
RTD-ready
Fault detection improves system reliability
ADS1262/3 – Differentiating Features
Best-in-class Industrial ΔΣ ADC w/ Ultra Low Noise| 32-bit | 10/5 SE/Diff Channels
Industry’s Highest Resolution ADC
• Industry’s best-in-class 32-bit ADC
• 7nVRMS noise @ G=32 & 2.5SPS
• Programmable Digital Filter offers 96dB NMR @ 50Hz
Industry’s Best Specified ADC
• Industry’s best drift specifications
• Internal reference with specified long term drift
• Widest operating temperature range: -40°C to +125°C
Highly Integrated ADC
• Includes: Burnout Current Sources; Self-Calibration; Dual Matched
IDACs, “any combination you want” MUX, Temperature Sensor,
GPIOs, Error Detection
PREVIEW
ADS1257
Very Small | Very Low Noise ΔΣ ADC w/ PGA & Input Buffer | 24-bit | 4-Ch
Features
Benefits










Up to 23 Bits of Noise-Free Resolution!
Very Small Packaging: 5mm x 5mm QFN-20
INL: 10ppm (max)
Output Data Rates: 5SPS–30kSPS
4 Analog Inputs w/ Flexible Channel Configuration &
Sensor Detect
Chopper-Stabilized Input Buffer
Low-Noise PGA: 1/2/4/8/16/32/64
Independent Supplies:
o Analog Supply: 4.75–5.25V
o Digital Supply: 1.8–3.6V
Low Power Dissipation: 38mW (Normal Mode)
Applications

Industrial Process Control

Medical Equipment

Test & Measurement

Weigh Scales





Small device footprint supports use in even the most spaceconstrained designs
Selectable input buffer greatly increases the input impedance
of the device, making direct sensor connection possible
Integrated PGA enables small analog signal conversion
Programmable digital filter allows for varying output data
rates as well as 50/60 Hz rejection
Convert multiple sensor inputs via multiplexing and take
advantage of the device’s high sampling rate and singlecycle settling
Independent supply voltages support different voltage levels
for analog and digital circuitry, reducing necessary power
consumption for low voltage signals
Preview
ADS131A02/04:
Two/Four-Channel, Multi-Bit Analog Front End for Energy Applications
Features
 2/4-channel, Simultaneous Sampling, 24-bit
Analog Front End








SNR: 107dB , THD: 100 dB @8kSPS
ENOB: Over 17 bits @ 8kSPS
Accuracy: 0.025% @ 3000:1 DR
Data Rate: Up to 128kSPS
Digital Scaling (Gain) options: 1, 2, 4, 8, & 16
Data Integrity check: CRC and Hamming Code
Low drift internal reference: 10ppm/C
Power: 2mW/Channel
Benefits
• Accuracy exceeds requirements for Class 0.1 systems
• Wide bandwidth options for harmonic analysis
• Data integrity to check for errors during data transmission
• Ability to correct single bit errors in data transmission
• Inputs can accept signals below ground in single supply
configuration
• Wide operating temperature range
• Synchronization options for multiple devices
AVDD
IN1N
VREFP VREFN IOVDD DVDD
Reference
Mux
ADC
Reference
Voltage
IN1P
Applications
• Industrial Power Applications
• Single Phase, Polyphase Energy Metering
• Relay Protection, Circuit Breaker
• Power Quality
• Portable Instrumentation, IEDs
IN2N
ADC
IN2P
IN3N
ADS131A02
ADS131A04
PWDN
M [2:0]
RESET
Control and
Serial
Interface
ADC
IN3P
IN4N
Negative
Charge
Pump
ADC
IN4P
ADS131A04 only
AVSS
VNCP
CLK/XTAL
GND
CS
SCLK
DIN
DOUT
DRDY
DONE
XTAL1/CLKIN
XTAL2
Preview
ADS127L01
Wide Bandwidth 24 bit Delta Sigma ADC
Features
Benefits
• Data Rate: Up to 512kSPS
• SNR 106 dB @ 250 kSPS
• Selectable digital filter options
• Wide Bandwidth (FIR): +/-0.00004dB passband ripple
• Low Latency
• DC Performance: 8.8uVrms @ 250kSPS
• Offset Drift: 2 µV/C
• Gain Drift: 1.3 ppm/C
• 38mW @512kSPS
• -40C to 125C Operating Range
• Wide data rate options: 512 kSPS
• Extremely low power density
• Excellent AC and DC accuracy
• Low Offset Drift
• Low Gain Drift
• Extremely low pass-band ripple attractive for AC
applications
Applications
•
•
•
•
•
•
Vibration Analysis
Pressure Sensors
Ultrasonic Sensors
Acoustics / Dynamic Strain Gauges
Low Power Data Acquisition
Test & Measurement
The Difference lies in Filtering
230kHz bandwidth
Excellent AC Performance
+/-0.0004dB ripple
ADS127L01FIR Filter
0
Droop
-20
Gain (dB)
-40
110dB stop-band
attenuation
-60
-80
Other 24-bit
industrial ADCs
-100
Flat stop-band
-120
DC
100
200
Input Frequency (kHz)
300
400
Agenda
• Key Terminology
• SAR Topology and Front End Signal Conditioning
• New SAR ADCs
• Delta Sigma Topology and Front End Signal Conditioning
• New Delta Sigma ADCs
• Isolated Delta Sigma Modulators
• Summary
Isolated Current Measurement
ISOLATION
VINP
VINN
(2) Isolated Delta-Sigma
Modulators
ΔΣ
ISOLATION
(1) Isolated Amplifiers
VOUTP
VOUTN
Data
Clock
Modulators / Isolated Delta-Sigma ADCs
3
AMC1304L05
AMC1304L25
AMC1304M25
LVDS Interface
20MHz CLK, 1-Ch
Current Shunt, LDO
7kV Isolation
LVDS Interface
20MHz CLK, 1-Ch
Current Shunt, LDO
7kV Isolation
CMOS Interface
20MHz CLK, 1-Ch
Current Shunt, LDO
7kV Isolation
AMC1304M05
AMC1305L25
AMC1305M25
CMOS Interface
20MHz CLK, 1-Ch
Current Shunt, LDO
7kV Isolation
LVDS Interface
20MHz CLK, 1-Ch
Current Shunt
7kV Isolation
CMOS Interface
20MHz CLK, 1-Ch
Current Shunt
7kV Isolation
AMC1305M05
Linearity Error (16-Bit LSB)
CMOS Interface
20MHz CLK, 1-Ch
Current Shunt
7kV Isolation
ADS1205
4-Ch
Hall Effect Sensor
Digital Modulator Filters
ADS1204
4-Ch
Hall Effect Sensor
AMC1210
4-Ch Digital Filter
For DS Modulators
ADS1203
10MHz Modulator
Single Input
Current Shunt
AMC1204B
Single Input
20MHz Modulator
Current Shunt
4.25kV Isolation
Q-100
6
AMC1204
Single Input
20MHz Modulator
Current Shunt
4kV Isolation
8
AMC1203
Single Input
10MHz Modulator
Current Shunt
4kV Isolation
ADS1209
Isolated Amplifiers
2-Ch
Resolver Sensor
Q-100
AMC1200
AMC1200B
Isolated Amplifier
Current Shunt
4kV Isolation
Isolated Amplifier
Current Shunt
4.25kV Isolation
ADS1208
Single Input
Hall Effect Sensor
AMC1100
Isolated Amplifier
E-metering
4kV Isolation
ADS1202
Single Input
10MHz Modulator
Current Shunt
13
≤100mV
250mV
Input Range
280mV
Vref(5V)
EXISTING
NEW
ROADMAP
AMC1200B
4.25kVPEAK Isolated Amplifier
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250mV input voltage range
Fixed gain: 8
Input bandwidth: 100kHz typ, 60kHz min
Noise: 3.1mVRMS
Input offset voltage: 1.5mV max;
drift: ±10V/C max
Non-linearity: ±0.075 / 0.1% max
CMRR: 102dB
Supply Current: 8/6mA (IDD1 / IDD2)
Specified Temp range: -40..105C
• Pin-to-pin performance upgrade for
HCPL7800 & HCPL7840 (GullWing-8)
• Over 90% more linear,
80% less gain drift,
50% of the power
• enables higher system efficiency
5V:
2.55V
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Shunt-based Current measurement in:
 Green Energy
 Frequency Inverter Applications
 Uninterruptible Power Supplies
0V
2V
250mV
3.3V:
1.3V
AMC1200 EVM Available
2V
AMC1304
7kVpeak Reinforced Isolated ΔΣ Modulator with LVDS Interface & Integrated LDO
Features
Benefits
• Reinforced Isolation (UL1577 & VDE V 0884-10)
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Working voltage: 1.0 kVRMS, 1.5 kVDC
Isolation voltage: 7 kVPEAK / 10 kVSURGE
• CMTI: 15 kV/s (min.)
• Clock: 5-20 MHz (external)
• Input voltage ranges:
 50 mVIN (BW = 1 MHz, RIN = 5 kW)
 250 mVIN (BW = 1 MHz, RIN = 25 kW)
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Superior DC performance
Offset /Drift:  50uV / 1.3uV/C
Gain / Drift:  0.3% / 40ppm/C
LDO allows 4V … 18V supply voltage range
Interface: CMOS and LVDS
Temperature range: -40 to 125C
SO-16 (DW) package
Simplified BOM (integrated LDO)
Galvanic barrier provides EMI immunity
Robust isolation barrier lifetime
Wide clock range gives sample rate
flexibility for customer
• Reduced input voltage range enables
higher shunt currents
• Extended industrial temperature range
VCAP
LDO_IN
AINP
AINN
LDO

Modulator
Applications
Shunt-based Current measurement in:
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Motor Control
Green Energy
Frequency Inverter Applications
Uninterruptible Power Supplies
2.5 V REF
AGND
DVDD
ISOLATION BARRIER
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–
DATA
CLKIN
DGND
Advantages of AMC1304
Powered off floating power supply of
the isolated gate driver
– simple design
(AMC1304 only)
80% lower
power dissipation
vs. ±250mV
LVDS option for
improved EMI & better
signal integrity with long
transmission lines
±50 mV
drop
VINP
ΔΣ
VINN
ISOLATION
4..18VIN
LDO
Data
Clock
MCU
or
FPGA
(with decimation filter)
AMC1304
Isolated 20 MHz  modulator with
integrated gain stage
- supporting fast overload response
external clock input
simplifies system level
synchronization
Reference Designs
TIDA-00171
• Isolated Current Shunt and Voltage Measurement
for Motor Drives
• AMC1304 with C2000™ TMS320F28377D Delfino™
microcontroller
• Integrated Sinc-Filters in MCU
TIDA-00209
• Isolated Current Shunt and Voltage Measurement
Motor Drives
• AMC1304 with AM4379 Sitara™ ARM® Cortex® A9 Processor
• Sinc-Filters on PRU-ICSS
TIDA-00080
• Shunt-Based AC/DC Current and Voltage Sensing
for Smart Grid
• isolated shunt based current measurement to
replace Current Transformers (CT)
Agenda
• Key Terminology
• SAR Topology and Front End Signal Conditioning
• New SAR ADCs
• Delta Sigma Topology and Front End Signal Conditioning
• New Delta Sigma ADCs
• Isolated Delta Sigma Modulators
• Summary
Summary
Resolution (bits)
Highest Bandwidth
Benefits
Drawbacks
SAR
Delta Sigma
8 -18
12 - 32
4 MSPS
1 MSPS
Simple to Use
High Resolution
Low Power
High Linearity
Point in Time
Digital Design
Multiplexing
Integration
Size
Low Power
Anti Aliasing Filter
Latency
Analog Design
Bandwidth
Integration
Configuration
Thank You!