IMPEDANCE MATCHING NETWORK SYNTHESIS TECHNIQUE FOR
A SINGLE-ENDED FET FREQUENCY DOUBLER DESIGN
MISS SURUNYA LAMAIPHAN
A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF MASTER OF SCIENCE
IN COMMUNICATION ENGINEERING
SIRINDHORN INTERNATIONAL THAI-GERMAN GRADUATE SCHOOL OF ENGINEERING
(TGGS)
GRADUATE COLLEGE
KING MONGKUT'S INSTITUTE OF TECHNOLOGY NORTH BANGKOK
ACADEMIC YEAR 2006
ISBN 974-19-0850-4
COPYRIGHT OF KING MONGKUT'S INSTITUTE OF TECHNOLOGY NORTH BANGKOK

Name
Thesis Title
: Miss Surunya Lamaiphan
: Impedance Matching Network Synthesis Technique for
Major Field a Single-ended FET Frequency Doubler Design
: Communication Engineering
King Mongkut's Institute of Technology North Bangkok
Thesis Advisors : Associate Professor Vech Vivek
Mr. Alongkorn Namahoot
Academic Year : 2006
Abstract
In this thesis, an impedance matching network synthesis technique for designing an active frequency doubler is proposed. A single-ended MESFET frequency doubler circuit is first constructed to determine a set of ideal terminating impedances for the maximum conversion gain with minimum unwanted-output harmonics. The complex conjugation of those ideal impedances is equivalent to the internal input and output impedances of the FET at different harmonics. As a result, the microstrip matching networks can be easily designed to match with the input and output impedances of the nonlinear device by conventional network synthesis. To validate this design technique, a single-ended FET 1.2/2.4 GHz frequency doubler for ISM band is demonstrated. The measured performances of fabricated circuit conform to the simulated results and exhibit 7.8 dB conversion gain and 75 MHz operating bandwidth as well as unwanted-output harmonics suppression better than 20 dB.
(Total 71 pages)
Keywords : Frequency doubler, Frequency multiplier, Frequency translation,
Impedance
Advisor ii

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วิทยานิพนธฉบับนี้ได กลาวถึงวิธีการสังเคราะหเพื่อที่จะจับคูความตานทานที่เหมาะสมที่จะ
ตอกับระบบซึ่งเปนขอเสนอหนึ่ง เพื่อที่จะใชออกแบบวงจรทวีความถี่ โครงสรางเดี่ยวที่ใชวิธีการ
สังเคราะหวงจรจับคูความตานทานที่เหมาะสมสําหรับ การออกแบบวงจรทวีความถี่โครงสรางเดี่ยว
ที่ใชทรานซิสเตอรสนามไฟฟาหรือเฟต โดยวงจรที่ถูกสรางนี้ไดมีการวิเคราะหหาความตานทาน
อุดมคติที่นํามาตอ เพื่อใหไดอัตราขยายแปลงผันสูงที่สุด และฮารมอนิกที่ไมตองการต่ําที่สุด
คอนจูเกตของคาอิมพีแดนซอิมพีแดนซเปนเชิงซอน สําหรับความตานทานที่หาไดนั้นเทียบเทากับ
ความตานทานที่นําเขาที่ขาเขาและขาออกของ FET ที่ความถี่ตางๆ ดังนั้นการออกแบบไมโครสตริป
สําหรับระบบสามารถทําไดงาย โดยการจับคูกับความตานทานทางขาเขา และความตานทานขาออก
ของอุปกรณไมเปนเชิงเสน โดยการสังเคราะหโครงขายมาตรฐานตรวจสอบความสมเหตุสมผล
และเพื่อเปนการยืนยันสมมติฐานนี้ จึงไดทําการประดิษฐวงจรทวีความถี่จาก 1.2 กิกะเฮิรตซ ไปเปน
2.4 กิกะเฮิรตซ โดยใชโครงสรางแบบโครงสรางเดี่ยวที่ใช FET สําหรับเทคโนโลยีไรสายผลการ
วัดวงจรเทียบกับใชโปรแกรมจําลองการทํางานมีผลใกลเคียงกัน ซึ่งมีอัตราขยายแปลงผันเทากับ
7.8 dB และแบนดวิดทเทากับ 75 เมกกะเฮิรตซ และฮารมอนิกที่ไมตองการที่ขาออกมีคาต่ํา
ซึ่งสามารถลดไดต่ํากวา 20 dB
(
71
)
คําสําคัญ : วงจรทวีความถี่ , วงจรเปลี่ยนความถี่ , วงจรเขาคูอิมพีแดนซ
iii

ACKNOWLEDGEMENTS
This thesis cannot be completed without the help of many people. Thanks to all those who have given me their time and information. Everyone was both very helpful and enthusiastic for my thesis success.
First of all, I would like to special thank my advisors, Associate Professor Vech
Vivek and Mr. Alongkorn Namahoot for their helpful guidance, suggestion and encouragement throughout this study.
Finally, this thesis would have not been finished without the never ending support and tolerance of my teachers, family, friends and student at wireless communications research group. I am grateful for the financial support received from
The Sirindhorn International Thai-German Graduate School of Engineering. I would like to thank the Graduate College of King Mongkut's Institute of Technology North
Bangkok for providing financial support. iv

TABLE OF CONTENTS
Page
Abstract (in English)
Abstract (in Thai) ii iii
Acknowledgements iv
List of Tables
List of Figures
List of Abbreviations and Symbols vii viii x
Chapter 1 Introductions
1.1
Propose of the study
1
1
1.2
Scope of the study 1
1.3
Method 2
1.4
Tools 2
1.5
Utilization of the study 2
Chapter 2 Background
2.1
Principle of frequency multiplier
3
3
4 2.2
Frequency multiplier theory
2.3
Transistor models
2.4
MESFET frequency generation
2.4.1
Class A
4
6
9
9
2.5
2.4.2
Class B
2.4.3
Class C
2.4.4
Class AB
Application of frequency multipliers
2.6
Reviews of frequency multipliers
9
10
11
13
Chapter 3 Design of a single-ended FET frequency doubler
3.1
Ideal network synthesis
3.2
Ideal circuit components
3.2.1
Impedance typically
3.2.2
Band-pass filter
3.2.3
High-pass filter
3.2.4
Bias tee
3.2.5
Nonlinear model of the MESFET
3.3
Transistor operating point
3.4
Frequency-doubler matching network
3.5
The input matching networks
3.5.1
Gate-bias tee structure
3.5.2
Gate-radial stub
3.5.3
Gate-bias circuit
3.5.4
Input-matching circuit
3.6
The output-matching network
3.6.1
Drain-bias tee structure
3.6.2
Drain-radial stub
3.6.3
Drain-bias circuit
3.6.4
Output-matching circuit
3.7
A single-ended FET frequency doubler
3.7.1
Variation of input power
15
15
16
16
16
17
17
18
19
20
21
22
22
25
28
31
31
31
32
35
39
41 v

TABLE OF CONTENTS (CONTINUED)
Page
3.7.2
Bandwidth of a single-ended FET frequency doubler
3.8
Layout capture of a single-ended frequency doubler
Chapter 4 Experimental and measured results
4.1
The measurement of a single-ended FET frequency doubler
4.2
Harmonic-output power
4.3
Conversion gain
4.4
3-dB Bandwidth
42
43
45
45
45
47
47
4.5
Power sweep
Chapter 5 Conclusions
48
50
5.1
Conclusion 50
5.2
Problem and Suggestion for future work 50
References 51
Appendix A Data sheet NE3210S01
Appendix B Data sheet GML1000
Appendix C Data sheet surface mount capacitors
52
62
64
Appendix D ITC-CSCC2006 66
Biography 71 vi

LIST OF TABLES
Table Page
3-1 Input- and output-reflection coefficients
3-2 Simulated dimensions of input matching circuit
19
28
3-3 Simulated dimensions of output matching circuit
4-1 Output spectrum comparison between simulation and measurement at
P in
= 0 dBm
36
46 vii

LIST OF FIGURES
Figure Page
2-1 Block diagram of typical frequency multiplier
2-2 Network configuration model
3
4
2-3 Simplified cross-section of a MESFET device [4]
2-4 Equivalent circuit of a GaAs MESFET
2-5 V
DS
is raised from zero to some low value
2-6 V
DS at the saturation point
2-7 Current saturation
5
6
7
7
8
8 2-8 Load line and the waveforms for ideal class-A operation
2-9 Load line and the waveforms for ideal class-B operation
2-10 Load line and the waveforms for ideal class-C operation
2-11 Load line and the waveforms for ideal class-AB operation
2-12 Block diagram of 94 GHz frequency source presented [7]
9
10
10
11
2-13 Block diagram of down converter system presented [8]
2-14 Improved down converter system utilizing CG frequency doubler
3-1 Simplified ideal single-ended FET doubler circuit
3-2 Impedance circuit and symbol
3-3 Band-pass filter circuit and symbol
12
13
15
16
17
17 3-4 High-pass filter circuit and symbol
3-5 Bias tee circuit [15]
3-6 MESFET nonlinear model
3-7 Input and output harmonic power
3-8 Input and output matching network diagram
3-9 Substrate definition
18
18
20
21
21
22 3-10 Bias-circuit structure
3-11 Bias-circuit equivalent
3-12 S
21
from open stub, short stub and radial stub
3-13 Gate-radial stub [16]
3-14 S-parameter of gate-radial stub (a) S
11
and (b) S
21
3-15 Gate-bias circuit
3-16 S-parameter of Gate-bias circuit (a) S
11
, (b) S
21
and (c) S
13
3-17 Gate-bias tee layout
3-18 Input matching (a) schematic and (b) layout
3-19 S-parameter of drain-radial stub (a) S
11
(b) S
21
3-20 Drain-bias circuit
3-21 S-parameter of Gate-bias circuit (a) S
11
, (b) S
21
and (c) S
13
3-22 Drain-bias tee layout
22
23
23
24
25
26
27
29
32
33
34
35
37 3-23 Output matching (a) schematic and (b) layout
3-24 A single-hybrid 1.2/2.4 GHz frequency doubler
3-25 HB-simulation result of the single-ended FET frequency doubler
3-26 Power spectra at gate of transistor
3-27 Power spectra at load
3-28 Time domains of input and output voltage
3-29 Input power as (a) Harmonic-output power and (b) Conversion gain
39
39
40
40
41
41 viii

LIST OF FIGURES (CONTINUED)
Figure Page
3-30 Fundamental frequency as (a) Harmonic-output power and (b) Conversion gain
3-31 Layout of frequency doubler
42
43
44 3-32 Image of practical frequency doubler
4-1 Measurement setup for a single-ended FET frequency doubler
4-2 The output spectra power between simulation and measurement
45
46
4-3 Frequency response of doubler at P in
= 0 dBm
4-4 Power sweep of doubler at f
0
(sim) = 1.2 GHz and f
0
(meas) = 1.185 GHz
(a) Output power and (b) Conversion gain
47
48 ix

LIST OF ABBREVIATION AND SYMBOLS
ω
g
Guide
The operatng radian frequency wavelength
Γ in
Γ out
The reflection coefficients at input
The reflection coefficients at output f
2f
0
Second n n th
harmonics
ADS Advances design system
BJT Bipolar transistor
BPF Bandpass
C Capacitor
CG Conversion
C
DS
C
GD
The drain to source capacitance
The gate to drain capacitance
C
GS
The gate to source capacitance
DC Direct
DGS Defected ground structure
FET Field-effect f
0
Fundamental
GaAs
HEMT High electron mobility transistor
I
ISM Industrial,
D
I
DS
The nonlinear channel-current source
Saturation current of transistor
L Inductor
LO Local
LPF Lowpass
LPKF Printed circuit board engraving machine
MESFET Metal-semiconductor field effect transistor
PCB Printed board
P in
Power input from a transistor or doubler circuit
P out
Power output from a transistor or doubler circuit
RF Radio
RFC Radio frequency choke
The drain ohmic contact resistances
The ohmic resistance of the gate
R
D
R
G
R
S
R
I
SMA
S ij
TOM
The source ohmic contact resistances
The intrinsic resistance
Subminiature version A
S-parameter characterization between port i and j of a network
V
D
V
DS
V
G
V
GD
The internal drain voltage
The external drain voltage or drain-to-source voltage
The internal gate voltage
The gate-to-drain voltage x

LIST OF ABBREVIATION AND SYMBOLS (CONTINUED)
V
GS
The external gate voltage or gate-to-source voltage
V p
Pinchoff
V t
Turn-on voltage or threshold voltage
Z i
> f
0
Input impedance at more than second harmonic
Z i ,2 f
0
Z
,
0
Input impedance at second harmonic
Input impedance at fundamental frequency
Output impedance at more than second harmonic Z o f
0
Z o ,2 f
0
Z
,
0
Output impedance at second harmonic
Output impedance at fundamental frequency xi

Microwave and RF frequency multipliers are employed in a large number of communications, radar, civilian, and military systems. Due to the inherent upper limit in operating frequency of the active devices in local oscillators, a frequency multiplier in conjunction with a low frequency local oscillator is often used as a signal source with very low phase noise and low realization cost. Ether diodes or FETs can be used for multipliers but FETs are more superior because of their high gain [1, 2].
The requirements for general frequency multiplier are high conversion gain and good rejection of fundamental as well as other unwanted harmonics. In order to suppress the fundamental frequency component (f
0
), a quarter-wavelength open stub or a balanced multiplier structure can be used, although those methods limit the suppression of unwanted harmonics only by 25 dB [3]. A balanced frequency doubler using input balun can be used to eliminate fundamental but the f
0
cancellation characteristics depend on the unbalance phase property of balun and uniformity of transistors. Typically 20 dB fundamental rejections at microwave frequency are obtained [4, 5].
For this master thesis, a novel impedance matching synthesis technique is proposed. The idea is to first terminate the transistor with a set of ideal impedances with different frequency. Those impedance terminations are equivalent to the conjugation of the internal input and output impedances of the transistor. The termination values are then used to synthesize the microstrip matching networks.
This master thesis will work out to support that theory by designing a frequency doubler circuit. To validate the matching theory, the measured result must agree very well with the simulation result.
In order to understand the design of a single-ended FET frequency doubler, the report was written in 5 chapters to develop the knowledge from beginning of the design to the measurement of the final circuit: Introductions, Background, Design of a single-ended FET frequency doubler, Experiment and Measured results and
Conclusions.
1.1
Propose of the study
1.1.1
Investigate the frequency multiplier technology,
1.1.2
Study and design frequency doubler using all frequency impedance matching synthesis technique.
1.2
Method
1.2.1
Literature survey of the design theory for frequency multiplier,
1.2.2
Design a frequency doubler circuit for ISM band,
1.2.3
Study and design frequency doubler using all frequency impedance matching synthesis technique,
1.2.4
Perform circuit simulation, fabricate circuit measurements, validate the result and conclusions.

2
1.3
Method
1.3.1
Literature survey of the design theory for frequency multiplier,
1.3.2
Design a frequency doubler circuit for ISM band,
1.3.3
Study and design frequency doubler using all frequency impedance matching synthesis technique,
1.3.4
Perform circuit simulation, fabricate circuit, measurements, validate the result and conclusions.
1.4
Tools
1.4.1
Personal computer
1.4.2
ADS2005A software
1.4.3
MESFET
1.4.4
GML1000 substrate
1.4.5
PCB engraving machine
1.4.6
Swept signal generator
1.4.7
DC power supply
1.4.8
Digital multimeters
1.4.9
Spectrum analyzer
1.5
Utilization of the study
1.5.1
A novel design technique for frequency multiplier circuit.
1.5.2
A knowledge base for the deployment of synthesis network applied to microwave active circuits.

Before design a frequency multiplier, a basic idea and theory must be developed.
In this chapter, the principles of frequency multiplier design are discussed. A more specific frequency multiplier device (MESFET) is addressed. Finally, the former works of frequency multiplier are reviewed and the design strategies are concluded.
2.1
Principle of frequency multiplier
Frequency multipliers can be either passive or active in nature. In passive multipliers, a varactor or step recovery diode is frequently used [6], while in active multipliers [4] the design can include any of the transistor classes we have already studied, such as the BJT, FET, and HEMT. The design of frequency multipliers with these devices is not dissimilar to designing a power amplifier, since the source impedance needs to maximize power transfer at the fundamental frequency, and the output load needs to maximize power transfer at the desired harmonic frequency.
Ideally, all other unwanted frequencies are terminated in reactive impedances to prevent any loss.
Active frequency multipliers have significant advantages over diode multipliers.
While passive resistive diode multipliers are broadband and inefficient, while the varactor frequency multipliers are narrowband and efficient, the active multipliers can have broad bandwidths and conversion gain. They can realize efficient multipliers; a high-frequency FET or bipolar multiplier chain usually consumes little dc power and dissipates little heat; this is an important advantage in space systems. In contrast, receiver LO chains using multipliers often require high-power, high-gain driver amplifiers; such amplifiers often are a dominant drain on dc power.
FIGURE 2-1 Block diagram of typical frequency multiplier
A frequency multiplier is a nonlinear circuit that multiplies the input frequency with an integer factor n to obtain n th
harmonic signal output. Figure 2-1 depicts a typical diagram for frequency multiplier. An input signal is a periodically sinusoidal

4 waveform that can be represented by the summation of infinite harmonic call Fourier series. The frequency components can be suppressed or reproduced if the signal is distorted. The nonlinear devices are used to distort the signal. The output signal distorted by the nonlinear function of signal-distortion device contains harmonics and can be filtered out to attain required harmonic.
2.2
Frequency multiplier theory
A basic single-ended frequency doubler configuration as shown in Figure 2-2 has been considered in this thesis. The input-matching network is designed to pass the fundamental frequency component to the gate pin of FET but suppresses higher harmonic components. Likewise, the output-matching network suppresses the fundamental and other unwanted harmonics but allows the second harmonic passing to the output port. The design philosophy of impedance matching network for frequency doubler is to reflect unwanted-input signals back to the sources and to reject undesired-output harmonics back to the active device. The introduction of pure reactance from reactive element such as shunt stub can match the desired frequency and reflect unwanted harmonics [5].
V
GS
V
DS
RFC RFC
Z
S
V
S
Generator for f
0
Input
Impedance
Matching
G
S
D
Z in
Z out
Output
Impedance
Matching
Z
L
Load for f
0
FIGURE 2-2 Network configuration model
In order to generate the harmonics, the transistor must be biased by DC voltage sources; V
GS
and V
DS
. In this study, we choose the dc gate-source voltage to bias the amplifier at nonlinear region around the pinch-off regions or class AB where the drain current contains both even and odd harmonics.
2.3
Transistor models
It is no overstatement to say that the GaAs MESFET and its variants, including the high electron-mobility transistor (HEMT) have revolutionized low-noise microwave electronics and microwave systems. FETs also make excellent mixers, having low noise figures, broad bandwidths, and conversion gains, and as frequency multipliers they exhibit high efficiency, gain, and output power. FETs are commonly

5 used in quasilinear applications, especially as small-signal and medium-power amplifiers, where an understanding of their nonlinearities is critical in minimizing the less attractive aspects of their performance, primarily intermodulation distortion and saturation.
Figure 2-3 shows a cross section of a GaAs metal epitaxial-semiconductor field effect transistor (MESFET). The MESFET is fabricated by first growing a very pure, semi-insulating buffer layer on a semi-insulating GaAs substrate, then growing an ndoped epitaxial layer that is used to realize the FET’s active channel. Three connections are made to the channel: the source and drain ohmic contacts and, between them, the Schottky-barrier gate. The epilayer is made thicker than necessary for the channel and is etched to the correct channel thickness in the gate region. This recessed gate structure allows the layer of epitaxial material under the source and drain ohmic contacts to be quite thick, much thicker than the channel, minimizing the parasitic source and drain resistances. Reducing the source resistance is especially important for low-noise devices; it is also important for achieving good conversion efficiency in FET mixers, frequency multipliers, and power amplifiers. n ++ n - GaAs channel
Buffer layer
GaAs substrate n ++
FIGURE 2-3 Simplified cross-section of a MESFET device [4]
Figure 2-4 shows a lumped-element equivalent circuit of the MESFET that can be used either in a small-signal or a large-signal analysis. R
G
is the ohmic resistance of the gate, and R
S
and R
D
are the source and drain ohmic contact resistances, respectively. R
I
is the resistance of the semiconductor region under the gate (called the intrinsic resistance) between the source and channel; which is negligible in ordinary, current-saturated operation. It may be significant when the FET is operated in its linear region or in inverse mode. C
DS
is the drain-to-source capacitance, which is dominated by metallization capacitance, and is therefore often treated as a constant.
C
GS
and C
GD
are the gate-to-channel capacitances; by expressing these as capacitances instead of charges we imply the use of a division-by-capacitance model, although many MESFET models use a division-by-charge characterization. I
D
is the nonlinear channel-current source. The diodes in parallel with C
GS
and C
GD
account for forward or reverse gate conduction. I
D
, C
GS
, and C
GD
are functions of the gate voltage V
G and either the drain voltage V
D
or the gate-to-drain voltage, V
GD
. V
G
and V
D
are called the internal gate and drain voltages, to distinguish them from the voltages at the FET’s terminals, V
GS
and V
DS
, called the external voltages. V
GD
represents the internal

6 quantity; we do not use the external gate-to-drain voltage. V
G
and V
D
are related to
V
GS
and V
DS
as follows:
V
G
=
V
GS
−
R I
D
Eq.2-1 and
V
D
=
V
DS
− (
R
S
+
R
D
)
I
D
Eq.2-2
FIGURE 2-4 Equivalent circuit of a GaAs MESFET
In spite of many attempts to produce “physical” models, ones are based on the physical operation of the FET device, empirical models have been by far the most successful. The expressions that model the nonlinear circuit elements in empirical models are chosen only to reproduce the measured I/V characteristic of the device.
Indeed, most physical models include significant empirical elements, turning them, fundamentally, into empirical models. For these reasons this thesis is used GaAs
MESFET NE3210S01 form NEC the TriQuint model (TOM) of the transistor has been characterized by CEL and employed in this study.
2.4
MESFET frequency generation
The MESFET is biased by the two sources: V
DS
, the drain-to-source voltage, and V
GS
, the gate-to-source voltage. These voltages control the channel current by varying the width of the gate-depletion region and the longitudinal electric field. In order to develop a qualitative understanding of MESFET operation, imagine first that
V
GS
= 0 and V
DS
is raised from zero to some low value, as shown in Figure 2-5.

7
FIGURE 2-5 V
DS
is raised from zero to some low value
When V
GS
= 0, the depletion region under the Schottky-barrier gate is relatively narrow, and as V
DS
is increased, a longitudinal electric field and current are established in the channel. Because of V
DS
, the voltage across the depletion region is greater at the drain end than at the source end, so the depletion region becomes wider at the drain end. The narrowing of the channel and the increased V
DS
increase the electric field near the drain, causing the electrons to move faster; although the channel’s conductive cross section is reduced and the net effect increase current.
When V
DS
is low, the current is approximately proportional to V
DS
. If, however, the gate reverse bias is increased while the drain bias is held constant, the depletion region is wider and the conductive channel becomes narrower, as a result, the current is reduced.
When V
GS
= V t
, the turn-on (or threshold) voltage, the channel is fully depleted and the drain current is zero, regardless of the value of V
DS
. Thus, both V
GS
and V
DS can control the drain current. When the FET is operated in this manner, it is said to be in its linear or voltage-controlled resistor region. If V
DS
is increased further, as in
Figure 2-6. The channel current increases, the depletion region becomes even wider at the drain end, and the conductive channel becomes narrower. The current clearly must be constant throughout the channel, so as the conductive channel near the drain becomes narrower, the electrons must move faster.
FIGURE 2-6 V
DS
at the saturation point
However, the electron velocity cannot increase indefinitely; the average velocity of the electrons in GaAs can not exceed a velocity called their saturated drift velocity.
If V
DS
is increased beyond the value that causes velocity saturation, the electron concentration rather than velocity must increase to maintain current continuity throughout the channel. Accordingly, a region of electron accumulation forms near the drain end of the gate. Conversely, after the electrons transit the channel and move at saturated velocity into the wide area between the gate and drain, an electron

8 depletion region is formed. That depletion region is positively charged because of the positive donor ions remaining in the crystal. As V
DS
continues to increase, Figure 2-7, progressively more of the voltage increase is dropped across this region, called a dipole layer, and less is dropped across the unsaturated part of the channel.
FIGURE 2-7 Current saturation
Eventually a point is reached where further increases in V
DS are dropped entirely across the charge domain and do not substantially increase the drain current; at this point the electrons move at saturated drift velocity over a large part of the channel length. When the FET is operated in this manner, which is the normal mode of operation for small-signal devices, it is said to be in its saturation region, or in saturated operation. All FET amplifiers and most FET mixers and frequency multipliers are biased into saturation.
The class of operation of an amplifier is determined by the amount of time that current flows in the output circuit. This is a function of the operating point of the amplifying device. The operating point of the amplifying device is determined by the bias applied to the device. There are four classes of operation for an amplifier. These are: A, AB, B and C. Each class of operation has certain uses and characteristics.
FIGURE 2-8 Load line and the waveforms for ideal class-A operation

9
2.4.1
Class A: A simple transistor amplifier that is operated class A is shown in
Figure 2-8. Since the output signal is a 100% (or 360º) copy of the input signal, current in the output circuit must flow for 100% of the input signal time. This is the definition of a class A amplifier. Amplifier current flows for 100% of the input signal.
A class A amplifier is defined when the quiescent gate voltage is adjusted so that the drain current is set to I
D 0
=
I
DSS
2 . The efficiency of an amplifier refers to the amount of power delivered to the output compared to the power supplied to the circuit.
Since every device takes power to operate, if the amplifier operates for 360º of input signal, it uses more power than if it only operates for 180º of input signal. If the amplifier uses more power, less power is available for the output signal and efficiency is lower. Since class A amplifiers operate for 360º of input signal, they are low in efficiency. This low efficiency is acceptable in class A amplifiers because they are used where efficiency is not as important as fidelity.
2.4.2
Class B: As was stated above; a class B amplifier operates for 50% of the input signal. A simple class B amplifier is shown in Figure 2-9. It is defined when the device is biased at V
G 0
=
V
P
and the conduction angle (The conduction angle is defined as the time when energy flows from the transformer into the transistor. It's normally expressed in degrees, remembering that one complete cycle of a sine wave has 360 degrees.) is 180 o
.
Therefore, only the negative portion of the input signal is reproduced in the output signal. You may wonder why a class B amplifier would be used instead of a simple rectifier if only half the input signal is desired in the output. The answer to this is that the rectifier does not amplify. The output signal of a rectifier cannot be higher in amplitude than the input signal. The class B amplifier not only reproduces half the input signal, but amplifies it as well.
FIGURE 2-9 Load line and the waveforms for ideal class-B operation
2.4.3
Class C: Figure 2-10 shows a simple class C amplifier. Notice that only a small portion of the input signal is present in the output signal. Since the transistor does not conduct except during a small portion of the input signal, this is the most

10 efficient amplifier. It also has the worst fidelity. The output signal bears very little resemblance to the input signal. It is defined for V
G 0
<
V
P
where the conductions angle is smaller than 180 o
.
Class C amplifiers are used where the output signal need only be present during part of one-half of the input signal. Any amplifier that operates on less than 50% of the input signal is operated class C.
FIGURE 2-10 Load line and the waveforms for ideal class-C operation
2.4.4
Class AB: If the amplifying device is biased in such a way that current flows in the device for 51% - 99% of the input signal, the amplifier is operating class
AB. A simple class AB amplifier is shown in Figure 2-11.
FIGURE 2-11 Load line and the waveforms for ideal class-AB operation

11
Class AB is defined for V
G 0
>
V
P
where the conductions angle between 180 o and 360 o
. Notice that the output signal is distorted. The output signal no longer has the same shape as the input signal. The portion of the output signal that appears to be cut off is caused by the lack of current through the transistor.
Class AB amplifiers have better efficiency and poorer fidelity than class A amplifiers. They are used when the output signal need not be a complete reproduction of the input signal, but both positive and negative portions of the input signal must be available at the output.
Class AB amplifiers are usually defined as amplifiers operating between class A and class B because class A amplifiers operate on 100% of input signal and class B amplifiers (discussed next) operate on 50% of the input signal. Any amplifier operating between these two limits is operating class AB.
2.5
Application of frequency multipliers
The utility of frequency multiplier is best conveying by observing some real world application. The first example utilizes two frequency doublers in implementation of a high-frequency signal source [7]. Figure 2-12 shows the block diagram of the signal source.
FIGURE 2-12 Block diagram of 94 GHz frequency source presented [7]
This design utilizes a 23.5 GHz voltage-controlled oscillator as a local source, followed by a buffer amplifier. The 23.5 GHz signal is then raised to 47 GHz by a frequency multiplier and followed by another amplifier. Finally, a 47 to 94 GHz frequency multiplier is used to achieve the desired 94 GHz output. The two active frequency doublers allow a 23.5 GHz oscillator to be utilized than designing an oscillator directly at 94 GHz.
In the second example, several frequency doublers are utilized in a transceiver system [8]. A block diagram of the down converter section of the transceiver is shown in Figure 2-13. Similar to the previous example, this design uses a frequency multiplier in order to utilize an 11 GHz local oscillator to a 22 GHz system.

12
Mixer/Downconverter
20 GHz
RF Input
LNA
IF
Output
BPF
BPF
LO
Input
Amplifier
11-22 GHz
Doubler
Amplifier
Pad
Frequency
Doubler
Chain
LO
11 GHz
FIGURE 2-13 Block diagram of down converter system presented [8]
This design can also be used to show the possible advantages of utilizing an active frequency multiplier design with large conversion gain. If the second harmonic conversion gain of the multiplier used in the frequency multiplier-chain (Figure 2-13) could be improved, the amplifiers could be eliminated. This would result an improved system, demonstrated in Figure 2-14. In this improved system, the use of 2 amplifiers is eliminated, resulting in savings of chip space and DC power consumption. These savings show the possibilities of significantly improving a system’s efficiency with the use of an active frequency multiplier.

13
FIGURE 2-14 Improved down converter system utilizing CG frequency doubler
2.6
Reviews of frequency multipliers
Camargo [5] analyzs a frequency multiplier configuration using a load RL with a parallel LC filter. He provided an analysis of variation in the load resistance RL and described the expected effect on the output current and voltage waveforms. This analysis determines the optimum load for an output current at a given harmonic
(n
× f
0
).
Multiplier techniques are expanded further by considering not only the load presented to the desired output harmonic, but the loads seen at the input and the output of the transistor for several harmonic frequencies.
Rauscher [9] utilized a GaAs FET transistor to design a frequency multiplier with a gate bias near pinch off. At the device input, a variable reactive load is presented at the second harmonics (2f
0
). At the device output, variable reactive impedance is presented to the fundamental frequency (f
0
). These reactances are varied in a computerized simulation to adjust and maximize the second harmonic conversion gain.
EI Rabaie [10] utilized a realistic MESFET device model with an optimization routine to design a frequency doubler with maximum output power at a fixed input power. They utilized small-signal input matching at f
0
and the output matching at 2f
0
.
Also the optimum offset length of a fundamental frequency short circuit at the transistor’s output is applied.
Branner [11] utilized and greatly expanded the techniques previously presented unified design technique. This technique consists of several steps in multiplier development. The first step is to select a device based on its performance characteristics, and an accurate model for the device is developed. Second, optimum bias point and input power levels are chosen utilizing the model or measured data.

14
Third, responses for the input and output network are developed. This consists of simulating the device model with various input and output load combinations and tabulating the results to find optimum network configurations. Also, the use of reflector networks is explored. These reflector networks utilize typically unused harmonic power at the output and the input of the transistor by reflecting them back into the device. Fourth, the optimized input and output network designs are synthesized to realize the prescribed impedances.
Since the work of Thomas, several other authors have presented generalized design techniques. Colantonio [12] utilize a Materka MESFET model in a frequency doubler design technique using their own harmonic balance simulator. The design features a bias near the pinch off voltage at a fixed input power level. The input network provides an impedance match at the fundamental frequency and variable, reactive impedance at the second harmonic. The output network provides an impedance match at 2f
0
and variable, reactive impedance at the fundamental. The reactive impedances are varied to maximize the second harmonic conversion gain.
Schmale [13] utilized a very similar technique to Colantonio. A frequency doubler is designed by utilizing an f
0
reflector at the output a realistic device model, as well as a 2f
0
reflector at the input. The phase of the reflection coefficient of the input and output reflectors is varied to show the variation in the corresponding 2f
0 conversion gain.
Jeong [14] utilized a novel design of a frequency doubler, using a feed forward technique and a defected ground structure (DGS). In the proposed frequency doubler, the feed forward loop suppresses the fundamental component (f
0
), and the DGS attenuates the higher order harmonics such as third, fourth and so on. Due to the combination of the feed forward structure and the DGS, only the doubled frequency component (2f
0
) appears at the output port; the other unwanted components are suppressed effectively.

In the preceding chapter, the basic ideas and theories of frequency doublers have been developed. The indisputable design keys have been introduced. In this chapter, a design of single-ended FET frequency doubler is conducted by ADS2005A
(Advanced Design System 2005A). An ideal doubler circuit is constructed and its dc operating point is determined. At last, the optimal impedance terminations are quantified.
3.1
Ideal network synthesis
A MESFET together with ideal impedance terminations forms an ideal doubler circuit. The simplified circuit illustrated in Figure 3-1 consists of a transistor, bias circuits, and harmonic termination networks. The transistor amplifier is biased via bias tees and the single-tone stimulus excites the amplifier through an f
0
-pass filter.
FIGURE 3-1
Simplified ideal single-ended FET doubler circuit

16
The maximum power of fundamental frequency transporting to the gate pin occurs when the impedance Z
,
0
is equal to the conjugation of input-impedance of
FET at fundamental frequency. The unwanted input harmonics are terminated by the reactive loads
Z i ,2 f
0
and
Z i f
0
that are equivalent to the condition of mismatching between the input impedances of FET. (As a result, the undesired harmonics are reflected back to the source V
S
.) At the optimal input-terminating loads, the maximum power at fundamental frequency is presented at the gate pin with insignificant higher harmonics. Since the amplifier operates in class AB, the output signal is distorted from sinusoid and the spurious harmonics are generated. The unwanted output harmonics are terminated by complex loads
Z
,
0
and
Z o
> f
0
reflected the power back to the transistor. The desired harmonic 2f
0
is tuned and conjugate matched to the output impedance of the transistor at 2f
0
by the impedance
Z o
,2 f
0
. The circuit is optimized by harmonic-balance simulation for maximum conversion gain with minimal unwanted harmonics.
3.2
Ideal circuit components
In Figure 3-1, the circuit components are not purely constructed from typical components from libraries. The subcircuits have been used and their model is characterized in this section.
3.2.1
Impedance: Impedance in the doubler design can be utilized by a simple Z port. The simulation of doubler design is based on the nonlinear simulation called harmonic balance. To use a simple impedance element cannot guarantee the convergence of simulator, consequently a resistor 1 G Ω is added parallel to the Z port providing the convergence of simulation. Figure 3-2 presents the impedance in the design.
FIGURE 3-2
Impedance circuit and symbol
3.2.2
Band-pass filter: A band-pass filter allows the signal between the two specific frequencies to pass. The model of band-pass filter is illustrated in Figure 3-3.
The designed band-pass filter has centre frequency at F GHz with narrow bandwidth.
The high-selectivity filter consists of a Z impedance connecting parallel with an additional resistor. The value of Z impedance is an expression defined by an equation

17 whose value equals 1 μ Ω and 2 G Ω when the input frequency falls in the filter bandwidth and out of the filter bandwidth respectively.
R
R5
R=2 GOhm
Port
P1
Num=1
Port
P2
Num=2
Var
Eqn
Z1P_Eqn
VAR
VAR1
Z1P1
Z[1,1]=impedance impedance=2 GOhm * ( step(freq - (F+1Hz)) + step((F-1Hz) - freq)) + 1uOhm
FIGURE 3-3 Band-pass filter circuit and symbol
3.2.3
High-pass filter: A high-pass filter allows the signal above a specific frequency to pass. Figure 3-4 present the model of high-pass filter utilized in the design. The cut-off frequency is defined as F GHz. The value of Z impedance is defined by an expression whose value equals 1 μ Ω and 2 G Ω when the input frequencies are above the cut-off frequency and below the cut-off frequency of filter respectively.
R
R5
R=2 GOhm
Port
P1
Num=1
Port
P2
Num=2
Var
Eqn
Z1P_Eqn
Z1P1
VAR
VAR1
Z[1,1]=impedance impedance=2 GOhm * step((F-1Hz) - freq) + 1uOhm
FIGURE 3-4
High-pass filter circuit and symbol
3.2.4
Bias tee: The purposes of bias tee are to define the operating point of the transistor and to block the RF frequency flowing from high frequency port to the dc supply node. The circuit is fundamentally constructed of LC elements. The capacitor functions as a high pass filter that RF signal can flow indirectly between Port 3 and
Port 1 while the inductor is a low pass filter that inhibit high frequency component from Port 1 and 3 flowing to Port 2. The bias tee is shown in Figure 3-5.

18
Port 2
L i
Port 3 Port 1
C i
FIGURE 3-5
Bias tee circuit [15]
The admittance of capacitor is larger than 1 10 ω Ω and the impedance of inductor is larger than 1000 ω Ω , where the operating radian frequency ( ω ) is equals 2 π f . The low admittance provides the maximum power flow of desired RF frequency while the high inductor impedance provides the maximum reflection of a desire frequency back because of the mismatch condition of 1 k Ω from 50 Ω systems.
The value of lump elements for the gate-bias tee are evaluated and the result yields; C i
= 133 pF and L i
= 133 nH at 1.2 GHz. For the output side, the evaluation of lump elements for the drain-bias tee are C o
= 66 pF and L o
= 66 nH at 2.4 GHz.
3.2.5
Nonlinear model of the MESFET: There are three important parameters must be taken into account when designing an active frequency multiplier circuit; nonlinear model of the device depict in Figure 3-6, biasing class and stability. The device model can be physic-based model, empirical model or table-based model. The prediction of frequency multiplier behavior relies on the accuracy of device model.
CGD_PKG
0.001pF
GATE
Lgx
0.72nH
Rgx
6 ohms
CGS_PKG
0.04PF
Ldx
0.68nH
Rdx
6 ohms
Lsx
0.1nH
DRAIN
CDS_PKG
0.035PF
Rsx
0.6 ohms
SOURCE
FIGURE 3-6
MESFET nonlinear model

19
In this thesis, we use GaAs MESFET NE3210S01 form NEC the TriQuint model (TOM) of the transistor has been characterized by CEL and employed in this thesis.
3.3
Transistor operating point
In this topic, a doubler operating point for the transistor is determined. To address the problem, all termination loads are initially fixed at 50 Ω and the optimal
V
GS
and V
DS
will be determined from the optimization. From the discussions in
Chapter 2, it is suggested that the optimal V
GS
biasing is at either pinch-off or the midpoint between pinch-off and zero. The initial value of V
GS
is -1.5 volt which is approximately a pinch-off voltage of the MESFET using here. The V
DS
is also fixed to a value that the transistor does not operate in ohmic region, the V
DS
is approximately set to 2.0 volt while the input power is constantly held to 0 dBm.
First, the internal impedance of the power source and the impedance termination of second harmonic output are optimized together. The goals are to obtain the maximum fundamental power at input and maximum second harmonic power at the load 2f
0
The second step is to discover the termination load at the output and input. It is found that the termination of second harmonic at the input has effect to degrade the power of fundamental input; therefore the input termination for 2f
0
is fixed to an open circuit. The input termination of second harmonic, output termination of fundamental, and output termination of third harmonic are concurrently optimized to attain highest possible fundamental power for gate, highest possible second harmonic output, and unwanted harmonic power as low as possible for both input and output.
The ideal circuit is designed and simulated by follow the rule preceding mentioned technique. There optimization process is performed to reach two goals maximum conversion gain and other harmonics at least -20 dB. As a result, the optimal reflection coefficients of input- and output-terminating load are obtained and tabulated in table 3-1.
TABLE 3-1
Input- and output-reflection coefficients
Frequency (GHz)
Γ in
Γ out f
2f
0
0
0.93
∠ − 11 o
0.99
∠ − 48 o 0.5
∠
∠ − o
53 o
>2f
0
0.96 5 o 0.99 7 o
Those values are optimized at V
GS
= -1.5 V and V
DS
= 2.0 V. Now, the optimal
V
GS
and V
DS
will be evaluated. The V
GS
and V
DS
are swept independently and it has been discovered that for V
GS
= -0.93 V and V
DS
= 2.77 V, the second-harmonic output power and hence the conversion gain are maximum. Consequently the proposed operating point is selected at V
GS
= -0.93 V and V
DS
= 2.77 V.

20
FIGURE 3-7 Input and output harmonic power
A proposed operating point of the transistor has been optimized from the optimal harmonic termination found at V
GS
= -0.93 V and V
DS
= 2.77 V. In order to obtain the optimal harmonic terminations at a new operating point, all harmonic termination are required to be optimized. From author’s experience, if all impedances are independently optimized even with the excellent optimization goals.
The harmonic powers from the optimal termination impedance are tabulated in
Figure 3-7. The power of unwanted harmonic at output and input are very good lower all unwanted harmonic input and output power are 20 dB less than the design output power. The power of second-harmonic output is 11.357 dBm, which is 11.365 dB conversion gains.
3.4
Frequency-doubler matching network
The optimum terminations obtained from preceding section are used to systhesis the input- and output-matching networks. Here input and output matching networks will be designed separately.
Figure 3-8 shows a typical diagram of a single-ended FET frequency doubler.
The circuit consists of input matching network, transistor, and output-matching network. The input-matching network composes of fundamental frequency (f
0
) matching circuit, gate-bias circuit, second harmonic (2f reflector, drain-bias circuit and 2f
0
0
) reflector, and higher harmonic (>2f
0
) reflector while The output-matching network composes of f
0
matching circuit.

21
V
S
V
GS
Gate Bias
Circuit
Z
S f
0 matching
2f
0 reflector
Generator for f
0
>2f0 reflector G D f
0 reflector
S
V
DS
Drain Bias
Circuit
2f
0 matching
Z
L
Load for 2f
0
FIGURE 3-8
Input and output matching network diagram
The practical frequency doubler circuit was realized by microstip technology.
The substrate used throughout the designs is defined in Figure 3-9. The substrate has a dielectric constant of 3.2, conductivity of × 7 S/m, dielectric loss tangent of
0.004, substrate height of 0.762 mm, and conductor thickness of 0.035 μ m.
ε r
FIGURE 3-9
Substrate definition
3.5
The input matching network
The input matching network consists of a gate-bias tee and matching stubs. The gate-bias circuit provides the isolation of f
0
propagating to dc supply and supplies dc to the gate-source of transistor. The f
0
-matching stub is used for matching input impedance of the circuit to the 50 Ω input. The 2f
0
- and >2f
0
-reflector stubs are utilized to derogate 2f
0
and >2f
0
presenting at gate pin of the transistor. In a perfectly match and excellent harmonic terminations, the signal developed at gate pin of transistor has only fundamental component and there is on reflection of any harmonic back to the RF-power source.
The design of input matching network gate-bias circuit designed. When the gate-bias design is accomplished, the design of matching stubs will be performed. The gate-bias circuit combining with open stubs forms the input-matching network. By optimizing the input matching network with the ideal value from input-terminating impedances in section 3.3, the input matching microstrip network can be obtained.

22
3.5.1
Gate-bias tee structure: The gate-bias tee structure is depicted in
Figure 3-10. The equivalent of λ g
/ 4 ( λ g
= guide wavelength) is L and the equivalent of doubler radial stub is bandstop, that is L ′ parallel with C ′ . The equivalent circuit present in Figure 3-11, the circuit is a series of three sections of λ g
/ 4 transmission line. The high-frequency port is connected to the high-frequency circuit, which are 50
Ω systems. The series lines and radial stubs are defined in such a way that the reflection factor at the high-frequency port is an open. So the main line is not influenced by the bias-tee structure. The smallest possible width is chosen to establish a most exactly defined connection to the main line. In order to isolate of f
0
highfrequency port from the dc supply, the short-circuit stub are used to short out the fundamental frequency every λ g
/ 4 length. As the result, negligible high frequency signal can leakage at the dc port while the dc current from dc port can flow to the high-frequency port.
λ g
/ 4
λ g
/ 4
FIGURE 3-10 Bias-circuit structure
FIGURE 3-11
Bias-circuit equivalent
3.5.2
Gate-radial stub: the frequency rejection can use open stub, short stub and radial stub. Figure 3-12 shown S
21
for all. The open stub longer than other stub and short stub is difficult to fabrication, that are narrowband but the doubler radial stub is broadband and do not have multiple resonant effect which is suitable for using in frequency multiplier circuit. This is section advantage to reject the signal at DC power

23 supplies and circuit, which was flow to devices. So the radial stub is interested than other stub.
FIGURE 3-12
S
21
from open stub, short stub and radial stub
The design of gate-bias tee starts from dimensioning the radial stub. Instead of using a λ g
/ 4 -open stub, a radial stub is used as a short circuit to diminish f
0
. Since this structure sharp rejects the desired frequency considerably. Figure 3-13 shows the gate-radial stub circuit.
Angle
D
1 2
W
FIGURE 3-13
Gate-radial stub [16]

24
From Figure 3-13 the circuit presents the two-port circuit. The width of junction connecting to microwave port is designed to the highest possible impedance at 1.2
GHz. The design goal is to have a very sharp rejection of f
0
. In order to minimize the transmission of f
0
from port 1 to port 2 and vice versa, both port 1 and 2 must have maximum reflection at f
0
. By optimizing the circuit with those two goals, the optimization dimensions results as follows:
Width of feed line (W) = 0.65 mm
Outer radius of circular sector (Ro) = 25.2 mm
Angle subtended by circular sector (Angle) = 60 o
Insertion depth of circular sector in feed line (D) = 0.5 mm
(a)
-25
-30
-35
-40
-45
-50
-5
-10
-15
-20
10
5
0
0
2f
0 f
0 f freq= 1.200GHz
dBm(S(2,1))=-39.801
2f freq= 2.400GHz
dBm(S(2,1))=0.796
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
freq, GHz
3.0
(b)
FIGURE 3-14
S-parameter of gate-radial stub (a) S
11
and (b) S
21

25
The result of small-signal S-parameter analysis is illustrated in Figure 3-14.
Figure 3-14 (a) depicts the response of S
11
3.14 (b) displays the extremely low transmission from port 1 to 2 at f
0 the proposed structure provides the short circuit at f
0
. Because of the reciprocal property of the radial stub, S
11
equals S
having maximum reflection at f
0
22
and S
12
equals S
21
.
. Figure
, meaning that
3.5.3
Gate-bias circuit: In the previous topic, a gate-radial stub has been designed. The next design step is to combine the radial stubs with λ g
/ 4 microstrip lines. The gate-bias circuit is shown in Figure 3-15. The chosen impedance of λ g
/ 4 microstip line should be more than 50 Ω , therefore the narrowest width is taken. The impedance of 0.65 mm microstrip line at 1.2 GHz is 85 Ω . A capacitor of 133 pF is a filter capacitor providing a path for the high frequencies shorting to the ground. When the bias circuit is integrated with the full input matching circuit, port 1 and port 2 are connected to the high-frequency port while port 3 is connected to a dc supply. The goals of the bias-circuit design are to achieve maximum transmission of f
0
to gate and no signal leakage f
0
to the dc supply. Transmission at f
0
to the gate means large S
12 and large isolation of f
0
from the dc source means very small S
31
. As the transmission from port 1 to port 2 is very high, the reflection of port 1 itself S
11
is very low.
FIGURE 3-15
Gate-bias circuit

26
Form Figure 3-15, the gate-bias circuit has been optimized to attain very low values of S
11
, S
13
and very high value of S
12 microstrip lines follows:
at f
0
. After optimization, the dimension of
W1.2GHz@85Ohm = 0.65 mm
W1.2GHz@50Ohm = 1.79 mm
W1 = 1.4 mm
L1.2GHz@85Ohm = 40.77 mm
L1 = 2 mm
The S-parameter simulation responses of the optimized circuit are shown in
Figure 3-16.At 1.2 GHz S
11
= -44.981 dB, S
13
= -71.081 dB, and S
12
= -0.019 dB.
(a)
(b)
FIGURE 3-16
S-parameter of Gate-bias circuit (a) S
11
, (b) S
21
and (c) S
13

(c)
FIGURE 3-16 (CONTINUED)
The gate-bias tee layout is depicted in Figure 3-17.
g
/ 4
g
/ 4
FIGURE 3-17
Gate-bias tee layout
27

28
3.5.4
Input-matching circuit: The simplified input-matching network is depicted in Figure 3-18. The circuit consists of a gate bias tee and 50 Ω matching stubs. A double-radial stub connecting together with λ g
/ 4 microstrip lines of impedance higher than 50 Ω forms a structure of gate-bias tee. This bias tee provides an isolation of f
0
propagating from generator (V
S
) to DC power supply (V
GS
) and passes the negative current to the gate-source of the transistor. By considering the circuit at fundamental frequency, the virtual input impedance of transistor is equal to the conjugate of Z
,
0
. The matching stub at f
0
can be simply calculated f
0
is maximum power transfer from the generator to the gate. To determine the length of 2f
0
and >2f
0 reflectors, the network input is terminated with a 50 Ω and the network output is stimulated by a 50 source. The input-terminating reactances
Z i ,2 f
0
and
Z i f
0
are converted to input reflection coefficients Γ i
,2 f
0
and Γ i f
0
. The circuit is then performed small-signal simulation at 2f
0
and >2f
0
. The optimum length of the reflectors occurs when the reflection coefficients seen from microwave port are equal to Γ i
,2 f
0
and Γ i f
0
at 2f
0
and >2f
0
, respectively. The simulated dimensions are shown in Table 3-2.
TABLE 3-2
Simulated dimensions of input matching circuit
Input 2f
0
Length
Optimum value
Description Parameter
(mm)
L_SMA_Feeder 5
Reflector Line
W1.2GHz@50Ohm
L1@2f0_series_reflector
L2@2f0_series_reflector
1.789030
5.84937
1.05637
L1@2f0_open_stub 18.6716
Input 2f
0
Reflector Line Width W1.2GHz@50Ohm
Input >2f
0
Reflector Line
Length
L3@2f0_series_reflector
1.789030
10
L2@2f0_open_stub 14.8682
Input >2f
0
Reflector Line
Width
W1.2GHz@50Ohm 1.789030
Input f
Input f
0
0
Matching Line Length
Matching Line Width
L1_input 10.0949
L2_input 36.5606
L3_input 2.56498
W1.2GHz@50Ohm 1.789030

29

30

31
3.6
The output-matching network
The structure of an output-matching network is similar to the input-matching network. There are some slightly changes in the order of the matching stubs are type of utilized stub. The output-matching network proposed in Figure 3-8 consists of a drain-bias tee and matching stubs. The drain bias circuit isolates 2f supply and carries direct current to the drain-source of transistor. The f
0 extended designed as a fundamental frequency filter. Its function is to minimize f
0 appeared at the load as much as possible. The 2f
0
0
propagating to dc
-reflector is
reflector matches the secondharmonic power to the load. In a perfect match and best harmonic terminations, the load has only second harmonic.
The design process of output matching network is a similar to that of the inputmatching network. The alteration is only the change of operating frequency from 1.2
GHz (f
0
) to 2.4 GHz (2f
0
). The design starts from dimensioning drain-bias circuit and later the full matching circuit developed. The drain-bias circuit combining with the open stubs forms the input-matching network. Instead of using an open stub for f reflector, a bandpass filter center at f
0
0
is used. By optimizing the output-matching network with ideal value of output terminating impedances, the equivalent microstrip lines for output-matching network is synthesized.
3.6.1
Drain-bias tee structure: The drain-bias tee structure is similar to gate depicted in Figure 3-10. The circuit is designed and optimized at second-harmonic at
2.4 GHz instead of 1.2 GHz.
3.6.2
Drain-radial stub: The design follows the same steps as in section 3.5.2 but the operating frequency is 2.4 GHz. The radial stub is designed for short circuit at 2f
0
.
The structure for drain-radial stub is the as same the gate-radial stub circuit structure show in Figure 3-13.
The width of radial-stub T-junction should be satisfied for very high impedance as well as maximum attenuation at 2f
0
. To minimize the transmission of from port 1 to port 2 at 2f
0
, maximum reflection at 2f
0
must be selected. By optimizing the circuit with those two goals, the optimum results are at Figure 3-11. The dimensions follow:
Width of feed line (W) = 0.65 mm
Outer radius of circular sector (Ro) = 14.287 mm
Angle subtended by circular sector (Angle) = 60 o
Insertion depth of circular sector in feed line (D) = 0.54 mm

32
(a)
(b)
FIGURE 3-19 S-parameter of drain-radial stub (a) S
11
(b) S
21
The results of S-parameter simulation are depicted in Figure 3-19. Figure 3-19
(a) presents the response at S
11
, which has maximum reflection of 2f
0
. Figure 3-19 (b) shows the extremely low transmission at 2f
0
from port 1 to port 2.
3.6.3
Drain-bias circuit: In the previous section, a drain-radial stub has been designed. The combination of radial stubs with λ g
/ 4 microstip lines froms a drainbias tee. The drain-bias circuit is illustrated in Figure 3-20. The width of λ g
/ 4 microstrip line is identical to that of gate-bias tee. The goals of the bias circuit design are to have the highest transmission of 2f supply at 2f
0
. The highest 2f
0 very high while the isolation of 2f
0
0
to load and no signal transmits to the dc
power delivers to the load means that the S
12
must be
to the dc supply means to a very low value of S
13
.
The drain-bias circuit was optimized to attain very low value of S
11
, S
13
and very high value of S
12
at f follows:
0
. After optimization, Figure 3-20 has the dimension

W2.4GHz@85Ohm = 0.65 mm
W2.4GHz@50Ohm = 1.79 mm
W1 = 1.4 mm
L2.4GHz@85Ohm = 20.37 mm
L1 = 2 mm
33
FIGURE 3-20 Drain-bias circuit
The S-parameter simulation responses of the optimized circuit are depicted in
Figure 3-21. We obtain S
11
= -39.644 dB, S
13
= -63.641 dB, and S
12
= -0.022 dB.

(a)
(b)
(c)
FIGURE 3-21
S-parameter of Gate-bias circuit (a) S
11
, (b) S
21
and (c) S
13
34

The drain-bias tee layout is depicted in Figure 3-22.
35
λ g
/ 4
λ g
/ 4
FIGURE 3-22
Drain-bias tee layout
3.6.4
Output-matching circuit: The output matching network configuration is depicted in Figure 3-23. The circuit topology is similar the input matching network but there are little changes in the order of the matching stubs. The circuit comprises of drain-bias tee and matching stubs. The drain bias circuit isolates 2f supply and carries direct bias current to the transistor. At 2f
0
0
signal from DC
, the FET- virtual output impedance is equal to the conjugation of
2f
0
Z o ,2 f
0
.The selection of appropriates length of
output-matching stub provide maximum output for 50 Ω load. In order to determine the length of output reflector, the virtual-output impedance and the load 50
Ohm are replaced by 50 Ohm resistor and small-signal microwave port respectively.
The output-terminating reactances
Z
,
0
and coefficients Γ
,
0
and Γ o f
0
Z o
> f
0
are converted to output reflection
. Small-signal simulation at frequency f
0
and >2f
0
reveals the values of reflection coefficients at signal port. The suitable length of reflector obtained when the values of reflection coefficients seen from the port are equal to
Γ
,
0
and Γ o
> f
0
at frequency f
0
and >2f
0
respectively. When both input- and outputmatching network are combined together, the microstrip circuit design of frequency doubler is complete. The performances of doubler circuit in terms of conversion gain and harmonics suppression are in the same degree as ideal values given in Section 3.3.
The simulation dimensions are show in Table 3-3.

36
TABLE 3-3
Simulated dimensions of output matching circuit
Optimum value
Description Parameter
(mm)
Output Reflector Line Length
L@f0_series_reflector 10
L@f0_open_stub 39.35
Output Reflector Line Width W2.4GHz@50Ohm 1.788660
L1_output 5.69287
Input 2f
0
Matching Line Length L2_output 38.2869
L3_output 16.7045
Input 2f
0
Matching Line Width
Output 50 Ω Line Length
Output 50 Ω Line Width
W2.4GHz@50Ohm
L_SMA_Feeder
W2.4GHz@50Ohm
1.788660
5
1.788660

37

38

39
3.7
A single-ended FET frequency doubler
Based on the designs obtain in section 3.5 and 3.6, a single-ended FET frequency doubler was designed. The circuit diagram of proposed doubler is shown
Figure 3-24.
FIGURE 3-24
A single-hybrid 1.2/2.4 GHz frequency doubler
The circuit was design with both small-signal analysis and harmonic balance
(HB) simulations. Its operating points are
Gate-source voltage, V
GS
= -0.93 Volt
Drain-source
Power input,
DS
P_in = 0 dBm
The tabulated results Figure 3-25 shown the input- gate- drain- and outputharmonic powers. Good conversion gain and low unwanted response are obtain from the design.
Power input (dBm)
Pin_fund_dBm
-0.336
Pin_2nd_dBm
-52.401
Pin_3rd_dBm
-49.418
Pin_4th_dBm
-41.671
Gate power input (dBm) Drain power input (dBm)
Gate_fund_dBm
-6.842
Drain_fund_dBm
-5.920
Gate_2nd_dBm
-27.217
Gate_3rd_dBm
-41.972
Gate_4th_dBm
-28.145
Drain_2nd_dBm
7.078
Drain_3rd_dBm
-10.181
Drain_4th_dBm
-4.964
Power Output (dBm)
Pout_fund_dBm
-55.333
Pout_2nd_dBm
6.882
Pout_3rd_dBm
-47.979
Pout_4th_dBm
-20.920
Conversion Gain (dBm)
Doubler_Conversion_Gain
7.218
FIGURE 3-25
HB-simulation result of the single-ended FET frequency doubler

40
Figure 3-26 displays the power spectrum at the gate pin. It shows that the fundamental frequency is the highest power while the powers of other harmonics are kept small. The spectrum of output power at load is depicted in Figure 3-27. It is expected that the fundamental frequency and third harmonic are required to be suppressed at the output side. As it is shown, those two harmonics are well suppressed lower than -50 dBc.
FIGURE 3-26 Power spectra at gate of transistor
FIGURE 3-27
Power spectra at load
The input signal is 1.2 GHz sinusoidal signal and the output signal is 2.4 GHz sinusoidal signal. The amplitude of voltage designates the still presence of other harmonics than 2f
0
, show in Figure 3-28.

41
FIGURE 3-28
Time domains of input and output voltage
3.7.1
Variation of input power: a simulation of input power sweep has been conducted to discover triplication behavior of the circuit that knows the input power can feed in the input port. The input power of doubler circuit has been swept from -20 to 10 dBm while the input frequency. Figure 3-29 (a) depicts the harmonic output power and Figure 3-29 (b) shows the conversion gain (The conversion gain is the power level difference between the output signal and the input signal, an amount that is measured in decibels (dB) as a positive number.) variation with swept-input power.
When the input power more than -6 dBm. The harmonics output are same at 5 dBm that conversion gain is the output power minus the input power. It is conspicuously seen that the maximum-conversion gain occurs at -6 dBm power input.
(a)
FIGURE 3-29
Input power as (a) Harmonic-output power and (b) Conversion gain

42
(b)
FIGURE 3-29 (CONTINUED)
3.7.2
Bandwidth of a single-ended FET frequency doubler: The bandwidth
(BW) is usually defined as the difference between the lower and upper half power points. This is therefore also known as the − 3 dB BW. A single-ended FET frequency doubler has been conducted a frequency sweep. The input power was sustained to the initial values at 0 dBm. Figure 3-30 (a) plots harmonic-output power versus the frequency swept from 1 GHz to 1.3 GHz. Figure 3-30 (b) presents the conversion gain plot. Because the circuit has been designed and optimized at 1.2 GHz, the conversion gain is highest at this frequency. Both -3 dB point marks read 1.15 GHz and 1.225
GHz. Respectively, resulting 75 MHz bandwidth.
(a)
FIGURE 3-30 Fundamental frequency as (a) Harmonic-output power and
(b) Conversion gain

43
(b)
FIGURE 3-30 (CONTINUED)
3.8
Layout capture of a single-ended frequency doubler
The optimized frequency doubler designed with microstip technology was fabricated on circuit board. The circuit board was implemented utilizing a photolithographic process. Figure 3-31 shows the layout of the doubler design.
FIGURE 3-31 Layout of frequency doubler
The photograph of the fabricated circuit is displayed in Figure 3-32 by the milling machine. The circuit size is 12 × 15 cm 2 . The measurement was carried out at
KMITNB and the results are discussed in Chapter 4.

FIGURE 3-32
Image of practical frequency doubler
44

A single-ended FET frequency doubler was design and implemented. The measurements have been carried through the microwave transition analyzer, Hewlett
Packard 8564E. The optimal operating points of the circuits were determined. The frequency and power sweep was performed. The measurement results were compared with the simulation result. The discussions are given here.
4.1
The measurement of a single-ended FET frequency doubler
Figure 4-1 shows the measurement setup for a single-ended FET frequency doubler. The DC power supplies are set at -0.93 V for V
GS
and 2.77 V for V
DS
. The signal generator is set 0 dBm at 1.2 GHz for input power and connected the spectrum analyzer to the output port.
FIGURE 4-1 Measurement setup for a single-ended FET frequency doubler
From the design, the manual sweep of V
GS
and V
DS
has been performed to determine the optimal operating point of the doubler where the conversion gain is highest and there is no steep slope on the main lope. The steep slope on the main lope near the second harmonic suggests the oscillation of the circuit. From the fine-tuning of biasing point was found at V
GS
= -0.98 V and V
DS
= 2.94 V, with an uncelebrated measurement proposed the output at 1.185 GHz with 5.3 dB conversion gain.
4.2
Harmonic-output power
The designed single-ended frequency doubler is realized by 10
μ m resolution
PCB-engraving machine and shown in Figure 3-32. The fabricated doubler circuit is found to have 5.3 dB conversion gain at input frequency of 1.185 GHz and 0 dBm power input. The frequency 1.25% shifted down from 1.2 GHz to 1.185 GHz arises from the widening of microstrip width during the PCB engraving and can be mechanically compensated by feeding the engraving bit in the PCB deeper. By comparing the simulation result at 1.2 GHz with the measured performance at 1.185
GHz as listed in Table 4-1

46
TABLE 4-1 Output spectrum comparison between simulation and measurement at
P in
= 0 dBm
Simulated results Measured results
Frequency
(GHz)
Output Power
(dBm)
Output Power
(dBm)
Frequency
(GHz)
Error of
Output Power (%)
-22.76 2.7
7.2 -30.80 4.61
10
0
-10
-20
-30
-40
Simulated
Measured
-50
-60
1 2 3 4 5 6
Frequency (GHz)
7 8 9 10 11
FIGURE 4-2 The output spectra power between simulation and measurement

47
For the fabricated circuit, the fundament frequency dominating the highest second-harmonic output is distorted to a lower frequency from the designed value at
1.2 GHz. The change of operating frequency can be caused by the uncertainties of the circuit, for example, the residual error of microstrip line model, the imprecision of microstrip substrate preparation reflex the tolerance of microstip lines and the model of bonding wire. The model of bonding wire used in the simulation is a straight gold conductor over ground but physically, the bonding wire is not simply a stretch line but bending. In the microwave region, the bonding filament carries a microwave signal behaving like antenna; the radiation effect must be included to attain the exact model of bonding wire. Although, the simulation had used an exact model of bonding wire, the error were still inherent due to the physical placement of bonding wire elongating or shortening the bonding length degrading the doubler performance.
4.3
Conversion gain
In Figure 4-5 shows the fabricated frequency doubler can operated with conversion gain over a large input-power span from -15 dBm to 6 dBm and the best operating frequency at 1.185 GHz that was the maximum conversion gain is 7.8 dB occurs at -6 dBm power input. The measured output power harmonizes with the simulated responses. The second-harmonic output deviates about 19% from simulation.
The lower second harmonic output and conversion gain can be caused by losses of low-frequency chip capacitors C at input and C at output, the MESFET, the substrate, and the attenuations of the SMA connectors.However, the realized circuit still dominates excellent performance.
4.4
3-dB Bandwidth
FIGURE 4-3 Frequency response of doubler at P in
= 0 dBm

48
In order to determine the operating bandwidth of frequency doubler the input power is fixed to 0 dBm and the fundamental-frequency input is swept from 1.11 to
1.24 GHz for the simulation and from 1.12 to 1.22 GHz for the measurement. The responses are delineated in Figure 4-3. The trend of the curves is parallel which implies the validation of this design technique. The bandwidth of practical doubler is
75 MHz reading from the graph.
The approximation of bandwidth is rather low that is 70% deviated from the simulation. The more accurate bandwidth can be attained by performing a small frequency sweep step from 1.14 to 1.225 GHz to minimize interpolation errors but the fine frequency sweep may not deduce very much change of bandwidth value.
4.5
Power sweep
The power sweep has been performed concurrently with frequency sweep. The power has been swept from -20 dBm to 10 dBm. Figure 4-4 (a) and Figure 4-4 (b) shows the second harmonic output power and the conversion gain as the variation of input power at fundamental frequency equal 1.2 GHz. The increasing of input power increases all output harmonics slight, not a large change as the input magnitude. It mans the doubler is nearly or already saturated at power input that was designed.
10
-5
-10
5
0
-15
-20
-25
Measured
Simulated
-30
-21 -18 -15 -12 -9 -6 -3
Input power (dBm)
0 3 6 9 12
(a)
FIGURE 4-4 Power sweep of doubler at f
0
(sim) = 1.2 GHz and f
0
(meas) = 1.2 GHz
(a) Output power and (b) Conversion gian
The conversion gain is dropped very fast for higher power input. The reason is that the fabricated doubler circuit has already saturated at a low-input power and the higher input power cannot achieve very much change of second harmonic output.

14
12
10
8
2
0
-2
-4
-6
6
4
-21 -18 -15 -12 -9 -6 -3
Input power (dBm)
0
(b)
FIGURE 4-4 (CONTINUED)
3
Measured
Simulated
6 9 12
49

In this thesis, a novel synthesis technique of impedance matching network is proposed. The idea is to first terminate the transistor with a set of ideal impedances with different frequency. Those impedance terminations are equivalent to the conjugation of the internal input and output impedances of the transistor. As a result, the microstrip matching networks can be easily designed to match with the input and output impedances of the nonlinear device by conventional network synthesis. To validate this design technique, a single-ended FET 1.2/2.4 GHz frequency doubler for
ISM band is demonstrated.
A single-ended FET frequency doubler circuit was designed on GML1000 substrate and using ADS for designed, The circuit was fabricated by PCB engraving machine (LPKF), and measurement power spectrum of mixer were performed using spectrum analyzer.
5.1 Conclusions
A single-ended FET frequency doubler is proposed in master thesis. The measured performances of fabricated circuit agree very well with the simulated results.
The realized 1.2/2.4 GHz frequency doubler proposes excellence performances and the measured bandwidth is covering ISM band design range RF from 1.135 to 1.21
GHz. So, it was 75 MHz operating bandwidth. The circuit suppressed unwanted harmonic less than -20 dBm. The maximum conversion gain is 7.8 dBm at 1.185 GHz when the input power equal -6 dBm. The operating frequency at 1.185 GHz was best to work.
5.2 Problem and suggestion for future work
The designing problems of a single-ended FET frequency doubler were following: the distorted output power at the spectrum that problem is caused from loss in coaxial cable, SMA connector and chip capacitor which can be de-embedded by using on wafer-measurement system. The frequency shifting problem is result from the incorrect PCB engraving the incorrect PCB engraving. The compensating frequency will use for solve the problem.

1.
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Kanakawa and Y. Kobayashi. “A 60 GHz MMIC Stabilized Frequency
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Y. Iyama, A. Iida, T. Takagi, and S, Urasaki. “Second-harmonic reflector type high-gain FET frequency doubler operating in K-band.” IEEE MTT-S Int.
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D.G. Thomas Jr and G.R. Branner. “Optimization of active microwave frequency multiplier performance utilizing harmonic terminating impedances.” IEEE
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El Rabaie S., Stewart J. A. C., Fusco V. F. and McKeown J. J. “A novel approach for the large signal analysis and optimization of microwave frequency doublers.” IEEE MTT International Microwave Symposium
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Branner G. R., Thomas D. G., Jr and Kumer B. P. Radio Frequency Multipliers. n.p., 1999.
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Colantonio P., Giannini F., Leuzzi G. and Limiti E. Non-linear design of active frequency doubler. Microwave Computer Aided Eng.(USA), 1999.
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Schmale I. and Kompa G. “A stability-ensuring procedure for designing high conversion-gain frequency doubler.” IEEE MTT International Microwave
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Gonzalez G. Microwave transistor amplifiers analysis and design. 2nd Ed. New
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APPENDIX A
DATA SHEET NE3210S01

53

54

55

56

57

58

59

60

61

APPENDIX B
DATA SHEET GML1000

63

APPENDIX D
ITC-CSCC2006

67

68

69

70

71
BIOGRAPHY
Name : Miss Surunya Lamaiphan
Thesis Title : Impedance Matching Network Synthesis Technique for a Singleended FET Frequency Doubler Design
Major Field : Communication Engineering
Biography
She graduated with Bachelor of Engineering in Electrical Engineering
(Communications) from King Mongkut’s Institute of Technology North Bangkok in
2003 and study in Master of Science in Communication Engineering at King
Mongkut’s Institute of Technology North Bangkok in the Department of
Communication Engineering, Faculty of Sirindhorn International Thai-German
Graduate School of Emgineering (TGGS) in 2006. Her personal interest is RF active circuit. She can be reached at aomkmitnb@hotmail.com.