Journal of the Korean Physical Society, Vol. 35, December 1999, pp. S893 ∼ S896
K. H.
Kim
, S. W.
Hwang
∗
, S. W.
Kim and J. W.
Park
Department of Electronics Engineering, Korea University, Seoul 136-701
H. J.
Chung and S. H.
Yoon
Samsung Electronics, Suwon 449-900
An efficient off-chip impedance matching technique of RF silicon IC’s is presented. SPICE simulation of the chip including the package components such as lead frames, bonding wires, and pads is shown to be adequate enough for the construction of the matching networks and the S-parameter measurements of the inputs are not needed. Experimental results show that satisfactory off-chip impedance matching has been achieved using this technique. Simulation result of IF signal well describes measured time domain, and the measured input reflection coefficient ( S
11
) is shown to reach near the − 25 dB point.
I. INTRODUCTION
Most RF IC’s for wireless communication system has so far consisted of two major parts: one is the baseband block using CMOS and the other is the RF-band block using high-speed, low-noise GaAs or BiCMOS [1]. But the progresses of device fabrication technology [2] and needs for wireless communication system with low-power operation has increased the focus on the integration of
RF building blocks into a CMOS single chip solution [1].
Many CAD tools such as HP MDS, EEsof, etc.
, provide relatively accurate RF-band simulation results ( e.g.
input impedance, S-parameter, noise figure, etc.
) of discrete components so that circuit designers can effectively implement impedance matching networks.
However, these RF CAD tools represented by the S-parameter are not completely compatible with SPICE which is most widely used for CMOS IC designs.
The usual way of implementing impedance matching network is by utilizing the S-parameter measurement of the input ports. However, this method involve complicated embedding-deembedding procedures and sophisticated calibration techniques. Furthermore, in the case of N-port circuit such as silicon RF IC’s, all the ports except for the measured port should be properly terminated.
In this paper, we present an efficient impedance matching technique of silicon RF IC’s.
Utilizing adequate
SPICE equivalent circuits of the package with reasonable parameters, it has been possible to obtain input impedance of the chip without cumbersome S-parameter
∗
E-mail: swhwang@kuccnx.korea.ac.kr
measurements. Experimental results with the impedance matching network designed from the calculated input impedance demonstrate satisfactory performance of the
RF/IF downconverter chip for PCS application.
II. SPICE CALCULATION OF THE INPUT
IMPEDANCE AND THE CONSTRUCTION
OF THE IMPEDANCE MATCHING
NETWORKS
-S893-
The basic idea of impedance matching is that by inserting impedance matching networks, each pair of impedances has complex conjugate counterparts. When analyzing N-port circuits, impedance elements are expressed by Eq. (1), where Z ij is the i -th port impedance relative to the j -th port source, V i i -th port, and I i is the voltage at the is the current source at the i -th port.





V
1
V
2
.
.
V
N





=





Z
11
Z
12
.
.
Z
1 N
Z
21
. . Z
N 1
.
. .
.
.
. .
.
.
. .
.
.
. . Z
N N
 








I
1
I
2
.
.
I
N





(1)
When I i
= nonzero and I j
( j = i ) = 0 in the Eq.
(1), the diagonal element of the impedance matrix ( i -th port input impedance) relationship,
Z ii is expressed by a simple linear
Z ii
=
V i
I i
[Ω] (2)
Then the input impedance of each port can be obtained from Eq. (2) by simulating SPICE equivalent circuits of the chip. Here the coupled impedance elements

-S894Journal of the Korean Physical Society, Vol. 35, December 1999
Fig.
1.
(a) A schematic block diagram of the RF/IF down-converter chip, (b) The equivalent circuit of the package block, and (c) The equivalent circuit of the internal interconnection.
Z ij
( i = j ) are neglected for the design of the impedance matching block and a reasonable impedance matching can still be obtained as shown below.
In this work, the RF/IF down-converter chip is based on CMOS technology and a low-if topology is adopted.
Contrary to the conventional low-if topology that uses four mixers and two quadrature generators [3], this one has two mixers and three quadrature generators to reduce power consumption. Two RF-band signals which are offset by the IF frequency (5 MHz), are applied to 3 dB baluns and the resulting four RF-band signals ( LOP ,
LON , RF P , RF N ) are mixed to construct the IF output signals. Figure 1(a) shows a schematic block diagram of the RF/IF down-converter chip.
The general-purpose package (MQFP 100) which is inadequate for high frequency applications has been intentionally used to clearly demonstrate the off-chip impedance matching effect.
The blocks denoted by
P ad P kg , P ad P kg Coup LO , P ad P kg Coup RF in
Fig. 1(a) are packaging blocks which include lead frames, bonding wires, and pads. Figure 1(b) shows an equivalent circuit for the SPICE calculation of those blocks. A
3-dimensional field solver MAXWELL-SI [4] has been used to extract the electrical parameters of the lead frame. Figure 2(a) shows the self inductance ( L
LS
) and the mutual inductance ( L
LM
) of the lead frame as a function of the pin number. While the longest pin (pin #1) has L
LS of 10 nH, the shortest pin (pin #15) has the value of 5.67 nH. The value of L
LM is distributed within
Fig. 2. (a) Calculated self and mutual inductances of the lead frame and (b) Calculated self and coupling capacitances of the lead frame.
3 to 6 nH, and is comparable to L
LS of pin #15. The calculated self capacitance ( C
LS
) and the coupling capacitance ( C
LC
) are summarized in Fig. 2(b). The value of C
LS and C
LC and C
LC are strong function of the pin position is not negligible to C
LS
(1 .
1 < C
LS
< 2 .
3 pF,
0 .
5 < C
LC
< 1 .
0 pF). The value of R
L is approximately a few mΩ. The inductance of the bonding wire ( L
B
), and the capacitance/resistance of the pad ( C
P
/R
P
) have the value of approximately 4 nH, 1.5 pF, and 70 Ω respectively [5].
Within the frequency range of several GHz, the length of the internal interconnection is much shorter than the wavelength of the signal. In this case, the propagation in the interconnection lines is in the slow-wave mode [6] and a simplified 2-line 3-section RF model [7] is enough for reasonable simulation results.
The T rms LO and
T rms RF blocks in Fig. 1(a) denote these internal interconnections including the coupling effects, and the equivalent circuit is shown in Fig. 1(c). An analytic formula [8] has been used to calculate the R , L , C , and
G of the interconnection. The value of R is distributed in the range from 5.47 to 11.8 Ω and the distribution of the value of C
X and C
Y
, self capacitances of the lines is from 14.0 to 45.73 fF. The coupling capacitance C i is obtained from a 3-dimensional interconnection simulator RAPHAEL [9] and has the value of 8.05 fF. Finally,

An Efficient Off-chip Impedance Matching Technique of L-band Silicon Integrated Circuits- K. H.
Kim et al.
-S895-
Fig.
3.
The constructed test board including the impedance matching network.
Fig. 5. The bbip and bbin signal measured from the chip with impedance matching network.
Fig. 4. The bbip and bbin signal measured from the chip without any impedance matching network.
Fig. 6. The measured and simulated S
11
.
LOW IF block, in Fig. 1(a), consisting of CMOS circuits are simulated by the usual SPICE netlist provided by the foundry [10].
The input impedance calculated from Eq. (2) in the
N-port system of Fig. 1 (a) is 25 .
11 + j 65 .
81 Ω for LOP,
25 .
44 + j 64 .
06 Ω for LON, 18 .
77 + j 46 .
99 Ω for RFP, and
18 .
35 + j 48 .
15 Ω for RFN at the operating frequency of
1.86 GHz. The magnitude of the reactance of the lead frame and the bonding wire ( jωL
LS
10
9 × (10 + 4) × 10
− 9 ≈
+ jωL
B
= j 1 .
9 ×
30 Ω) is smaller than that of the pad and the load reactance (1 /jω [ C
P
10 9 × (1 × 10
− 12 × 1 × 10
− 12 )] ≈
//C
L
] = − j 1 / [1 .
9 ×
1000 Ω). A simple summation of these two values leads to a capacitive input reactance. However, the total reactance in the calculated input impedance is found to be inductive.
Impedance matching networks have been implemented by adopting basic impedance matching theory [11], and using microstip lines and stubs. Figure 3 shows the test board with off-chip impedance matching blocks.
ure 5 shows the measured bbip and bbin signal when the impedance matching network was used. Almost zero phase error between the bbip and bbin signal and no distortion had been found in the measured data. The open and filled circles are the SPICE simulation results using the same equivalent circuits and parameters as in the case of input impedance calculation for the 4 mV and the phase error is 10
◦
. Figure 6 shows the measured and simulated S
11 as a function of the frequency. The target frequency of the matching network is 1.86 GHz and the measured S
11 exhibits a minimum at 1.92 GHz.
This is acceptable for the down-converter chip, but further improvement is expected to be easily achieved by the refinement of equivalent circuit and the parameters.
III. MEASUREMENT RESULTS
Figure 4 shows the IF output signals (bbip and bbin) measured from chip a when bread board and socket are used to connect the chips. The bbip and bbin signals are supposed to have the same amplitudes and 180 ◦ phase difference but the measured result showed only 21 .
6
◦ phase difference and severely distorted waveforms. Fig-
IV. CONCLUSIONS
An efficient off-chip impedance matching technique of RF silicon IC’s is presented.
SPICE simulation of the chip including the package components such as lead frame, bonding wires, and pads is shown to be adequate enough for the construction of the matching networks.
Experimental results with the matching network designed from the calculated input impedance demonstrate satisfactory performance of the RF/IF down-converter chip for PCS application.

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ACKNOWLEDGMENTS
The authors wish to acknowledge the financial support of the Korea Research Foundation made in the program year of 1999 and Samsung Electronics.
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Journal of the Korean Physical Society, Vol. 35, December 1999
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