Universal and Reconfigurable to UPS Active Power
Filter for Line Conditioning
Fermín Barrero, Member, IEEE, Salvador Martínez, Senior Member, IEEE, Fernando Yeves, Member, IEEE,
Francisco Mur, and Pedro Mª Martínez
Abstract—This paper describes an improved universal active
power line conditioner designed to attenuate every disturbance in
the electric power system and critical loads, except frequency variations. The circuit has a series voltage filter and a parallel current
filter interconnected through a shared dc bus. In case of a supply
interruption, the current filter reconfigures to UPS and feeds a preselected 20% of load during 500 ms at the expenses of the dc bus.
Over previous reconfigurable solutions, the input and output series static switches have been eliminated improving the reliability,
efficiency and cost. Optional parallel LC tuned current filters have
also been proved to be control compatible. The search has been
guided by an iterative analysis+synthesis cost comparative method,
initiated in previous works, showing the cost of the components
involved in each explored topology. Experimental results on three
laboratory models and a 400 kVA industrial prototype validate the
topology and suggest improvement of some control loops.
Index Terms—Active filter, hybrid current filters (new index
term proposed), load flow control, power conditioning, power
line filter, power quality, pulse with modulation, uninterruptible
power systems.
I. INTRODUCTION
HE demand for a better quality in the electric grid and the
increase of disturbing loads have promoted the appearance
of the so called line conditioners based on active power filters
as one of the possible solutions. Compared with a traditional
on-line uninterruptible power supply (UPS), they normally provide to the load a worse voltage wave but they are cheaper and,
in the sophisticated versions, ameliorate the current harmonics
injected to the mains by UPS variants with poor input rectifier.
Combining one parallel (with regard to the load) current active filter and one series (with regard to the load+current filter
ensemble) voltage active filter has demonstrated to be one of
the most general and economical solutions to eliminate both the
current disturbs injected by the load to the grid (solved by the
current filter) and the voltage disturbs that the grid can show to
the load (solved by the voltage filter).
T
Manuscript received November 14, 2001; revised July 18, 2002. This work
was supported in part by the Spanish R&D Electrical Plan under under identification P.I.E. 132.206.
F. Barrero is with the Department of Electrical Engineering, Universidad de
Extremadura, Badajoz E 06006, Spain (e-mail: fbarrero@unex.es).
S. Martínez, F. Yeves, and F. Mur are with the Department of Electrical,
Electronic and Control Engineering, Universidad Nacional de Educación a
Distancia (UNED), Madrid E 28040, Spain (e-mail: smartine@ieec.uned.es;
fyeves@ieec.uned.es; francisco.mur@ieec.uned.es).
P. M. Martínez is with the R&D Electrical Lines Division, Iberdrola S.A.,
Bilbao E 48008, Spain (e-mail:pedro.mcid@iberdrola.es).
First concepts on active filters, as generators of the nonideal
component of a voltage or current wave, appear in the seventies
and early eighties [1]–[3], [5], and the hybrid (passive plus active) filter concept is established by the late eighties and early
nineties [4], [6]. The search for a universal (or unified) line conditioner can be dated in the nineteen decade, first as an interactive and self-feed combination of current filter and voltage filter
intended for power flow control [7], then adding the reconfiguration of the current filter to voltage inverter for feeding part
of the load in case of a sustained line interruption [8], [9], [11],
[16]. This improved universal line conditioner can reduce every
voltage and current disturb, competing with the UPS except in
frequency correction.
The ACCIONE project, integrated in the Spanish Electric Research Program (PIE 132.206), began in 1990 to investigate the
application of the new active filters to the power quality for low
voltages distribution lines in the range of 25–1000 kVA. One
technical and economical summary of the first solutions explored can be seen in [24]. The search for more complete topologies lead to an universal line conditioner [16] having over other
solutions [7], [10], [13], [21], the ability to eliminate voltage
interruptions in a selected part of the load, due to the reconfiguration of the power circuit and the control program of the current
filter to act as a voltage inverter.
The new topology shown here improves the first version in [8]
and [16] by means of a new maneuver strategy for the reconfiguration to UPS which eliminates the input and output series static
switches rated to nominal current plus overload. It remains an
unique maneuver switch rated to less than half of nominal load
and located out off the main current stream. Then, the reliability,
efficiency and cost are improved.
Furthermore, the topology gains generality by adding one or
several optional LC filters, tuned to low frequency current harmonics, in parallel with the active current filter [23]. This hybrid
configuration for the current filter can be convenient in cases
when a substantial part of the nonideal load current is composed
by low and constant frequency harmonics. It has been proved
by experiment than the resonance likely to appear between the
mains impedance and the LC filters can be damped by an appropriate control of the, now reduced in power, active current
filter which is dedicated also to compensate the high frequency
components in the load current.
II. SPECIFICATIONS
In general, it is expected from an universal line conditioner
to reduce or eliminate every line disturbance (except frequency,
reserved for the UPS) as detailed in Table I. Intended for such a
TABLE I
DISTURBANCES REDUCED OR ELIMINATED AND SPECIFICATIONS
Fig. 1. Schematics of the analysis+synthesis cost comparative method.
The results are in one table showing the rates of the main components for
every power topology solution investigated, transformed in terms of actual
ready-to-use standard components price lists.
general compliance, the designed line conditioner series has the
main specifications, also shown in Table I.
can be easily obtained from an up-to-date price list of common
use components (
).
III. ITERATIVE ANALYSIS+SYNTHESIS COST COMPARATIVE
SEARCH METHOD
The choice of power topology is based on a previous solutions research process, taking into account technical and economics aspects. Fig. 1 shows a synthetic vision for the described
method. For a more detailed explanation, see [24]. The method
is made concrete in the following steps:
A. Analysis: Power Circuit Equations
This step is the traditional attainment of the equations
showing the physical variables (
) time evolution, as a
function of the components rates (
). It is repeated for
several topologies, 1 to .
B. Synthesis: Component Synthesis Equations
They give the components rates (
tion of equipment specifications (Spec)
) as a func-
C. Transformation: Variants Transformations
They show the relationship among component rates for those
groups of circuits that are variants of an unique topology, and
obtain those rates for a new variant (
) as a function
of the rates of an already known variant (
).
D. Standardization and Cost
Formulas for transformers, coils, capacitors, electronic devices, etc, that transform the actual component rates (
)
into standard components rates of similar economical cost
(
). So, the cost of the actual components (
)
E. Comparison: Comparative Table
Finally, a table shows, for each topology and variant, their
basic performances, synthesis equations, standard component
rates, the component usage coefficients and their economical
cost. (The usage coefficient indicates the relationship among the
equipment output rated power and the sum of the power rate of
a main group of components standardized in an specific way.)
IV. POWER TOPOLOGY
The conditioner (see Fig. 2) has, per phase, one series voltage
active filter (VAF), which cancels the voltage perturbations
coming from the mains to the load, and one parallel current
active filter (CAF) which cancels the non ideal component
that the load demands from the mains. The current filter also
feeds the voltage filter through one common dc bus and, in
case of a mains sustained interruption, reconfigures to voltage
inverter and feeds a critical part of the load. As the dc bus is
common for all the phases, the current filters can compensate
load current unbalance transferring energy from one phase to
another. The voltage filters can also compensate mains voltage
unbalance at the expense of the current filter energy support. In
this way, the grid is seen by the load as an stiff voltage source
and the load is seen by the grid as an resistive balanced load.
Due to functional independence of the filters (except in the
overall energetic balance), the current filters are also able (while
compensating the nonideal components of load current) to act
as reactive power generators dedicated to compensate certain
selected upstream mains area.
Fig. 2. Universal power conditioner based on active voltage and current
filters. Three-phase block diagram. The energetic interconnection among
phases through one common dc bus allows the reduction of every nonideal
behavior both in the load current and in the line voltage.
Fig. 3. One phase circuit. In the dotted line appears optional LC resonant
current filters for low-order harmonics (5 ; 7 ; 11 ; . . .). Critical load (CL)
and the noncritical (NCL) have been rated 20% and 80%, respectively, in the
3- and 400-kVA prototypes.
A more detailed one-phase power circuit is shown in Fig. 3.
The three-phase circuit is made up from three similar circuits
wye connected.
The voltage filter is a full bridge IGBT inverter, S1 to S4,
followed by the low-pass filter - feeding the primary of the
series compensating transformer T1. The current filter is a half
bridge IGBT inverter, S5-S6, with a center-tap dc bus
–
followed by the filter coil . This active current filter can be
optionally complemented with one or several passive LC filters
tuned to low frequency harmonics as 3rd (for 4-wire load), 5th,
7th, 11th.
Normally, the static switch SO is closed and both the non critical load (NCL) and the critical load (CL) are fed by the mains
through the voltage filter. In case of a mains interruption SO
opens isolating CL which is now fed by the current filter inverter
acting as voltage inverter controlled by a reconfigured program.
Capacitor
completes the output filter coil
of this inverter
which feeds CL from the energy remaining in the dc bus capacitors (UPS operation). Rating the dc bus capacitors for the normal
internal voltage filter operation, a 20% of the nominal load can
be feed during 100 ms. As the electrical companies consider
that typically less than 5% of the interruptions last more than
500 ms, the dc capacitor has been overrated five times to ensure
this emergency time to a selected 20% of the nominal load (CL).
This means an affordable extra cost in the overall conditioner.
If bigger emergency and/or selected critical load are needed,
the dc bus can be paralleled with fast batteries and the reference
signal for the control loop 2 (see Fig. 6) must be programmed to
ensure correct charge along normal operation. The prototypes
have not been tested in this condition.
The high switching frequency of the current filter, when
acting as voltage inverter (15,6 kHz), allows a small capacity
for
(whose reactive 50 Hz power is in the range of 1% of
does not disturb the normal operation
the nominal power).
of the conditioner counting on some prevention in the voltage
filter control for its resonance with the line impedance.
As shown in Section III, the topology has been optimized
through an exhaustive search which guaranties to be one of the
most economical possible solutions. The usage coefficients [24]
obtained in the case of non passive LC current filters are:
Usage Coefficients of the main components:
Coils and transformer:
,8
Capacitors:
,03
Semiconductors:
,27
As said before, the main innovation presented here over other
reconfigurable to UPS topologies [16], [24] is the elimination of
the input and output static switches in the main circuit, due to
a new reconfiguration strategy of the power circuit. The input
switch has been eliminated and the output switch is relocated
as SO and derated from the nominal current (plus overload) to
the sum of the active filter current plus non critical load current (typically under 50% of the nominal current). This leads to
a better usage coefficient
for the whole conditioner rising
from 0.12 (calculated in [24] for the circuit described in [16]) to
0.27, as can be easily seen repeating the synthesis calculus for
the new circuit. In as much of a cost reduction, the contribution
means a substantial amelioration in efficiency and, more important, in reliability (as only the overloads in CL affect to SO).
The switch SI is normally off and closes in case of overload to
protect the voltage filter. After approximately 100 ms closes the
mechanical breaker COR removing the current from SI which
can be selected upon a nonrepetitive peak current criteria. Furthermore, the compensating transformer divides by (typically
11) the overload current seen by SI, resulting a relatively very
small thyristor pair (also alternistors are usable). It has not been
considered in the usage coefficient calculation, nor in [24], nor
here.
V. CONTROL
The control circuit has two independent and interactive processors, one for the voltage filter and another for the current
filter. Both operate in their inner loop under a time domain deadbeat technique. In the voltage section control, whose guidelines
have been described in [17], the line voltage and the load current
asymmetrical model showed in Fig. 5. The duty cycle, calculated by deadbeat technique (similar to the one described for
the voltage filter in [18]) is given by
(1)
Fig. 4. Equivalent electric circuit for the current filter showing the variables
operating in the control algorithm.
Fig. 5. Pulse pattern for the current filter switches S5-S6. The commuting
64 s.
frequency is 15.6 kHz. T
=
Fig. 6. Current filter control block diagram. The inner loop operates with a
very fast beat-dead algorithm. The peripheral loops, which elaborate the i
reference signal for inner loop, are hierarchically arranged under a function
preference-speed level criteria.
are the main input signals and the output signal is the duty cycle
for the switches. This signal is applied to a pulse pattern generator which commands the voltage active filter IGBT drivers.
In the current filter (see Fig. 4 for the electric equivalent circuit) the main input signal to the processor is the load current
. The output signal is, again, the duty cycle of the pulse pattern for the IGBT drivers (see Fig. 5). The input voltage seen
by this filter, , is the line voltage corrected by the voltage
filter and can be considered as an ideal sinus. The current active filter generates
, which (neglecting the dc bus charge,
the phase current unbalance reduction, and the possible reactive
current compensation over other areas outside the load) is the
equal-but-opposite of the nonideal component of the load current , thus eliminating it from the current provided by the
mains.
Considering a negligible effect of
over the system dynamics (ideal coil), the pulse pattern can be simplified to the
The target of the inner control loop is to follow as quickly
as possible (7 or 8 pattern periods , in practice) the instantaneous reference value
decided for
by the hierarchical
ensemble of outer control loops. In this operating mode,
is
considered as part of the load.
The outer loops pay attention to the dc bus voltage and to
every load+line current amelioration function prescribed for the
conditioner. Their preference hierarchy is carried out by their
response time, the faster (lower response time) being the first in
preference. The current filter block diagram is shown in Fig. 6.
The first (fastest) loop refreshes the current reference
signal after every sample of the data logger. In absence of other
constraints non related itself with the own phase current, this
reference is elaborated, as announced before, as the difference
between the instantaneous value of the load current
and the
extracted fundamental component. In turn, this ideal value is
elaborated by a filter algorithm who continuously averages the
actual value of along a time period inversely proportional to
the required precision [22]. In this way, the first loop eliminates,
from the line current the nonideal component of the load current.
The second and third loop controls the dc bus voltage
(average value 720 V in practice) and the reactive power generated
by the conditioner. Their time constant is about one line period.
The fourth loop controls the balance of the top and bottom capacitor voltage
and
of
and
in the dc bus. Its time
constant is much higher than the one in the previous loops. The
fifth controls the mains current unbalance.
Another control strategy, for the hybrid current filter option,
has been implemented in the same DSP (ADSP-2101 from
Analog Devices) using sliding mode techniques [23]. It watches
both the cancellation of the high frequency current harmonics
reserved to the active filter and the elimination of the resonance
of the LC arms with the line impedance, thus alleviating the
voltage filter from this task (see Fig. 12).
The control algorithm of the current filter, when acting as a
voltage inverter, is an adapted version of the one used in the
voltage filter. They share the basic control strategy and differ in
the measured and the controlled variables.
VI. PROTOTYPES
The electric and electronic design of six conditioners ranging
from 50 kVA to 1 MVA has been completed. The first test of
the control algorithms has been carried out over an 1-kVA onephase and a 3-kVA three-phase laboratory model. The last one is
a complete copy of the 400-kVA industrial prototype, in which
the coils and transformer quality factors have been replicated.
The line voltage and load current disturbances have been implemented in the 3-kVA model by means of programmable ac
sources. The hybrid current filter option has been tested over a
15-kVA three-phase prototype in which the passive filter (three
Fig. 9. Voltage active filter test. Response to an 18% positive step in the line
voltage: Upper trace, line voltage. Lower trace, output voltage. The recovery
time is in the order of 0.5 ms.
Fig. 7. A 400-kVA prototype under test, front view: Control circuit, top left.
Compensating transformers, middle left. DC bus, bottom. Static switches, right
top. Input-output terminals and protectors, middle right.
Fig. 8. The 400-kVA prototype, rear view: IGBT drivers, top. Paralleled power
IGBT, middle. DC bus, bottom.
LC arms for 5th, 7th, 11th harmonics) ranges 9 kVA and the load
is a six diodes rectifier bridge charged with a 15-kW resistor.
A 400 kVA industrial prototype (Fig. 7) has been constructed
and validated under full load conditions tests, except for some
voltage disturbances. In the prototypes construction have collaborated SAFT Ibérica, UNED and CENIDET (Centro de Investigación y Desarrollo Tecnológico, Cuernavaca). The tests have
been supervised by ASINEL (Asociación para la Investigación
Eléctrica) and IBERDROLA.
Power IGBT in parallel, directly connected to the dc bus, have
been used for the active filters in the 400-kVA prototype.
In order to prevent voltage spikes during commutation, it
has been crucial obtaining a low stray inductance in the dc bus
through the direct connection of the dc capacitors terminals to
three isolated, but close together cooper-plates (see Fig. 8). The
extra dc capacitors needed for obtaining 500 ms of UPS operation over 20% of critical load have been located in an nearby
cabinet. The connecting cables inductance is not important because the capacitors in the main dc bus provide by themselves a
low impedance way for the ripple currents.
Also important for the correct operation of the power
transistor has been the use of drivers provided by drain-source
voltage sensor. One first level protection inhibits the local
driver in case of a too high value of the sensed voltage. Another
second level protection, commanded by a central watching unit,
inhibits every driver (thus stopping the filters operation) and
shorts the primary of T1, leaving the load connected to the grid
trough its short-circuit impedance. In this way, the minimal
disturbance is caused to the load in case of a general failure of
the conditioner.
The active filters inductances construction elected has
been air-core, Litz wire multilayered cylindrical coil. As the
commuting frequency is high (15.6 kHz), other solutions based
on new core materials are liable to be cheaper than that. Each
control circuit has been implemented on an ADSP-2101 from
Analog Device. Certain degree of saturation has been observed
when all the tasks are required. No special coupling problems
have been encountered between power circuit and control
circuit using standard isolation techniques. Special care has
been taken over the decoupling of the power dc supplies by
means of an unique high voltage source feeding several dc-dc
converters distributed into the control blocks.
VII. RESULTS
A. Voltage Active Filter
The time response of the active voltage filter for positive
and negative steps is in the range of 0.5 ms. See Fig. 9. This
means than the proposed power topology, associated to the inner
dead-beat control loop described in [17] with 15.6 kHz commutation frequency, is likely to reduce significantly line voltage
harmonics up to order 11th (whose period is 1,8 ms and frequency is 550 Hz in 50-Hz systems).
The prevention of the resonance between capacitor
and the
line impedance, which can appear in ’weak’ systems (for values
of this impedance typically over 2% of the nominal impedance)
can be achieved by means of an input impedance resistant algorithm for the inner loop, or by filtering the voltage input signal
Fig. 10. Voltage active filter test. Flicker attenuation. Response to a 15%
amplitude modulation at 10 Hz. Up, modulated line voltage. Down, output
voltage in the case of a high impedance line; the modulation is reduced from
21:72) to 3.9% (P st = 8:094). With a low impedance line, the
15% (P st
P st is reduced to 8.6.
=
Fig. 11. Voltage active filter test. Reduction of third harmonic. Top, distorted
line voltage. Bottom, output voltage. Left, harmonic and fundamental in phase,
THD reduction from 15% to 2.66%. Right, harmonic and fundamental opposite,
reduction from 19% to 3.3%.
TABLE II
CURRENT HARMONIC REDUCTION
for the resonance frequency. As this frequency is high (in the
order of 2.5 kHz for a line impedance of 0.04 p.u. and a reactive
power in
of 0.01 p.u.) the overall active filter operation is not
penalized greatly.
In practice, the voltage control has shown acceptable results
in low frequency disturbances as flicker (see Fig. 10) and in
harmonics up to 7th (see Fig. 11 for harmonic 3 reduction) and
needs optimization for 11th and 13th.
B. Active Current Filter
Although the commutation frequency and the control strategy
of the inner control loop used in the current filter are similar to
those used in the voltage filter, the results obtained for the current harmonic reduction are poorer. Table II shows the reduction
of the current harmonics measured in the mains, with respect to
those measured in the load, obtained in the 400-kVA prototype
when charged with a power resistor through a six pulse noncontrolled rectifier.
Fig. 12. Optional hybrid current filter operation damping the resonance of
three LC arms tuned to 5 , 7 and 11 harmonics with the line impedance in a
15 kVA, three phase, 110-V line-neutral prototype [23]. Upper figure: Currents
when resonance damping is off. Upper trace, load current; 2nd trace, passive
filter current; 3rd trace, mains current. (50 A/div.). Lower figure: Idem when
the resonance damping is on. Upper trace, load current; 2nd trace, passive filter
current; 3rd trace, active filter current; 4th trace, mains current. (50 A/div.).
The low degree of inverse proportionality between the harmonic order and the correspondent obtained reduction indicates
than the control algorithm needs supplementary optimization
work. The appreciable reduction in harmonics as high as 17th
and 19th indicates than this optimization must be done preferably in the outer control loops.
C. Hybrid Current Filter
As part of the plan for obtaining a complete power topology
for line conditioners, the test of the hybrid option for the current
filter has been carried out on the mentioned 15-kVA prototype.
The active circuit of the filter is significantly reduced in power as
it is dedicated to reduce the current harmonics 13th and higher,
the fifth, seventh, 11th harmonics being attenuated by the LC
arms. This option has not been taken into account for the usage
coefficients calculations and may be interesting if an important
part of the nonideal load current comes from stable and low
frequency harmonics.
It has been also proved [23] than the damping of the resonance between the passive LC arms and the line impedance
Fig. 13. Operation as uninterruptible power supply (UPS). Upper trace, line
voltage showing a 500-ms interruption. Lower trace, voltage in the critical load
output.
can be trusted on the active current filter. In this way, the universal conditioner showed integrates as well the advantages of
this damping solution [17] over other solutions that relay on an
additional voltage active filter [6], [12]. In Fig. 12 are shown the
results of the hybrid current filter for both tasks: the load current
harmonic reduction and the damping of the resonance. Another
role not investigated for this current filter control version is to
extend the damping effect up to the resonance frequency among
the line impedance and capacitor , thus releasing the voltage
filter control from this task.
D. UPS Operation
As shown in Fig. 13, the transfer of the critical load from
mains to the current filter, acting as a voltage inverter, happens
with no significant dead time. The key is to turn-off the thyristor
switch SO in a fast mode. This has been done, without auxiliary
forced commuting switches, by means of an adequate sequence
in the SO driving pulses, coordinated with the pulses (as voltage
inverter) of the active filter during the first 50-Hz period. The
procedure has shown to be sensitive to the accuracy in the detection of the line phase.
VIII. CONCLUSION
A very complete universal line conditioner showing a high
effectiveness/cost ratio has been developed guided by an iterative analysis+synthesis cost comparative method which allows
to know the effective power and cost of the components needed
for every topology investigated. The conditioner is composed
by one fast active voltage filter and one fast active current filter
(both made with IGBT modulated at 15.6 kHz). The active
power filter can be paralleled with classic resonant LC filters
for low frequency current harmonics. The active voltage filter
reduces slow line deviation (as flicker and voltage unbalance)
and fast deviations (up to harmonic 19th). The active current
filter reduces current harmonics up to order 19th and can
compensate power factor and current unbalance. In case of a
line sustained interruption, the current filter reconfigures to
uninterruptible power supply, feeding 20% of the nominal load
during 500 ms from the energy stored in the dc bus capacitor
(overrated five times for this purpose).
Main improvements over previous solutions [7], [8], [10],
[15] are the elimination of the input and output series static
switches which accomplish the reconfiguration to UPS, and the
possibility of hybridizing the active current filter with LC resonant arms. In this case, the control circuit of the active current
filter can eliminate the resonance of the LC arms with the line
impedance with no help from the voltage filter [23]. The last
improvement means also a sound simplification for the hybrid
(LC arms plus active) current filters applied on its own.
The tests confirm the universality of this cost effective power
topology, but also indicates that the control circuit needs new
investigation in order to improve the results on high frequency
voltage and current harmonic reduction and in the resonance
damping. This could be facilitated by lowering the sampling
time (64 s) by the use of a faster DSP.
REFERENCES
[1] L. Gyugyi and E. C. Strycula, “Active power filters,” in Proc. IEEE/IAS
Annu. Meeting, 1976, p. 529.
[2] N. Mohan and H. A. Peterson, “Active filters for AC harmonic suppression,” in Proc. IEEE/Power Eng. Soc. Winter Meeting, 1977.
[3] J. Uceda, P. Martínez, and F. Aldana, “Active filters for static power
convertors,” Proc. Inst. Elect. Eng. B, vol. 130, pp. 347–354, Sept. 1983.
[4] F. Z. Peng, H. Akagi, and A. Nabae, “A new approach to harmonics compensation in power systems,” in Proc. 1998 IEEE-IAS Annu. Meeting,
Oct. 1988, pp. 874–880.
[5] W. M. Grady, M. J. Samotyj, and A. H. Noyola, “Survey of active power
line conditioning methodologies,” IEEE Trans. Power Delivery, vol. 5,
pp. 1536–1542, July 1990.
[6] T. Tanaka and H. Akagi, “A new combined system of series active and
shunt passive filter aiming at harmonic compensation for large capacity
thyristor converters,” in Proc. IEEE IECON, 1991.
[7] L. Gyugyi, “A unified power flow control concept for flexible AC transmission systems,” Proc. Inst. Elect. Eng. C, vol. 139, pp. 323–331, July
1992.
[8] L. Azpiazu, P. M. Martínez, S. Martínez, V. Feliu, and F. Yeves, “Voltage
and current conditioner for distribution networks reconfigurable to
UPS,” in Proc. CIRED Int. Conf., Birmingham, AL, 1993, pp. 17–21.
[9] S. Martínez, V. Feliu, F. Yeves, J. L. Iribarren, and P. M. Martínez,
“Acondicionador de Línea Para Reducción o Eliminación de Perturbaciones,” (in Spanish), P-9 300 932/1, 03,05-1993/3, 1993.
[10] C. H. Chen and D. M. Divan, “Simple topologies for single phase AC
line conditioning,” IEEE Trans. Ind. Applicat., vol. 30, pp. 406–412,
Mar. 1994.
[11] S. Martínez, V. Feliu, F. Yeves, J. L. Iribarren, and P. M. Martínez, “Dispositif de Condicionnement de Ligne Pour Reduire ou Eliminer les Perturbations,” (in French), European Patent 94 069631, 05, 1994.
[12] H. Akagi, “Trends in active power line conditioners,” IEEE Trans. Power
Electron., vol. 9, pp. 263–268, May 1994.
[13] M. B. Brennen and B. Banerjee, “Low cost, high performance active
power line conditioners,” in Proc. PQA, 3rd Int. Conf. Power Qual.: End
Use, Applicat. Perspectives, Amsterdam, The Netherlands, Oct. 1994.
[14] C. Pumar, F. Mur, F. Yeves, and V. Feliu, “Interactive voltage and current
high frequency line conditioner,” in Proc. PQA, 3rd Int. Conf. Power
Quality: End Use, Applicat. Perspectives, Amsterdam, The Netherlands,
Oct. 1994, pp. 24–27.
[15] L. Gyugyi, C. D. Schauder, S. L. Williams, and T. R. L. Rietman, “The
unified power controller: A new approach to power transmission control,” IEEE Trans. Power Delivery, vol. 10, pp. 1085–1093, Apr. 1995.
[16] F. Yeves, J. Carpio, S. Martínez, V. Feliu, and C. Pumar, “Iteractive
voltage and current high frequency line conditioner,” EPE J., vol. 5, pp.
38–43, Jan. 1996.
[17] H. Akagi, “New trends in active filters for power conditioning,” IEEE
Trans. Ind. Applicat., vol. 32, pp. 1312–1322, May 1996.
[18] V. Feliu, F. Mur, I. de la Nuez, and S. Martínez, “Pulse width modulation based control system for voltage conditioning of distribution networks,” in Proc. IFAC World Congress, San Francisco, CA, June-July
30–5, 1996.
[19] J. Häfner, M. Aredes, and K. Heumann, “A shunt active power filter
applied to high voltage distribution lines,” IEEE Trans. Power Delivery,
vol. 12, pp. 266–272, Jan. 1997.
[20] S. Bhattacharya, P.-T. Cheng, and D. M. Divan, “Hybrid solutions for
improving passive filter performance in high power applications,” IEEE
Trans. Ind. Applicat., vol. 33, pp. 732–747, May 1997.
290
[21] M. Aredes, K. Heumann, and E. H. Watanabe, “An universal active
power line conditioner,” IEEE Trans. Power Delivery, vol. 13, pp.
545–551, Apr. 1998.
[22] F. Mur, V. Cárdenas, J. Vaquero, and S. Martínez, “Phase siynchronization and measurement digital systems of AC mains for power converters,” in Proc. IEEE Int. Power Electron. Conf. (CIEP’98), Oct. 1998,
pp. 188–194.
[23] V. M. Cárdenas, “Filtros activos híbridos para compensación armónica
de corriente y corrección de factor de potencia en sistemas trifásicos,”
Ph.D. dissertation, CENIDET, Cuernavaca, México, 1999.
[24] F. Barrero, S. Martínez, F. Yeves, and P. M. Martínez, “Active power
filters for line conditioning: A critical evaluation,” IEEE Trans. Power
Delivery, vol. 15, pp. 319–325, Jan. 2000.
[25] H. Fujita, T. Yamasaki, and H. Akagi, “A hybrid active filter for camping
of harmonic resonance in industrial power systems,” IEEE Trans. Power
Electron., vol. 15, pp. 215–222, Mar. 2000.
[26] M. El Shatshat, M. Kazerani, and M. M. A. Salama, “Multi converter approach to active power filtering using current source converters,” IEEE
Trans. Power Delivery, vol. 16, pp. 38–45, Jan. 2001.
[27] S. M.-R. Rafiei, H. A. Toliyat, R. Ghazi, and T. Gopalarathnam, “An optimal and flexible control strategy for active filtering and power factor
correction under nonsinusoidal line voltages,” IEEE Trans. Power Delivery, vol. 16, pp. 297–305, Apr. 2001.
Fermín Barrero (M’95) received the M.Sc. degree in
electrical engineering from the Universidad Politécnica de Madrid, Madrid, Spain, in 1984 and the Ph. D.
degree from the Universidad Nacional de Educación
a Distancia, Spain, in 1995.
He is a Full Professor in electrical engineering at
the Universidad de Extremadura, Spain. His research
interests are power electronics in the power system,
FACTS, active power filters, and electrical machine
drives.
Dr. Barrero is a member of the IEEE IAS Industrial
Static Converters Committee, European Working Group.
Salvador Martínez (SM’90) received the M.Sc. and
Ph. D. degrees in electrical engineering from Universidad Politécnica de Madrid, Madrid, Spain, in 1966
and 1969, respectively.
He was an Associate Professor at the Universidad
Politécnica de Madrid, from 1975 to 1979, and at
the Universidad Nacional de Educación a Distancia,
Madrid, from 1979 to 1982, where he has been a
Full Professor since 1982. He spent eight years as
a Design Engineer on power electronics equipment
in several companies. His research interests are
integrated magnetics, transformer calculation programs, and power line
conditioners.
Dr. Martínez is a member of the IEEE IAS Industrial Static Converter Committee, European Working Group.
Fernando Yeves (M’90) received the M.Sc and Ph.D.
degrees in electrical engineering from Universidad
Politécnica de Madrid, Madrid, Spain, in 1981 and
1987, respectively.
He was an Associate Professor at the Universidad
Politécnica de Madrid, from 1985 to 1990, and a Full
Professor at the Universidad Nacional de Educación a
Distancia, Madrid, since 1990. His research interests
are power electronics equipment for solar energy systems and the electrical grid, both in power topology
and control circuits supported by DSPs.
converters.
Francisco Mur received the M.Sc degree in electrical engineering from the Universidad Politécnica
de Madrid, Madrid, Spain, in 1992 and the Ph.D. degree in electrical engineering from the Universidad
Nacional de Educación a Distancia, Madrid, in 1998.
He has been a Full Professor at the Universidad
Nacional de Educación a Distancia, Madrid, since
1998. Since 1993, he has participated in several
activities on power conditioning. His research interests are power circuits, control circuits supported
by DSPs and control programs for power static
Pedro Mª Martínez received the M.Sc. degree in
electrical engineering from the Universidad Nacional
de Educación a Distancia, Madrid, Spain, in 1989.
Since 1995, he has been a Tutorial Professor in the
Bilbao Center. Universidad Nacional de Educación
a Distancia, Madrid. He joined the Electric Power
Corporation IBERDROLA S.A., in 1979, where
he has been leader of several research projects on
FACTS. His current status is Technological Development Manager of the Electrical Lines Division.
He participates in several international committees
promoting FACTS development.