Mixed signal SoC:
A new technology driver in LSI industry
Akira Matsuzawa
Matsushita Electric Industrial Co., Ltd
(Tokyo Institute of Technology, after this April)
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Contents
•
•
•
•
Introduction
Current electronics and mixed signal technology
CMOS as an analog device
Development strategy and design system for
mixed signal SoC
• Issues of mixed signal SoC and solutions
• Summary
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Current electronics and
mixed signal technology
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Image of current electronics
Digital consumer electronics and networking drive current electronics.
IEEE 1394, USB, Blue tooth, Wireless LAN
DAB
CS/BS
Ethenet
Digital TV
ITS
HII Station
Home network
ADSL, FTTH
Network
Digital TV
W-CDMA
Home
Server
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DVD
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Mixed signal technology :Digital networkingｓ
Mixed signal technology enables high speed digital networking.
Data conversion
Equalization
Encryption
Data and clock recovery
Noise cancellation
Error correction
Digital
Analog
DAC
DAC
DAC
DAC
Line
I/F
TX3
TX4
6b, 125MHz ADC, DAC
ADC
ADC
ADC
ADC
250Mbaud
(PAM-5)
Pulse Shaping
Slicer
FFE
DFE
Clock
Recovery
TX1
TX2
Side-stream
Scramber
&
Trellis,Viterbi
Symbol
Encoder
Side-stream
Descramber
&
Trellis,
Viterbi
decoder
Echo Canceller
Analog circuit
3-NEXTCanceller
Digital circuit
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Mixed signal tech. ;Digital read channel
Digital storage also needs high speed mixed signal technologies.
Variable
Variable
Gain
GainAmp.
Amp.
Analog
Analog
Filter
Filter
AAto
toDD
Converter
Converter
Voltage
Voltage
Controlled
Controlled
Oscillator
Oscillator
Data In
Pickup signal
(Erroneous)
Digital
Digital
FIR
FIRFilter
Filter
Viterbi
Viterbi
Error
Error
Correction
Correction Data
Out
Clock
Clock
Recovery
Recovery
Analog circuit
Data Out
Digital circuit
Processed
(No error) Signal
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Mixed signal SoC for DVD RAM system
This enables high readability for weak signal from DVD RAM pickup.
World fastest and highly integrated mixed signal CMOS SoC
0.18um- eDRAM
Analog
for servo
24M Tr
16Mb DRAM
Digital
Read channel
500MHz
Mixed Signal
16Mb DRAM
Goto, et al., ISSCC 2001
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Recent developed mixed signal CMOS LSIs
5G RF LAN
12b 50MHz ADC 2ch
12b 50MHz DAC 2ch
AFE for ADLS
AFE (Analog Front End)
Digital network
1394b (1GHz)
AFE for Digital Camera
12b 20MHz ADC+AGC
12b 20MHz
ADC+DAC
2GHz RF CMOS
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Application area in mixed signal CMOS tech.
Almost all the products need mixed signal CMOS LSI tech.
・Cellular phone: PDC, W-CDMA
Wireless
・RR-Net: Bluetooth, IEEE802.11
・Broad cast: STB, DTV, DAB
Network
Network
Communication
Communication
・Optical:FTTH, OC-xx
・Metal: ADSL, VDSL, Power line modem
Wired
・Serial: IEEE1394, USB, Ethernet
・Parallel: DVI, LVDS
Recording
Recording
・DVD, VDC, HDD
Output
Output
Input
Input
Power
Powersupply
supply
・LCD, PDP, EL, Audio drive
・Camera, Others
・ Switching supply, Every LSIs (On-chip)
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Digital technology in real world
Digital signal suffers heavy damage in real world.
But, digital can address this issue by own advantages,
but needs the help of analog tech.
Pure digital
Advantages of Digital Tech.
•
•
•
•
•
High robustness
Programmability
Time shift (memory)
Error correction
High Scalability
Media
(Cable, Disc, Air, etc)
Noise
Distortion
Interference
Limited bandwidth
Real world
Damaged
digital
Mixed
Mixedsignal
signaltechnology
technology Reconstruction
(Analog+Digital)
(Analog+Digital)
Not only digital, but also analog;
ADC, DAC, Filter, and PLL are needed
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Recovered digital
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Progress in A/D converter; video-rate 10b ADC
ADC is a key for mixed signal technology.
We have reduced the cost and power of ADC drastically;
1/ 2,000 for Power and 1/200,000 for the cost!
dulling past 20 years
CMOS technology attained it.
1980
1982
1993
Now
Conventional product World 1st Monolithic World lowest power SoC Core
Board Level (Disc.+Bip)
20W
$ 8,000
Analog Devices Inc.
Bipolar (3um)
2W
$ 800
Our developed.
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CMOS (1.2um) CMOS (0.15um)
10mW
30mW
$0.04
$ 2.00
Our developed.
Our developed.
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Progress in high-speed ADC
High speed ADC has reduced its power and area down to be embedded.
World fastest 6b ADC
6b, 1GHz ADC
2W,
1.5um Bipolar
ISSCC 1991
6b, 800MHz ADC
400mW, 2mm2
0.25umCMOS
Pd/2N[mW]
ISSCC 2000 World fastest CMOS ADC
10
1
Reported Pd of CMOS ADCs
ps
s
G
W/
m
10
s
sp
G
W/
m
1
ISSCC 2002 World lowest Pd HS ADC
7b, 400MHz ADC
50mW, 0.3mm2
0.18umCMOS
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1 order down
This Work
0.1
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Conversion rate [x100Msps]
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Early stage mixed signal CMOS LSI for CE
Success of CMOS ADC and DAC enabled low cost mixed signal CMOS LSI.
This also enabled low cost and low power digital portable AV products.
1993 Model: Portable VCR with digital image stabilizing
6b Video ADC
Digital Video filter
System block diagram
8b low speed ADC;DAC
8b CPU
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CMOS as analog device
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CMOS as analog device
CMOS has many issues as analog device,
but also has a variety of circuit techniques
CMOS
Bipolar
Comment
Switch action
++
--
Low Input current
++
--
Only CMOS can realize
switched capacitor circuits
High gm
-
+
CMOS is ¼ of Bip.
Low Capacitance
+
-
This results in Cp issue
fT
+
+
Almost same
Voltage mismatch
--
++
CMOS is 10x of Bip.
1/f noise
--
++
CMOS is 10x to 100x of Bip.
Low Sub. effect
-
+
Offset cancel
++
--
Analog calibration
++
--
Digital calibration
++
--
Embed in CMOS
++
--
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CMOS has a variety of
techniques
to address the self issues
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GHz operation by CMOS
Cutoff frequency of MOS becomes higher than that of Bipolar.
Over several GHz operations have attained in CMOS technology
0.13um
100G
0.18um
Frequency (Hz)
20G
fT : Bipolar (w/o SiGe)
0.25um
50G
fT : CMOS
fT /10 (CMOS )
0.35um
RF circuits
10G
5G
Cellular
Phone
CDMA
fT /60 (CMOS )
5GHz W-LAN
gm
fT ≡
2πCin
vsat
fTpeak ≈
2πLeff
Digital circuits
2G
1G
IEEE 1394
D R/C for HDD
500M
200M
100M
1995
2005
2000
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CMOS technology for over GHz networking
Digital consumer needs over GHz wire line networking.
CMOS has attained 5Gbps data transfer.
DVC
IEEE1394
STB
DVI
HD-DVD
FPD
World first 1394b transceiver
For 1Gbps networking
Test chip for 5Gbps wire line
0.25um 3AL_CMOS
0.18um 4AL_CMOS
200ps
5Gbps Eye pattern
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fT: MOS vs. Bipolar
Even if fT of MOS is same as that of Bipolar,
fT of MOS is easily lowered by parasitic capacitance.
Because, gm of MOS is ½ to ¼ of that of Bipolar at the same current.
MOS
gm
fT ≡
2πCin
Ids
gm ≡
⎛ Veff ⎞
⎜
⎟
⎝ 2 ⎠
Veff min = 2nU T
Veff/2: 50-100mV
(actual ckt.)
Bipolar
Ic
gm ≡
UT
UT ≡
n: 1.4
gmCMOS <
CinCMOS
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, gmBip
2 4
1 1
< , CinBip
2 4
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kT
≈ 26mV
q
（Same operating current）
（Same fT）
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Parasitic effect: CMOS CT filter
High frequency ckt. with scaled device is strongly affected from parasitic.
Circuit optimization with layout and parasitic effect is needed.
SIM w/o parasitic C
SIM with parasitic C
NO LPE
2.5E+00
3.5E+00
3.5E+00
NG
3.0E+00
2.5E+00
Group Delay
OK
Group Delay
Group Delay
LPE OPTIMIZED
LPE
3.5E+00
3.0E+00
Optimized with parasitic C
OK
3.0E+00
2.5E+00
2.0E+00
2.0E+00
2.0E+00
1.5E+00
1.00E+07 1.00E+08 1.00E+09
1.5E+00
1.00E+07 1.00E+08 1.00E+09
1.5E+00
1.00E+07 1.00E+08 1.00E+09
Freq.
Freq.
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Freq.
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Transistor issue: VT mismatch
Larger gate area is needed for small VT mismatch.
Scaling and proper channel structure can improve this.
ΔVT (σ:mV)
15
Tox
ΔVT ∝
LW
0.4um Nch
Larger gate area
0.13um Nch Boron w. Halo*
Tox scaling
10
0.4um Pch
Channel engineering
0.13um Nch In w/o Halo*
5
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
1
( μm −1 )
LW
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* Morifuji, et al., IEDM 2000.
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Development strategy and design system
for mixed signal SoC
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Full DVD system integration in 0.13um tech.
Advanced mixed signal SoC has been successfully developed.
Okamoto, et al., ISSCC 2003
0.13um, Cu 6Layer, 24MTr
CPU2
CPU１
System
Controller
Pixel
Operation
Processor
Front-End
Analog FE
+Digital R/C
VCO
ADC
PRML
Read
Channel
AV
Decode
Processor
IO
Processor
Servo DSP
Gm-C
Filter
Back
Back -End
-End
Analog
Analog
Front
Front End
End
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System: DVD player
Current electrical system is complicated and needs analog and memory.
Optical Disc Optical
Head
Memory
32bit MCU
DRAM Embedded
Red Laser
Driver
Head
Amp
16M
SDRAM
PhotoPhoto-receptive
Compound
4M
Red Laser Unit DRAM
ODC
High-speed
Analog-Digital
Read
Channel
Analog
Front End
Copy
Protection
Servo DSP
MPEG
Algorithm
Video Output
AC-3 Output
AC-3 Audio
CD
DEM
System Controller
MCU
Servo
DSP
MPEG 2
Video
Demodulation
ECC
Pre Amp
Analog
AV Decoder
Media Core
Processor
Stereo Output
Console
Panel
System Controller MCU
：First-Gen.
：Third-Gen.
：Second-Gen.
：Fourth-Gen.
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Scaled CMOS technology
Current Scaled CMOS technology is very artistic.
Matsushita’s 0.13um CMOS technology
Gate
SiO2
Seven lattices
Si
100nm
Transistor
Cu Interconnection
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Development strategy and system
Product time slot is narrow and development cost is huge.
Conventional analog LSI needs 2 or 3 re-designs.
This can not be accepted to mixed signal SoC
Advanced development strategy and design system must be established.
12 Mon
12 Mon
12 Mon
6 Mon 6 Mon 3 Mon
Sales (A.U)
Combo
8x
DVD ROM
16x
DVD
ROM
12x
DVD ROM
6x DVD ROM
First
DVD ROM
‘97
2.6G
RAM
‘00
Time
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Combo
2nd G
2.6G
RAM
4.7G
RAM
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Strategy for the mixed signal SoC
•
System design
– Digital calibration for analog adjustment and unknown parameters.
– System optimization to reduce analog area and increase robustness.
•
System verification
– Fast and accurate mixed signal system simulator with behavioral model to
verify and optimize the mixed signal system.
– Create the target performance for circuit blocks.
•
Circuit design
– Ultra fast and accurate circuit simulation for P.V.T and fluctuation analysis
to verify the performance and robustness.
– Circuit optimizer to find the sweet spot of the circuit.
– Automated creation of analog behavioral model for system sim.
•
Process and device development
– Develop suitable analog option device
– Early analog parameter extraction ( mismatch, temp. and voltage chara.)
– Monitor and control the analog parameters in Fab.
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Design flow for mixed signal SoC
Design flow from System to layout with top down and bottom up process
should be used for designing mixed signal SoC.
Accurate and a variety of device parameters is an another key.
Unified design flow controller
Device parameters
(SPICE, Noise, Mismatch)
System design
(Mixed signal level)
Transistors Top down flow
Required SPEC
Passives
Substrate
Circuit design
(SPICE +Behavioral)
Package
Bottom up flow
Actual
Circuit model
Optimizer
Cable
Parasitic effect
Layout design
(Semi/Full automated)
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Multi-language simulation
Multi-language simulation is 56x faster than SPICE with same accuracy.
This will contribute to shorter design TAT and higher design quality.
SPICE+Verilog D+Verilog A
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Mixed signal system design
Needs mixed signal Simulation for total signal processing.
Many parameters and processing methods should be optimized.
Finally, system is checked by real disc signals.
Real disc signal
Encoder/Decoder Methods
PRECODER
M-RANDOM
ENCODER
Analog
Digital
Resolution
ＢＥＲ
Processing Method
# of Taps
Filter
NOISE
ADC
Boost level
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EQUALIZER
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VITERBI
DETECTOR
DECODER
# of Path
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System simulation
Perfection of the mixed signal system should be verified
and optimized by system simulation.
ADC resolution effect
EPR4ML BER vs SNR (AD ENOB)
1.0E+00
RLL (2, 10) recorded data
1.0E-01
4b
1.0E-02
BER
BER
PR(3,4,4,3) waveform
4bit
5bit
6bit
7bit
1.0E-03
5b
1.0E-04
Viterbi decoded result
1.0E-05
6b
7b
1.0E-06
18
19
20
21
22
23
24
25
26
SNR (dB)
SNR
System verification
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LSI design using behavioral language
Example: Analog Front End chip for ADSL system.
LNA
Output driver
Buffer
Buffer
Filter
Filter
D/A
A/D
VCXO cont.
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Control logic
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Hierarchical and behavioral system design
System should be described in behavioral language, hierarchically.
Analog: Verilog-A
Logic: Verilog-D
Analog behavioral model
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Virtual System test using Verilog AMS and Matlab
We can test the designed mixed signal system virtually,
by using Verilog AMS and Matlab.
Matlab
Matlab
DMT modulation
DMT demodulation
Target LSI
Conste
llation
ENC
IFFT
FIR
FIR
FFT
Verilog-AMS
Conste
llation
DEC
Matlab is used as a soft DSP
> 66dB
Q
I
f
MTPR TEST (DMT Carrier hole)
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QAM constellation
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Fitting between behavioral and Spice
The combination of Verilog AMS and SPICE assures system perfection.
Function check
In Verilog-AMS
Verilog-A
Verilog-A Sim
Specification
Circuit design
(SPICE+Verilog AMS)
SPICE
Fitting check
Behavioral model
extraction
If needed
SPICE sim
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Unified mixed signal circuit simulator
New design system can increase design speed, 10x to 50x.
System level Specification
Optimization
Simulation
Results
Design flow
controller
Documentation
Test bench
PVT analysis
Spec sheet
Behavioral model
Optimization
Simulation flow
Verilog-AMS
+SPICE
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Controller for automated simulation
Simulation controller enables fast and automated simulation steps
Project name
Test bench (20 types)
Parameter seep
Spec sheet
-PLL simulation results
-Behavioral modeling
Behavioral model calibration
Behavioral model generation
Optimization
Design procedure
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Issues of mixed signal SoC
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Vdd and CMOS scaling limits in analog
Lowest analog operating voltage must be 1.2V -1.8V.
Thus 0.18um – 0.13um must be a scaling limit for analog.
This results in salutation of fT and area reduction.
Technology node (0.1um)
Supply voltage (V)
4
ITRS ‘99
Digital
（Upper）Technology
node
テクノロジーノード
デジタル（上限）
Analog
アナログ（上限）
(Upper)
3
Analog
アナログ（下限）
(Lower)
2
1
Digital
(Lower)
デジタル（下限）
0
1
2
‘00
3
4
5
6
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10
11
12
‘10
13
14
15
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Optimization in channel parameters
Larger gate length is needed for small mismatch and small noise circuit.
However, this results in increase of cost and decrease of performance.
Log (Magnitude)
Internal capacitance
Transistor area
Output resistance
DC Gain
Frequency characteristics
1/f noise
VT mismatch
Small
Log L
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Cost up issue by analog & I/O
Cost of mixed A/D LSI will increase when using deep sub-micron
device, due to the increase of cost of non-scalable analog and I/O
parts.
Large analog on SoC must be unacceptable in near future.
Wafer cost increases 1.3x
for one generation
I/O
Analog
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
（0.35um : 1）
Digital
0.35um
0.25um
0.18um
0.13um
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.35um
Chip area
0.25um
0.18um
0.13um
Chip cost
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Solution 1: Scaled CMOS and use of digital
Use scaled CMOS and not accurate passives.
Address the issues by M/S compensation and system optimization.
0.35um Tr
0.18um_0.13um Tr
Accurate passive Not accurate passive
(If low Vdd is acceptable)
0.35um
0.35um
0.13um
0.13um
Pros
· ·Small
Smallarea
area(low
(lowcost)
cost)
· ·High
Highspeed
speed
· ·Low
Lowpower
power
Cons
Scaled CMOS
· ·Low
Lowaccuracy
accuracy
· ·Sensitive
Sensitiveto
toProcess
Process
· ·Large
Large1/f
1/fnoise
noise
Solution
··Analog
Analogcompensation
compensation
··Digital
Digitalcalibration
calibration
··System
Systemoptimization
optimization
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Example: Analog+ digital calibration tech.
Area and power are reduced drastically, by scaled CMOS and digital tech.
Y. Cong and R. L. Geiger, Iowa state university,
ISSCC 2003
14b 100MS/s DAC
1.5V, 17mW, 0.1mm2, 0.13um
0.5 LSB INL,
SFDR=82dB at 0.9MHz, 62dB at 42.5MHz
+/- 9 LSB
+/- 0.4 LSB
Area: 1/50
Pd: 1/20
Calibration
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Solution 2: Advanced packaging technology
Some advanced packaging technologies will give the solution.
Analog: using not so much scaled technology.
Digital: using scaled technology
Connect with low parasitic cap. and inductance.
LSI B
(MPU)
Digital
LSI A
(DRAM)
Analog
area pads
+
LSI chip A
Chip On Chip technology
LSI chip B
Same capacitance
as on-chip interconnection.
No interconnection inductance
bumps
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Future step: Mixed signal egg.
Analog helps digital (digital network and storage…).
Next step is digital must help analog.
Mixed signal egg ( Analog yolk and white with digital shell)
Digital shell
Sustain the analog egg.
Calibration and adjustment.
Analog yolk and white
Ultra-low power signal processing (Weak inversion)
Ultra-high speed signal processing
But, very delicate and fancy
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Summary
• The mixed signal (Analog+Digital) is essential for almost
all the systems. Not analog only, not digital only.
• Effective modeling of analog parts and high speed
concurrent simulation with digital is vital for design.
• CMOS is very powerful technology for analog, as well as
digital, but scaling limitation is reaching.
• The collaboration between analog and digital, and
advanced packaging technology will bring us effective
solutions.
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