Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
PICMG® AMC.1 R2.0 - PCI Express® on
AdvancedMC™
Revision 2.0
A subsidiary specification to the
Advanced Mezzanine Card Base Specification
October 8, 2008
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
Revision History
Revision Level
Date
Action
R2.0
Oct 8, 2008
Generate released spec after Exec review
R2.0 RC1.0
Aug 21, 2008
Generate Release Candidate after Member review
R2.0D1.95
Aug 14, 2008
Incorporate comments from member review/CR cycle
#8
R2.0D1.94
Aug 5, 2008
Incorporate comments from member review/CR cycle
#7
R2.0D1.93
Aug 1, 2008
Incorporate comments from member review/CR cycle
#6
R2.0D1.92
June 9, 2008
Incorporate comments from review/CR cycle #5
R2.0D1.91
June 2, 2008
Incorporate comments from review/CR cycle #4
R2.0D1.90
May 12, 2008
Edits and PDF generation.
R2.0D1.85
April 14, 2008
Incorporate comments from review/CR cycle #3,
interim for cycle #3, clock CR effort
R2.0D1.08
February 28, 2008
Incorporate comments from review/CR cycle #2
R2.0D1.07
January 2, 2008
Incorporate comments from review
R2.0D1.06
December 4, 2007
Revision 2.0 draft 1.06 with ECN changes
R1.0
January 20, 2005
Revision 1.0 with copyright update
© Copyright 2008, PCI Industrial Computer Manufacturers Group
The attention of adopters is directed to the possibility that compliance with or adoption of PICMG® specifications may require use of an invention
covered by patent rights. PICMG® shall not be responsible for identifying patents for which a license may be required by any PICMG® specification or
for conducting legal inquiries into the legal validity or scope of those patents that are brought to its attention. PICMG® specifications are prospective
and advisory only. Prospective users are responsible for protecting themselves against liability for infringement of patents.
NOTICE:
The information contained in this document is subject to change without notice. The material in this document details a PICMG® specification in
accordance with the license and notices set forth on this page. This document does not represent a commitment to implement any portion of this
specification in any company's products.
WHILE THE INFORMATION IN THIS PUBLICATION IS BELIEVED TO BE ACCURATE, PICMG® MAKES NO WARRANTY OFANY KIND,
EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, ANY WARRANTY OF TITLE OR
OWNERSHIP, IMPLIED WARRANTY OF MERCHANTABILITY OR WARRANTY OF FITNESS FOR PARTICULAR PURPOSE OR USE.
In no event shall PICMG® be liable for errors contained herein or for indirect, incidental, special, consequential, reliance or cover damages, including
loss of profits, revenue, data or use, incurred by any user or any third party. Compliance with this specification does not absolve manufacturers of
equipment from the requirements of safety and regulatory agencies (UL, CSA, FCC, IEC, etc.).
PICMG®, CompactPCI®, AdvancedTCA®, AdvancedTCA® 300,ATCA®, ATCA® 300, CompactPCI® Express and the PICMG, CompactPCI,
AdvancedTCA and ATCA logos are registered trademarks, and COM Express™, MicroTCA™, µTCA™, CompactTCA™, AdvancedMC™ and SHB
Express™ are trademarks of the PCI Industrial Computer Manufacturers Group. All other brand or product names may be trademarks or registered
trademarks of their respective holders.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
ii
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
Table of Contents
1 Introduction ......................................................................................................... 1-1
1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2.1 Reference specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2.2 Environment and regulatory documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3 Special word usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.4 Name and logo usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.5 Signal naming conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.6 Intellectual property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.6.1 Necessary claims . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.6.2 Unnecessary claims . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.6.3 Third party disclosures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.7 Acronyms and definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
2 PICMG® AMC.1 Compliance .............................................................................. 2-1
3 AMC.0 ................................................................................................................... 3-1
3.1 AMC.0 Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 AMC.0 Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.3 Port Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
4 Link Specification ................................................................................................ 4-1
4.1 Electrical and Link Layer Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2 Dual-Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.3 Ports and Link Widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.4 AMC.0 Basic and Extended Connector Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.5 Reference Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.6 Additional Common Link-Level Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.6.1 Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.6.2 Presence Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
5 PCI Express ......................................................................................................... 5-1
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2 PCI Express Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3 PCI Express Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.3.1 Primary and Secondary PCI Express Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.3.2 Multiple Hosts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.4 Type P Control Path Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
6 Advanced Switching ........................................................................................... 6-1
7 Signal Integrity .................................................................................................... 7-1
7.1 PCI Express at 2.5 GT/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1.1 Minimum Receiver Requirements at 2.5 GT/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1.2 AMC.1 Signal Interconnection Requirements for 2.5 GT/s . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
iii
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
7.2 PCI Express at 5 GT/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-2
7.2.1 Minimum Receiver Requirements at 5 GT/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.2.2 AMC.1 Signal Interconnection Requirements at 5 GT/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
8 Management and E-Keying .................................................................................8-1
8.1 AMC Fabric E-Keying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1
8.1.1 AMC Point-to-Point Connectivity Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.1.1 Record Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.1.2 AMC Channel Descriptor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.1.3 AMC Channel Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.1.1.4 AMC Link Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.1.1.4.1AMC Link Designator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.1.1.4.2AMC Link Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.1.1.4.3AMC Link Type Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.1.1.4.4Asymmetric Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8.1.1.4.5Link Grouping ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
8.1.1.4.6Summary of AMC.1 Link Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
8.1.2 Carrier Point-to-Point Connectivity Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
8.2 AMC Clock E-Keying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-13
8.2.1 AMC Direct Clock Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
8.2.2 FCLK Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
8.3 PCI Express Interface Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-14
8.3.1 Primary PCI Express interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
8.3.2 Secondary PCI Express Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
A AMC.0 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
B Carrier Topologies (Informative). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.1
B.2
B.3
B.4
Basic PCI-E I/O Carrier, or With RC on the Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-1
PCI-E Carrier Which Supports an RC on a Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-2
PCI-E Carrier Which Supports Primary and Secondary RC With NTB and Failover Support . . .B-2
Carrier populated with NTB-isolated RC Modules creating a compute farm . . . . . . . . . . . . . . . .B-4
C Signal Integrity Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
C.1 Signal Integrity Analysis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-1
C.1.1 Modeling Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-1
C.1.2 Module Stackup and Via Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-2
C.1.3 Carrier Stackup and Via Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-3
C.1.4 Backplane Stackup and Via Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-4
C.2 Signal Integrity Analysis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-5
C.2.1 Module to Backplane to Module Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-5
C.2.2 Module to Carrier to Module Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-6
C.2.3 Module to Carrier Serial Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-7
C.2.4 2.5GT/s Representative Eye Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-8
C.2.5 5GT/s Insertion Loss, Return Loss and Impulse Response . . . . . . . . . . . . . . . . . . . . . . . . .C-16
D Requirements Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
iv
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
List of Figures
Figure 5-1 Primary and Secondary Ports in a PCI Express Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Figure 5-2 Example AMC.1 Carrier Supporting Dual Hosts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Figure B-1 Basic I/O Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Figure B-2 PCI-E Carrier with an RC on a Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
Figure B-3 PCI-E Carrier with support for dual hosts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
Figure B-4 PCI-E Carrier populated with isolated RCs creating a compute farm . . . . . . . . . . . . . . . . B-4
Figure C-1 AdvancedMC Module Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
Figure C-2 ATCA Carrier Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3
Figure C-3 MicroTCA Backplane Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4
Figure C-4 Module-Backplane-Module Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5
Figure C-5 Module-Carrier-Module Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-6
Figure C-6 Module-Carrier Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7
Figure C-7 Module to Backplane to Module, Crx = 1.0µF at 2.5GT/s . . . . . . . . . . . . . . . . . . . . . . . . C-8
Figure C-8 Module to Backplane to Module, No Crx at 2.5GT/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-9
Figure C-9 Module to Carrier to Module, Crx = 1.0µF at 2.5GT/s . . . . . . . . . . . . . . . . . . . . . . . . . . C-10
Figure C-10 Module to Carrier to Module, No Crx at 2.5GT/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-11
Figure C-11 Carrier to Module, Crx = 1.0µF at 2.5GT/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-12
Figure C-12 Carrier to Module, No Crx at 2.5GT/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-13
Figure C-13 Module to Carrier, Crx = 1.0µF at 2.5GT/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-14
Figure C-14 Module to Carrier, No Crx at 2.5GT/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-15
Figure C-15 Module to Carrier to Module Insertion Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-16
Figure C-16 Module to Carrier to Module Return Loss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-17
Figure C-17 Module to Carrier to Module Impulse response, Crx = 1.0µF. . . . . . . . . . . . . . . . . . . . C-18
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
List of Tables
Table 1-1 AMC.1 terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Table 3-1 AMC Port Mapping Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Table 3-2 Sample of AMC.0 Port Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Table 4-1 List of AMC.1 Fabric Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Table 4-2 AMC.1 Fat Pipe Port Assignment on Basic and Extended Connectors . . . . . . . . . . . . . . . 4-3
Table 8-1 AMC.1 Applicable fields of an “AMC Point-to-Point Connectivity Record” . . . . . . . . . . . . . 8-2
Table 8-2 Record Type field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Table 8-3 Number of AMC Channel Descriptors for a Single AMC.1 Type . . . . . . . . . . . . . . . . . . . . . 8-3
Table 8-4 AMC Channel Descriptor Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Table 8-5 AMC.1 Channel Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Table 8-6 AMC.1 Channel Descriptors for Types 1 and 2 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
Table 8-7 AMC Link Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
Table 8-8 AMC Link Designator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
Table 8-9 AMC.1 Link Designators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
Table 8-10 PCI Express (Link Type 02h) - AMC Link Type Extensions . . . . . . . . . . . . . . . . . . . . . . . 8-8
Table 8-11 AMC Link Descriptor Asymmetric Match Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
Table 8-12 PCI Express (02h) - AMC Asymmetric Match Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
Table 8-13 Example E-Keying Configurations for Modules of Type 1, 2, and 4 . . . . . . . . . . . . . . . . 8-11
Table 8-14 Example E-Keying Configurations for Type 8 Modules . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
Table 8-15 AMC.1 Applicable fields of an AMC.0 “Direct Clock Descriptor” . . . . . . . . . . . . . . . . . . . 8-13
Table A-1 AdvancedMC Module Edge Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Table C-1 Modeling Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
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1 Introduction
¶1
1.1
AMC.1 defines the implementation of PCI Express on AMC.0 Modules and Carriers. It is
dependent upon and leverages AMC.0 for definition of the mezzanine’s mechanical,
interconnect, management, power and thermal requirements.
Scope
¶2
This is a subsidiary specification to AMC.0 and is limited in scope to defining Port usage and
Electronic-Keying (E-Keying) parameters for PCI Express. This specification includes
definition for both AdvancedMC Modules and Carriers. AMC.1 defines a single Fat Pipe Link
of 1, 2, 4, and 8 Lanes. AMC.1 also defines a reference clock for use with the Fat Pipe Link.
¶3
Compatibility between an AMC.1 Module and Carrier depends on a number of parameters
such as their negotiated Link width and the location of the Root Complex. AMC.1 addresses
only the parameters of the devices at each end of the Link which identify capabilities and
requirements or can be configured to establish a compatible Module and On-Carrier device
pair. Parameters beyond the scope of AMC.1 include:
• PCI Express Lane ordering, which are negotiated in hardware and are transparent to the
function of the Link
• PCI Express number of transaction classes, which requires system level software to
enumerate the capabilities of the entire system prior to configuring the parameter in the
devices throughout the hierarchy
• Support on a Carrier for peer-to-peer PCI Express transactions
¶4
1.2
Reference documents
¶5
1.2.1
AMC.1 takes precedence in the case of a conflict between AMC.0 and AMC.1 requirements.
The following sections list the publications that are relevant to this specification. Many of the
specifications are subject to periodic and independent updates and are the responsibility of
their respective organizations. Version and/or revision numbers of each specification should
be carefully checked if used in conjunction with this specification.
Reference specifications
¶6
The following publications are used in conjunction with this standard. When any of the
referenced specifications are superseded by an approved revision, the cited revision shall
apply. All documents may be obtained from their respective organizations.
• PCI Express Base Specification, Revision 1.1, PCI Special Interest Group,
www.pcisig.com
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• PCI Express Base Specification, Revision 2.0, PCI Special Interest Group,
www.pcisig.com
• PICMG® AdvancedMC.0 - Advanced Mezzanine Card Base Specification, Revision
2.0; PCI Industrial Computer Manufacturers Group (PICMG®), www.picmg.org
• ANSI/TIA/EIA-644-A-2001: Electrical Characteristics of Low Voltage Differential
Signaling (LVDS) Interface Circuits, January 1, 2001
• PICMG® Policies and Procedures for Specification Development, Revision 3.0, March
13, 2008, www.picmg.org
• PCI Express Card Electro-Mechanical (CEM) Specification, Revision 1.1, PCI Special
Interest Group, www.pcisig.com
• PCI Express Card Electro-Mechanical (CEM) Specification, Revision 2.0, PCI Special
Interest Group, www.pcisig.com
• PICMG® MicroTCA.0 - Micro Telecommunications Computing Architecture Base
Specification, Revision 1.0, PCI Industrial Computer Manufacturers Group (PICMG®),
www.picmg.org
• PICMG® 3.0 Revision 3.0 - Advanced TCA Base Specification, PCI Industrial
Computer Manufacturers Group (PICMG®), www.picmg.org
• PCI Express Architecture Mobile Graphics Low-Power Addendum to the PCI Express
Base Specification, Revision 1.0, October 21, 2003, PCI Special Interest Group,
www.pcisig.com
• AMC Port Map Gap-Analysis, Version 1.0, May 20, 2007, SCOPE Alliance,
www.scope-alliance.org
1.2.2
Environment and regulatory documents
¶7
1.3
All environment and regulatory requirements that pertain to the PICMG AMC.1 specification
are cited within the PICMG AMC.0 base specification.
Special word usage
¶8
In this specification the following key words (in bold text) will be used:
¶9
may:
indicates flexibility of choice with no implied preference.
¶ 10
should:
indicates flexibility of choice with a strongly preferred implementation. The use
of should not (in bold text) indicates flexibility of choice with a strong
preference that the choice or implementation be avoided.
¶ 11
shall:
indicates a mandatory requirement. Designers shall implement such mandatory
requirements to ensure interchangeability and to claim conformance with this
specification.The use of shall not (in bold text) indicates an action or
implementation that is prohibited.
Note:When not in bold text, the words “may”, “should”, and “shall” are being used in the traditional sense;
that is, they do not adhere to the strict meanings described above.
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¶ 12
1.4
1.5
This document uses requirement numbering as a way to find and reference AdvancedMC
requirements. Each requirement is numbered using the format “REQ X.YYz” where X is the
original section where the requirement is located, YY denotes the requirement number and is
a running sequence for each section, z denotes the revision of the requirement. Requirement
revisions note changes made to the requirement from the originally published requirement.
Requirements modified by Revision 2.0 are marked with a revision ‘a’. An index of the
requirements in this specification can be found at the end of the document.
Name and logo usage
¶ 13
The PCI Industrial Computer Manufacturers Group’s policies regarding the use of its logos
and trademarks are as follows:
¶ 14
Permission to use the PICMG organization logo is automatically granted to designated
members only as stipulated on the most recent Membership Privileges document (available at
www.picmg.org) during the period of time for which their membership dues are paid. Nonmembers must not use the PICMG organization logo.
¶ 15
The PICMG organization logo must be printed in black or color as shown in the files available
for download from the member’s side of the Web site. Logos with or without the “Open
Modular Computing Specification” banner can be used. Nothing may be added or deleted
from the PICMG logo.
¶ 16
Manufacturers’ distributors and sales representatives may use the AdvancedTCA and
AdvancedMC logos (but not the PICMG organization logo) in promoting products sold under
the name of the manufacturer. The use of AdvancedMC and MicroTCA logos is a privilege
granted by the PICMG organization to companies who have purchased the relevant
specifications (or acquired them as a member benefit), and who believe their products comply
with these specifications. Use of the logos by either members or non-members implies such
compliance. PICMG may revoke permission to use logos if they are misused. The
AdvancedMC logo can be found on the PICMG web site (www.picmg.org)
¶ 17
The PICMG name and logo are registered trademarks of PICMG. Registered trademarks must
be followed by the “®” symbol, and the following statement must appear in all published
literature and advertising material in which the logo appears: “The PICMG name and logo are
registered trademarks of the PCI Industrial Computer Manufacturers Group.”
Signal naming conventions
¶ 18
All signals are active high unless denoted by a trailing # symbol (e.g., RST#.) Differential
signals are denoted by a trailing + (positive) or – (negative) symbol (e.g., Rx2+.)
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1.6
1.6.1
1.6.2
1.6.3
Intellectual property
¶ 19
The Consortium draws attention to the fact that it is claimed that compliance with this
specification might involve the use of a patent claim(s) (Intellectual Property – “IPR”).The
Consortium takes no position concerning the evidence, validity, or scope of this IPR.
¶ 20
Under the PICMG Intellectual Property Rights Policy adopted by the Executive Membership
September 14, 2004 and updated in February/2008, the license grants of Necessary Claims
made in connection with this specification apply only to the Compliant Portion of an
implementation. As a result, they apply only to the required (as designated by the keyword
“shall”) or recommended (as designated by the keyword “should”) elements of a
specification that are within the bounds of the Statement of Work under which the
Specification was developed.
¶ 21
The holder of this IPR has assured the Consortium that it is willing to license or sublicense all
such IPR to those licensees (Members and non-Members alike) desiring to implement this
specification. The statement of the holder of this IPR to such effect has been filed with the
Consortium.
¶ 22
Attention is also drawn to the possibility that some of the elements of this specification might
be the subject of IPR other than those identified below. The Consortium is not responsible for
identifying any or all such IPR.
¶ 23
No representation is made as to the availability of any license rights for use of any IPR
inherent in this specification for any purpose other than to implement this specification.
¶ 24
This specification conforms to the current PICMG® Intellectual Property Rights Policy and
the Policies and Procedures for Specification Development and does not contain any known
intellectual property that is not available for licensing under Reasonable and Nondiscriminatory terms. In the course of Membership Review, the following disclosures were
made:
Necessary claims
¶ 25
(referring to mandatory or recommended features)
¶ 26
No disclosures in this category have been made.
Unnecessary claims
¶ 27
(referring to optional features or non-normative elements)
¶ 28
No disclosures in this category have been made.
Third party disclosures
¶ 29
(Note that third party IPR submissions do not contain any claim of willingness to license the
IPR.)
¶ 30
No disclosures in this category were made during subcommittee review.
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1.7
¶ 31
Refer to PICMG® IPR Policy and the company owner of any patent for terms and conditions
of usage.
¶ 32
PICMG® makes no judgment as to the validity of these claims or the licensing terms offered
by the claimants.
¶ 33
THIS SPECIFICATION IS BEING OFFERED WITHOUT ANY WARRANTY
WHATSOEVER, AND IN PARTICULAR, ANY WARRANTY OF NONINFRINGEMENT
IS EXPRESSLY DISCLAIMED. ANY USE OF THIS SPECIFICATION IS MADE
ENTIRELY AT THE IMPLEMENTER'S OWN RISK, AND NEITHER THE
CONSORTIUM, NOR ANY OF ITS MEMBERS OR SUBMITTERS, HAVE ANY
LIABILITY WHATSOEVER TO ANY IMPLEMENTER OR THIRD PARTY FOR ANY
DAMAGES OF ANY NATURE WHATSOEVER, DIRECTLY OR INDIRECTLY, ARISING
FROM THE USE OF THIS SPECIFICATION.
¶ 34
Compliance with this specification does not absolve manufacturers of equipment from the
requirements of safety and regulatory agencies (UL, CSA, FCC, IEC, etc.).
Acronyms and definitions
¶ 35
Acronyms and definitions used throughout this document are defined and referenced in the
PICMG AMC.0 base specification, Section 1.13. In order to maintain consistency between
AMC.0 and AMC.1, they are not repeated here.
¶ 36
The following select terms are either used in this document exclusive of the PICMG AMC.0
definitions or have been included to emphasize their meaning.
Table 1-1 AMC.1 terms
Term or Acronym
Description
AMC.1 Link
A PCI Express Link established in the Fat Pipe Region of the AdvancedMC
Connector.
ASI
Advanced Switching Interconnect.
Carrier switch
Refers to a switch on the AdvancedMC Carrier that connects two or more Ports
(including AdvancedMC Modules) to allow packets to be routed from one Port to
another. This term is used consistently in the AMC.0 E-Keying definition and is used
in the AMC.1 Management definition for consistency.
Device
An integrated circuit implementing one end of an AMC.1 Link.
Downstream
A direction of information flow through a PCI Express hierarchy where the
information is flowing away from the Root Complex.
Downstream
switch
A generally defined PCI Express switch. A Downstream switch is required to support
peer-to-peer transfers.
End Node
A PCI Express node that is not the Root Complex.
E-Keying
Abbreviation for Electronic Keying. Electronic Keying defines the process in which a
Carrier determines if the Control and Fabric interfaces on a Module are compatible
with the Carrier interconnects.
Gen1
Refers to the first generation of PCI Express which operates @ 2.5 GT/s in each
direction.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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Table 1-1 AMC.1 terms (Continued)
Term or Acronym
Description
Gen2
Refers to the second generation of PCI Express which operates @ 5.0 GT/s in each
direction.
GT/s
Giga-Transfers per second.
Host Switch
A PCI Express switch optionally closest to the Root Complex. A Host Switch is not
required to support peer-to-peer transfers.
Lane
1. [PCI Express] A set of differential signal pairs, one pair for transmission and one
pair for reception. One or more Lanes operate together to form a PCI Express Link.
2. E-Keying definition of a differential pair associated with a specific Fabric Link (e.g.,
a Link generally consists of Lanes[x:y].)
Link
One or more Ports aggregated under a common protocol. Links are groups of Ports
that are enabled and disabled by Electronic Keying operations. A xN Link
(pronounced “by-N Link”) is composed of N Ports.
A group of Lanes which operate together to connect two devices; the number of
Lanes used is negotiated.
Link Negotiation
The process whereby two PCI Express Ports negotiate a common number of PCI
Express Lanes, Lane polarity, Lane ordering, and Link speed that will be used to
interconnect the two PCI Express Ports and form a single Link.
Module and OnCarrier device
When used in a requirement this phrase specifically means that the requirement
applies equally to a PICMG® AMC.1 Module and to a PICMG® AMC.1 On-Carrier
device.
nF
Nano-Farads.
NTB
Non-Transparent Bridge.
On-Carrier Device
An On-Carrier device is a device located on a Carrier which provides a Link to a Slot.
This term is used consistently in the AMC.0 E-Keying definition and is used in the
AMC.1 Management definition for consistency.
PCI- Express
Interface
An expansion bus interface defined by the set of PCISIG PCI Express Specifications
and used in this AMC.1 Specification.
Peer-to-Peer
A transfer initiated by an End Node and targeting another End Node. Does not
require Root Complex intervention.
Port
A set of differential signal pairs, one pair for transmission and one pair for reception.
One or more Ports operate together to form a Link. A Port refers to the location of a
specific such pair on the AdvancedMC Connector and the associated traces on the
Carrier and Module.
PCI Express calls a Port a ‘Lane’, and uses the word Port to denote the interface at
one end of a Link. AMC.1 uses the AMC.0 sense of ‘Port’ unless specifically referring
to as a “PCI Express Port”. AMC.1 E-Keying defines the binding of Lanes to Ports.
Primary Host
A Primary Host is the primary Root Complex in a redundant PCI Express host
configuration.
Primary Port
A Primary Port is equivalent to an Upstream Port as defined in the PCI Express
Specification. The Port on a Switch that is closest topologically to the Root Complex
is the Primary Port. The Port on a component that contains only Endpoint or Bridge
Functions is a Primary Port.
ps
Pico-seconds
Root Complex or
RC
Location of the host for a PCI Express hierarchy.
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Table 1-1 AMC.1 terms (Continued)
Term or Acronym
Description
Secondary Host
A Secondary Host is the back-up Root Complex in a redundant PCI Express host
configuration.
Secondary Port
A Secondary Port is equivalent to a Downstream Port as defined in the PCI Express
Specification. The Ports on a Switch that are not the Primary Port are Secondary
Ports. All Ports on a Root Complex are Secondary Ports.
Slot
A Slot is a single AdvancedMC connection on an AdvancedMC Carrier or MicroTCA
backplane.
UI
Unit Interval (time to transmit one bit).
Upstream
Movement through a PCI Express hierarchy towards the Root Complex.
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2 PICMG® AMC.1 Compliance
¶1
Statements of compliance with this specification take the form specified in the PICMG
Policies and Procedures for Specification Development:
“This product complies with PICMG® AMC.1 Revision 2.0”
¶2
Products making this simple claim of compliance must meet, at a minimum, all features
defined in numbered requirements (REQ X.YYz) listed in this specification as being
mandatory by use of the keyword “shall” in the body of the requirement. Such products must
not include any feature prohibited by the use of the keyword “shall not” in the numbered
requirements contained in this specification. Such products may also provide recommended
features associated with the keyword “should” and permitted features associated with the key
word “may” contained within the numbered requirements.
¶3
A simple claim of compliance with a subsidiary specification indicates the presence of all
features defined as being mandatory by the user of the keyword “shall” in the body of that
specification and must not include any feature prohibited by the use of the keyword “shall
not.” Because subsidiary specifications may also provide for recommended and permitted
features beyond the mandatory minimum set and a range of performance capabilities, more
complete descriptions of product compliance are encouraged.
¶4
Definitions for the keyword terms used above are provided in section 1.3 of this specification.
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3.1
AMC.0 Compliance
Requirement
REQ 3.1
3.2
A PICMG® AMC.1 compliant Module and On-Carrier device shall conform to the
PICMG AMC.0 specification.
AMC.0 Port Mapping
¶1
Section 6, Interconnect, of the AMC.0 R2.0 specification, partitions use of the 20 available
Ports into three “recommended” regions: Common Options, Fat Pipes and Extended Options
(see Figure 3-1.) Although the partitions are given as general guidelines, they are not
intended to “reserve” or “prohibit” Port usage. The purpose of this partitioning is to provide
the industry with general guidelines that will ultimately encourage interoperability between
Modules and Carrier boards. As such, AMC.1 embraces this general partitioning and restricts
its data interface definition to the Fat Pipes Region. In addition, AMC.1 defines a reference
clock on FCLKA.
Table 3-1 AMC Port Mapping Regions
Basic Connector
M IS C
Extended Connector
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3 AMC.0
TCLKA
TCLKB
FCLKA
0
1
2
3
4
5
6
7
8
9
10
11
12
13
86
14
15
TCLKC/D
17
18
19
20
C lo c k s
C o m m o n O p tio n s R e g io n
F a t P ip e s R e g ion
E x te n d e d O p tio n s R e g io n
170
M IS
C
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3.3
Port Definition
¶2
A Port is defined as a pair of transmit and receive differential pairs. All differential pairs are
bound by Logic Ground. The shielding function of a Logic Ground is used for differential
pairs on both sides of the differential pair as appropriate. The point of reference for
“Transmit” and “Receive” is that of the AdvancedMC Module (i.e., signals are transmitted
from a Module to the Carrier and received by a Module from the Carrier.) Ports are numbered
from 0-15 and 17-20 as illustrated below in Table 3-2. For ease of reference, a copy of the
AMC.0 pin mapping is included (without GND pins) in Appendix A, “ AMC.0 Pin
Assignments”.
Table 3-2 Sample of AMC.0 Port Mappings
AMC Module Edge Connector Pin Assignment
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4 Link Specification
¶1
4.1
The term “AMC.1 Interfaces” will be used when referring collectively to the PCI Express
interface.
Electrical and Link Layer Rules
¶3
AMC.1 Interfaces share the same electrical and Link layer specification and the same
negotiation capabilities. AMC.1 Interfaces specify a serial point-to-point system with the
basic interface being a Link, which consists of one or more couplets of transmit pairs and
receive pairs of LVDS wires. The two LVDS pairs implement simplex communication in
opposite directions.
¶4
The physical layer of the first generation (Gen1) AMC.1 Interface operates at 2.5 GT/s in
each direction as defined in the PCI Express Base specification R1.1. The physical layer of
the second generation (Gen2) AMC.1 interface operates at 5.0 GT/s in each direction as
defined in the PCI Express Base specification R2.0.
¶5
The PCI SIG has defined a lower-power signaling specification for PCI Express
communication in the Mobile Graphics Low-Power Addendum to the PCI Express Base
Specification. However, devices using this addendum across the AdvancedMC connector
have a lower signal integrity loss budget and might experience compatibility issues if using
this lower voltage signaling. Therefore, this level of signaling is not considered compliant
with AMC.1.
¶6
The PICMG® AMC.0 specification defines support for up to 12.5 GT/s signaling rates,
which is sufficient to support both current and anticipated future generations of AMC.1
Interfaces. The electrical topologies specified in AMC.1 (Section 7, “Signal Integrity”)
define compliance for PCI Express Gen1 at 2.5 GT/s and PCI Express Gen2 at 5.0 GT/s.
Requirement
REQ 4.1
PICMG® AMC.1 Modules and On-Carrier devices shall conform to all the physical
and Link layer requirements as set forth in the PCI SIG PCI Express Base
Specification R2.0.
REQ 4.21
PICMG®AMC.1 Modules and On-Carrier devices shall not use the low-voltage
signaling specified in the Mobile Graphics Low Power Addendum to the PCI Express
Base Specification for communication between the Module and the Carrier.
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4.2
Dual-Mode Support
¶7
4.3
Support for Advanced Switching Interconnect and Dual-Mode support was deleted in
AMC.1 R2.0.
Ports and Link Widths
¶8
Performance is scalable for AMC.1 Interfaces. Bandwidth can be linearly scaled up by
adding more Ports, each Port carrying an additional Lane of PCI Express. Although PCI
Express allows for a number of Link widths (x1, x2, x4, x8, x12, x16 and x32), AMC.1
specifies support for x1, x2, x4 and x8 Link widths.
¶9
The Link layer for AMC.1 Interfaces defines automatic configuration of a Link between two
Link partners. During Link initialization, the interface in each device is configured following
a negotiation of Lane polarity, Lane ordering, Link width, and frequency of operation by the
two agents at each end of the Link. This Link Negotiation will negotiate downward to the
highest common number of Lanes that can be used to interconnect between the two. For
example:
• A x8 AMC.1 Interface is capable of auto-negotiating a x8 or x1 Link and may be
capable of negotiating a x4 or x2 Link.
• A x4 AMC.1 Interface is capable of auto-negotiating a x4 or x1 Link and may be
capable of negotiating a x2 Link.
• A x2 AMC.1 Interface is capable of auto-negotiating x2 or x1 Link.
¶ 10
PCI Express does not dictate support of all valid sub-widths on a device; it requires only a x1
capability along with any other supported Link widths. In order to foster interoperability,
AMC.1 strongly desires that a On-Carrier device support all valid sub-widths of its
maximum width. A Module can choose to support some or all sub-widths of its maximum
width in addition to x1 support.
¶ 11
The PCI Express requirement for x1 support ensures that any two devices can communicate,
but it is possible for a valid Link to be negotiated in hardware which provides insufficient
bandwidth for a Module. E-Keying recommendations for AMC.1, found in Section 8,
“Management and E-Keying” encourage an On-Carrier device to enumerate the widths that it
supports. Section 8 also specifies that a Module enumerates the minimum width it requires to
meet its bandwidth requirements plus all wider Links that it supports.
¶ 12
Each AdvancedMC Module site on a Carrier specifies its own AMC Fat Pipes Options and
Common Options. The sites on a Carrier are not required to be uniform.
Requirements
REQ 4.3a
A PICMG® AMC.1 On-Carrier device should support all legal sub-widths of its
maximum Link width in a Fat Pipe Link.
REQ 4.4a
A PICMG® AMC.1 Module may support AMC.1 Links of multiple widths including 1,
2, 4 and 8 Lanes.
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4.4
AMC.0 Basic and Extended Connector Support
¶ 13
Link width Designators for both AMC.1 Modules and On-Carrier devices supporting PCI
Express in the Fat Pipes Region will be referred to by the following “Type” classifications.
This is for ease-of-reference purposes only (also see Section 8, “Management and EKeying.” ) These Types indicate the Link width(s) supported by a Slot or required by a
Module. The E-Keying for an AMC.1 Module or On-Carrier device enumerates all Types
(widths) a Slot supports or all widths a Module can work with (see Table 4-1.) The Module
and On-Carrier device will negotiate in hardware the fastest common Link speed they
support, which is independent of compatibility as determined by E-Keying. However, if they
are compatible according to E-Keying, then they will negotiate a compatible width and speed
in hardware.
Table 4-1 List of AMC.1 Fabric Types
Type
Module
Carrier
Type 1
Works with a x1 Link
Provides a x1 Link
Type 2
Works with a x2 Link
Provides a x2 Link
Type 4
Works with a x4 Link
Provides a x4 Link
Type 8
Works with a x8 Link
Provides a x8 Link
¶ 14
The Designators apply to both the AMC.1 Modules and On-Carrier devices.
¶ 15
In support of the AMC.0 General Port Mapping Strategy as defined in AMC.0 Section 6, Fat
Pipes support on a Basic Connector is defined using Ports 4 through 7. As such, Basic
Connectors are capable of supporting x1, x2 and x4 Link widths. Fat Pipes support on an
Extended Connector is defined as using Ports 4 through 11 in support of a x8 Link.
¶ 16
Few usage models exist to justify supporting multiple Links of PCI Express fabric on an
AdvancedMC Module. In order to foster maximum interoperability, AMC.1 specifies only a
single Link at a known location in the Fat Pipes Region.
¶ 17
See Table 4-2 for Port assignments for each Link width on a Basic Connector and on an
Extended Connector.
Table 4-2 AMC.1 Fat Pipe Port Assignment on Basic and Extended Connectors
Port Number
Type 1
Basic
Type 2
Type 4
Type 8
Extended
x1 Link
4
4
5
5
(Unassigned)
6
6
(Unassigned)
(Unassigned)
7
7
(Unassigned)
(Unassigned)
8
(Unassigned)
(Unassigned)
(Unassigned)
9
(Unassigned)
(Unassigned)
(Unassigned)
10
(Unassigned)
(Unassigned)
(Unassigned)
11
(Unassigned)
(Unassigned)
(Unassigned)
x2 Link
x4 Link
x8 Link
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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¶ 18
Note that the SCOPE Alliance AMC Port Map Gap-Analysis document recommends usage
of a x4 PCI Express Link width for AdvancedMCs and against usage of x8 Link widths. The
PICMG AMC.1 Specification includes an x8 PCI Express Link capability for backwards
compatibility with previous versions of the specification and for use in applications that are
outside the purview of the SCOPE Alliance.
Requirement
REQ 4.5a
4.5
PICMG® AMC.1 Modules and On-Carrier devices shall support a single AMC.1 Link of
up to 8 PCI Express Lanes, using contiguous Ports starting with Port 4 as shown in
Table 4-2.
Reference Clock
¶ 19
The PCI Express Base Specification, in conjunction with the PCI Express Card
Electromechanical (CEM) specification, defines three clock architectures: “common
reference clock (Refclk) architecture”, “data clocked architecture”, and “separate reference
clock (Refclk) architecture”. The majority of devices targeting both the consumer and the
embedded markets support the common reference clock architecture. To ensure the largest
availability of devices and the maximum interoperability between AdvancedMC Modules
and Carriers using those devices, this specification focuses on supporting the common
reference clock architecture defined in the PCI Express specifications.
¶ 20
With a common reference clock provided to an expansion connector, PCI Express allows
electromechanical specifications such as AMC.1 to specify if the device on the clock-source
side of the connector is required to use that reference clock source. To avoid interoperability
issues and ensure maximum compatibility, this specification mandates that a common
reference clock, provided on FCLKA, is used by both the Upstream and Downstream
devices. This applies regardless of whether the Root Complex is on an AMC.1 Module or on
the Carrier.
¶ 21
PCI Express also allows in Section 4.3.1.1.1 that a common reference clock may be slightly
modulated (Spread Spectrum Clock or “SSC”) by 30-33 kHz in order to reduce emissions.
The PCI Express Base Specification stops short of requiring in that case that both devices on
a Link use the common reference clock; but jitter requirements imply that either both use it,
or that if one device does not use it then both devices on the Link must be able to track the
slow variation in the bit rate. Mandating the use of a common reference clock on FCLKA
minimizes such interoperability issues. Section 4.3.7 of the PCI Express Base Specification
Revision 2.0 provides an electrical specification for the reference clock at 5.0 GT/s only. The
electrical specification for 2.5GT/s reference clock is referenced from the PCI Express Card
Electro-Mechanical Specification revision 2.0.
¶ 22
AMC.1 requires that Carriers that provide a PCI Express fabric connection from On-Carrier
PCI Express devices to AMC Slots must provide those AMC Slots a common reference
clock. On-Carrier devices could be, for example, a PCI Express Switch, a Root Complex
device or an Endpoint device. The clocks for all such devices within the same PCI Express
hierarchy as the AMC Modules, and the clock to the AMC Slots themselves, must be derived
from a common source provided by the Carrier.
¶ 23
Additionally, AMC.1 requires that AMC.1 Modules be capable of receiving a common
reference clock on FCLKA. AMC.1 provides two additional recommendations for FCLKA
capability on Modules. The first recommendation is that AMC.1 Modules with devices
capable of non-AMC.1 fabric interfaces be capable of operating in scenarios where a
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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common reference clock is not provided on the FCLKA pins, such as on a Carrier that does
not support AMC.1 PCI Express. A few devices have been found to be rendered inoperable if
they do not receive a PCI Express reference clock. This goes beyond just the PCI Express
interface itself being inoperable; compute functions and other fabric interfaces become
inoperable as well.
¶ 24
The second recommendation is that Modules providing Root Complex capability be
optionally capable of sourcing the FCLKA as an output from the Module. This will enable
such AdvancedMC Modules to be used in Carriers providing direct slot-to-slot connectivity
of both the PCI Express fabric, and the reference clock.
¶ 25
Carriers that provide direct slot-to-slot PCI Express fabric connectivity are permitted to also
route the FCLKA clock directly from slot-to-slot as well. Carriers utilizing such a topology
are typically trying to avoid the single-point-of-failure aspect of centralized clock
distribution. In such a scenario, the Root Complex Module provides the clock to the FLCKA
pins of the AMC Slot, the Carrier routes that clock directly to another AMC Slot, and the
Endpoint Module in that Slot receives the clock on it’s FCLKA pins. Carriers supporting
direct slot-to-slot connection of the PCI Express fabric and FCLKA require Root Complex
Modules that support the optional clock output capability described above. This could be
especially applicable in a MicroTCA environment.
¶ 26
AMC.1 Carriers and Modules that source FCLKA are required to disable their FCLKA
drivers until enabled as determined by clock E-Keying specified in AMC.0 R2.0. Electrical
isolation of FCLKA receivers until enabled by clock E-Keying is optionally permitted
though not required by this specification.
¶ 27
Important: The requirements below take precedence over the AMC.0 specification’s
requirements related to FCLKA signals. FCLKA termination and signaling is per the PCI
Express specifications, and not M-LVDS. Although it is not operational, it is recommended
that AMC.1 Modules be designed such that thay will not be damaged if a Carrier drives
FCLKA with an M-LVDS driver.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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Requirements
REQ 4.9a
PICMG® AMC.1 Modules and Carriers implementing 2.5GT/s capability shall
implement FCLKA as the common reference clock, as specified in the PCI Express
Card Electro-Mechanical (CEM) Specification, Revision 2.0.
REQ 4.26
PICMG® AMC.1 Modules and Carriers implementing 5.0GT/s capability shall
implement FCLKA as the common reference clock, as specified in the PCI Express
Base Specification, Revision 2.0.
REQ 4.6a
PICMG® AMC.1 Carriers that implement a PCI Express fabric connection from OnCarrier PCI Express devices to AMC Slots shall be capable of sourcing FCLKA to
those AMC Slots.
REQ 4.27
PICMG® AMC.1 Carriers with direct slot-to-slot PCI Express connections shall either
source FCLKA to those Slots, or shall route FCLKA directly from slot-to-slot for those
AMC Slots.
REQ 4.8a
PICMG® AMC.1 Modules shall be capable of receiving FCLKA.
REQ 4.20
PICMG® AMC.1 Modules may implement electrical isolation on FCLKA receivers,
controlled by clock E-Keying.
REQ 4.23
PICMG® AMC.1 Modules that receive FLCKA may implement AC coupling
capacitors on the FCLKA signals.
REQ 4.10
PICMG® AMC.1 Modules that implement a PCI Express Root Complex should be
capable of sourcing FCLKA, for use in Carriers with slot-to-slot FCLKA.
REQ 4.28
PICMG® AMC.1 Modules may implement REQ 4.8a and REQ 4.10 as build options in
which case REQ 4.8a and REQ 4.10 are not required to be met simultaneously.
REQ 4.14
AMC.1 Modules and Carriers that source FCLKA shall ensure that the FCLKA drivers
are disabled by default and only active when enabled by clock E-Keying.
REQ 4.22
AMC.1 Modules and Carriers that source FCLKA shall implement source-termination
as specified by the source device’s specifications.
REQ 4.29
PICMG® AMC.1 Modules providing non-AMC.1 fabric interfaces or compute
functionality usable in Carriers without PCI Express capability should be capable of
operation in cases where FCLKA is not present.
REQ 4.11
The FCLKA source in REQ 4.6a and REQ 4.10 may support a spread spectrum clock
(SSC).
REQ 4.12
PICMG® AMC.1 Carriers or Modules that source an SSC FCLKA shall provide a
mechanism to disable SSC modulation of the FCLKA source.
REQ 4.24
A Carrier sourcing FCLKA should provide visibility into the FCLKA SSC state
(enabled or not) to its IPM Controller.
REQ 4.25
A Module sourcing FCLKA should provide visibility into the FCLKA SSC state
(enabled or not) to its Module Management Controller.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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4.6
Additional Common Link-Level Considerations
4.6.1
Sleep Modes
¶ 28
4.6.2
Support for and use of PCI Express sleep modes are beyond the scope of AMC.1.
Presence Detect
¶ 29
AMC.1 supports the use of in-band presence detect in accordance with the PCI Express Base
specification. Presence detection for hot plug events is managed via AMC.0 management
facilities.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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4-8
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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5 PCI Express
5.1
Introduction
¶1
PCI Express builds a hierarchical system of nodes interconnected via switches using the
previously described point-to-point Links. There is a “Root Complex” (RC) host at the top of
the hierarchy and a number of End Nodes at the bottom. Traffic moving through the
hierarchy towards the RC is considered to be moving Upstream, and traffic moving towards
an End Node is considered to be moving Downstream. A “Primary Port” on a node or switch
moves data upstream to the “Secondary Port” on its Link Peer Device, while Downstream
data moves from a Secondary Port to a Primary Port (see Figure 5-1.) The PCI Express
specification uses the terms Upstream and Downstream for both traffic flow and to describe
the ports. This specification uses Upstream and Downstream for traffic flow, but uses
Primary and Secondary to describe ports. A Primary Port in this specification is equivalent to
an Upstream Port in the PCI Express specification; similarly, a Secondary Port in this
specification is equivalent to a Downstream Port in the PCI Express specification.
¶2
Most PCI Express switches support peer-to-peer transfers among End Nodes; the one
exception is that the host switch in a Root Complex is not required to provide this
functionality. In a peer-to-peer transaction an End Node initiates a transaction which targets
another End Node without intervention from the Root Complex; the transaction moves first
Upstream, then Downstream from the initiator to the switch(es) to the target.
¶3
Compatibility between a PCI Express Module and a On-Carrier device depends on a number
of parameters such as the width of the Link that can be established between them, location of
the Root Complex and others. Those parameters which are configured transparently by
hardware and do not affect the functionality of a Module in a system (such as Lane ordering)
are outside the scope of AMC.1. Those parameters whose configuration depends on
information beyond the two parties on the Link (such as the number of virtual channels to use
in the system) are also outside the scope of AMC.1.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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Figure 5-1 Primary and Secondary Ports in a PCI Express Hierarchy
CPU &
Root Complex
S
P = Primary Port
S = Secondary Port
1 = Upstream Traffic
2 = Downstream Traffic
3 = Peer-to-Peer Traffic
S
2
P
P
PCI-E Switch
S
S
1
3
¶4
5.2
End Node
S
P
P
P
End Node
End Node
End Node
An AMC.1 Carrier Board for PCI Express is likely to have a PCI Express switch, and the
characteristics of a On-Carrier device represent the characteristics of the switch Port
connected to that Slot. Alternatively a Module with a Root Complex might connect directly
to a different Module with one or more End Nodes without first passing through a fanout
switch on the Carrier. An AMC.1 Module might have either a single node connected to the
Carrier, or might have a switch on the Module to fan out from the Carrier Switch Port to
multiple PCI Express devices on the Module. It is also possible for a Carrier to have multiple
PCI Express switches connected in a single hierarchy, and also for a Carrier to have multiple
switches for independent PCI Express domains each with their own Root Complex. AMC.1
makes no assumptions about the switch architecture on the Carrier or Module.
PCI Express Compliance
Requirement
REQ 5.1
A PICMG® AMC.1 Module and On-Carrier device operating with a PCI Express Link
shall conform to all the protocol and management specifications set forth in the PCI-SIG
PCI Express Base Specification.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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5.3
PCI Express Parameters
5.3.1
Primary and Secondary PCI Express Ports
¶5
A Module with one or more End Nodes has a Primary PCI Express switch Port. An OnCarrier device which supports a Module with End Nodes has a Secondary PCI Express
Switch Port, thus a secondary On-Carrier device is compatible with a primary Module.
Conversely, an On-Carrier device which supports a Module with a Root Complex has a
Primary Port, and the compatible Module providing the Root Complex has a Secondary Port.
¶6
A Module or On-Carrier device which is capable of supporting both Primary and Secondary
behavior indicates this by listing both capabilities. Such a Module or On-Carrier device is
compatible with a peer who supports a Primary Port, a Secondary Port, or both. The ability to
offer both kinds of behavior indicates the presence of both a Root Complex path and a NonTransparent Bridge which can be used to isolate the PCI Express hierarchy of that Root
Complex, as described in Section 5.3.2, “Multiple Hosts.”
Requirement
REQ 5.2
A PICMG® AMC.1 Module and On-Carrier device operating with a PCI Express Fabric
Link shall indicate if its PCI Express Port is a Primary or Secondary Port with the
appropriate AMC Link Extension as defined in Section 8, “Management and E-Keying.”
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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5.3.2
Multiple Hosts
¶7
Note:
Note:
While PCI Express is a single-hosted hierarchy, non-standard mechanisms exist and have
been used in the past to allow a Secondary Host to take over for the Primary Host in a PCI
environment. Given the target environments for AdvancedMC Modules it is likely that
support for redundant Root Complex Modules will become common so there is impetus to
provide support capability for this in AMC.1. Following is a description of the support and
requirements to enable such failover support.
The designation of a host as Primary Host or Secondary Host has to do with their order in a failover
hierarchy and has nothing to do with PCI Express Primary or Secondary Ports.
¶8
The suggested mechanism is for a Carrier to designate two Slot/Module pairs as the Primary
and Secondary Hosts (Root Complexes.) In the suggested mechanism non-transparent
bridging and host switch-over would be provided by the Carrier switch. A Non-Transparent
Bridge (NTB) mechanism allows a PCI Express hierarchy to see an address window into the
address space of a different PCI Express hierarchy, and to expose a window in its own
address space for access by agents on that different hierarchy. This non transparent bridging
is not part of the PCI Express standard and is also beyond the scope of AMC.1. With host
switch-over a switch can exchange whether the Primary Host Link or a Secondary Link
provides the RC for that switch's hierarchy, and which Host Link’s address space ends at its
NTB.
¶9
Both Root Complex Modules would present a Secondary Port to the switch, and the switch
would provide a Primary Port to each. However, the RC in the Primary Host Slot would be
the RC used by the switch to host the rest of its hierarchy, while the domain of the RC in the
Secondary Host Slot would terminate at the NTB associated with the Secondary Host Link.
The Secondary Host would see the address window(s) into the other hierarchy as a memory
or I/O device. When a change of ownership occurs, the switch would use the Secondary Host
Slot as the RC for its hierarchy, and terminate the domain of the RC in the Primary Host Slot
at the NTB associated with that Link.
¶ 10
In general redundant processors maintain a sideband communication channel for heartbeat
exchange and often for state update between the two processors. AMC.1 recommends that
Modules and AMC Slots intended for redundant host Modules also support a single Ethernet
Port of Gigabit Ethernet on Port 0 as specified in AMC.2. Provisions for a higher-bandwidth
update channel between the Modules is beyond the scope of AMC.1, but it is suggested that
such a channel might use Ports starting at Port 12.
The primary and secondary root capability defined in section 5 is different from the IOV and multiroot capability defined by PCISIG.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
Figure 5-2 Example AMC.1 Carrier Supporting Dual Hosts
Backplane
P = Primary Port
S = Secondary Port
PH= Primary Host Link
SH = Secondary Host Link
NTB = Non Transparent
Bridge
PCI-E Switch
Primary
Secondary
NTB
NTB
P
PH
CPU &
Root
Cmplx
S
S
S
S
S
SH
S
S
S
P
CPU &
Root
Cmplx
P
AMC.1
Module
(PCI-E)
P
AMC.1
Module
(PCI-E)
P
AMC.1
Module
(PCI-E)
P
AMC.1
Module
(PCI-E)
P
AMC.1
Module
(PCI-E)
P
AMC.1
Module
(PCI-E)
¶ 11
Any number of Modules containing a Root Complex can be supported on a switch each with
a Non-Transparent Bridge, as their local hierarchy is not visible to the Root Complex for the
hierarchy. A Carrier switch would need an NTB on each Link which supported this; each
such Link might or might not also be capable taking over as RC for the system. Alternatively,
a Module might support a dual-mode bridge which can act as an NTB and which can also be
made transparent. When the bridge is transparent, that Module presents a Root Complex to
the On-Carrier device. Such Modules can be used for example to construct a compute farm as
shown in Figure B-4 and can optionally provide the RC for a hierarchy on the Module, with
the dual mode bridge in the transparent mode and the Module inserted into an RC-capable
Slot.
¶ 12
As mentioned earlier, AMC.1 does not assume a single switch connecting all Slots in one
hierarchy. While the above example in Figure 5-2 shows two Root Complex Slots associated
with a single switch on the Carrier, a Carrier might have multiple switches each with its own
pair of Root Complex modules arranged as Primary and Secondary Hosts.
¶ 13
The presence of an NTB or host failover support on a Carrier switch Port is not visible to a
Module. AMC.1 makes no provision for indicating these as use of them is beyond the scope
of AMC.1. E-keying parameters indicate if a compatible Module and On-Carrier device
together can support operation with the Module providing RC to the switch, or operating as
an End Node.
Requirements
REQ 5.3
A PICMG® AMC.1 Carrier may provide support for failover of the PCI Express host
from a Primary Host Module to a Secondary Host Module.
REQ 5.4
A PICMG® AMC.1 Module and On-Carrier device intended for a system supporting
Root Complex failover should support a Gigabit Ethernet Port on Port 0 as defined in
AMC.2.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
REQ 5.5
5.4
A PICMG® AMC.1 On-Carrier device in a system supporting Root Complex failover
should provide transparent bridging for the active Host and non-transparent bridging for
the inactive Host.
Type P Control Path Support
¶ 14
The Type P control path was removed in AMC.1 R2.0.
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6 Advanced Switching
¶1
Support for Advanced Switching Interconnect was removed in AMC.1 R2.0.
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7 Signal Integrity
¶1
This chapter describes the electrical requirements for compliant AMC.1 Modules and
Carriers at both 2.5 GT/s and 5 GT/s. The PCI Express Base Specification Revision 2.0
provides the definition of signaling at both 2.5GT/s and 5.0GT/s and Appendix C, “Signal
Integrity Analysis” discusses the signal integrity analysis that was performed to arrive at
these requirements.
¶2
The trace lengths in the requirements of this section were calculated using the channel
characteristics described in section “C.1.1 Modeling Parameters".Other trace lengths might
be possible when using PCB materials or geometries with different channel characteristics as
long as signal integrity is maintained.
7.1
PCI Express at 2.5 GT/s
7.1.1
Minimum Receiver Requirements at 2.5 GT/s
¶3
At 2.5 GT/s, the minimum eye mask per Figure 4-26 of the PCI Express Base Specification
1.1 is used.
Requirements
7.1.2
REQ 7.1a
Minimum eye amplitude at the receiving end of a Link operating at 2.5 GT/s on AMC.1
Modules and Carriers shall comply with the eye mask for 2.5 GT/s PCI Express
operation as specified in the PCI Express Base Specification 1.1.
REQ 7.2a
Maximum jitter at the receiving end of a Link operating at 2.5 GT/s on AMC.1 Modules
and Carriers shall comply with the maximum jitter requirement for 2.5 GT/s PCI Express
operation as specified in the PCI Express Base Specification 1.1.
AMC.1 Signal Interconnection Requirements for 2.5 GT/s
¶4
Even though the minimum required eye amplitude is 175 mV, a margin of 150-200 mV is
recommended over the minimum due to the broad assumptions made for simulation
purposes. Several test cases that were run indicated that there is adequate margin for both the
configurations; Module-to-Carrier as well as Module-to-Carrier-to-Module. These test cases
indicated that the capacitor location is not critical at 2.5 GT/s. PCI Express requires the
capacitors to be placed close to the transmitter. As specified earlier in REQ 4.1 an AMC.1
Module or Carrier must comply with all aspects of the PCI Express Gen1 or Gen2 physical
specification as appropriate, so AMC.1 follows the PCI Express capacitor placement
requirement, but adds an additional capacitor on the receive side as well to avoid direct
coupling issues with other protocols that might be present on an AdvancedMC connector.
¶5
Since the other AdvancedMC variants such as AMC.2 and AMC.4 mandate that coupling
capacitors be placed at the receive end, there is a potential for damage to components if an
AMC.1 board is plugged into a system expecting a board other than an AMC.1 board
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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because one pair would have two sets of capacitors, and the other pair would have none. To
eliminate this problem, a second pair of capacitors is inserted in the receive pair between the
AdvancedMC connector and the receiver chip.
¶6
Simulation and tests with the additional capacitors have been done and the results indicate
that there is no significant degradation of the PCI Express performance as long as the normal
good engineering practices are followed as would be required for any PCI Express design.
The test and simulation results may be found in the AMC.1 section of the PICMG web site
Requirements
7.2
7.2.1
REQ 7.3
Maximum trace length from the transmitter of a device operating at 2.5 GT/s on an
AMC.1 Module to the Connector shall not exceed 76 mm.
REQ 7.4
Maximum trace length from the transmitter of a device operating at 2.5 GT/s on a AMC.1
Carrier to a Module Connector shall not exceed 381 mm.
REQ 7.5
Maximum trace length from the receiver of a device operating at 2.5 GT/s on an AMC.1
Module to the Connector shall not exceed 76 mm.
REQ 7.6
Maximum trace length from the receiver of a device operating at 2.5 GT/s on a AMC.1
Carrier to a Module Connector shall not exceed 381 mm.
REQ 7.7
Maximum trace length on an AMC.1 Carrier between two Module connectors shall not
exceed 305 mm for operation at 2.5 GT/s.
REQ 7.8
Maximum difference in length on the traces of a differential pair to the Connector on an
AMC.1 Module shall not exceed 1.5 mm for operation at 2.5 GT/s.
REQ 7.9
Maximum difference in length on the traces of a differential pair from a device on an
AMC.1 Carrier to the Connector shall not exceed 1.5 mm for operation at 2.5 GT/s.
REQ 7.10
Maximum difference in length on the traces of a differential pair between two
Connectors on an AMC.1 Carrier shall not exceed 1.5 mm for operation at 2.5 GT/s
REQ 7.23
A pair of 100nF +/-10% capacitors shall be placed in each PCI Express transmit pair in
series between the transmit chip and the AdvancedMC connector for operation at 2.5GTs.
REQ 7.24
A pair of capacitors of value between 680nF -10% and 1000nF +10% shall be placed in
each PCI Express receive pair in series between the receiver chip and the AdvancedMC
connector for operation at 2.5GT/s.
PCI Express at 5 GT/s
Minimum Receiver Requirements at 5 GT/s
Requirements
¶7
At 5.0 GT/s, the minimum eye mask per Figure 4-41 of the PCI Express Base Specification
2.0 is used.
REQ 7.11a
Minimum eye amplitude at the receiving end of a Link operating at 5 GT/s on AMC.1
Modules and Carriers shall comply with the eye mask for 5 GT/s PCI Express operation
as specified in the PCI Express Base Specification 2.0.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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REQ 7.12a
7.2.2
Maximum jitter at the receiving end of a Link operating at 5 GT/s on AMC.1 Modules
and Carriers shall comply with the maximum jitter requirement for 5 GT/s PCI Express
operation as specified in the PCI Express Base Specification 2.0.
AMC.1 Signal Interconnection Requirements at 5 GT/s
¶8
Even though the minimum acceptable eye amplitude is 175 mV, a margin of 150-200 mV is
recommended over the minimum due to the broad assumptions made for simulation
purposes. Several test cases that were run indicated that there is adequate margin for both the
configurations; Module-to-Carrier as well as Module-to-Carrier-to-Module. These test cases
indicated that the capacitor location is not critical for 5 GT/s. AMC.1 follows the PCI
Express requirement that the capacitors to be placed close to the transmitter, and also adds an
additional capacitor on the receive side as well to avoid direct coupling issues with other
protocols that may be present on an AMC connector.
¶9
Module-to-Carrier test cases at 5 GT/s showed sufficient margin. The eye patterns for test
cases for Module-to-Carrier-to-Module configuration at 5 GT/s started shrinking. For the
worst case of Module-to-Carrier-to-Module configuration, the amplitude margin was 149
mV and the peak deterministic jitter was 56 ps or 0.28UI. Note that the HSPICE model
device specification is 0.36UI. It can be concluded from all of the test cases for the Moduleto-Carrier-to-Module configuration that the performance with 18" trace length depends on
the specific characteristics of the 5GT/s devices used. These include drive level, pre/de
emphasis, receiver equalization, etc. Hence, it is strongly recommended that if trace lengths
exceed 11" for either the Module-to-Module or Module-to-Carrier cases, the signal integrity
of the system needs to be verified for performance using simulation. Since the expected
maximum trace length on a Module is 3", the signal integrity performance ought to be
reviewed for any Carrier with Module to Module traces longer than 5" or any Carrier with
Module-to-Carrier traces longer than 8".
¶ 10
The coupling capacitor requirements for PCI Express Gen2 are the same as those for PCI
Express Gen1.
Requirements
REQ 7.13
Maximum trace length from the transmitter of a device operating at 5 GT/s on an AMC.1
Module to the Connector shall not exceed 76 mm.
REQ 7.14
Maximum trace length from the transmitter of a device operating at 5 GT/s on a AMC.1
Carrier to a Module Connector shall not exceed 381 mm.
REQ 7.15
Maximum trace length from the receiver of a device operating at 5 GT/s on an AMC.1
Module to the Connector shall not exceed 76 mm.
REQ 7.16
Maximum trace length from the receiver of a device operating at 5 GT/s on a AMC.1
Carrier to a Module Connector shall not exceed 381 mm.
REQ 7.17
Maximum trace length on an AMC.1 Carrier between two Module connectors shall not
exceed 305 mm for operation at 5 GT/s.
REQ 7.18
Maximum difference in length on the traces of a differential pair to the Connector on an
AMC.1 Module shall not exceed 1.5 mm for operation at 5 GT/s.
REQ 7.19
Maximum difference in length on the traces of a differential pair from a device on an
AMC.1 Carrier to the Connector shall not exceed 1.5 mm for operation at 5 GT/s.
REQ 7.20
Maximum difference in length on the traces of a differential pair between two
Connectors on an AMC.1 Carrier shall not exceed 1.5 mm for operation at 5 GT/s.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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REQ 7.21
A pair of 100nF +/- 10% capacitors shall be placed in each PCI Express transmit pair
between the AdvancedMC connector and the transmit chip for operation at 5 GT/s.
REQ 7.22
A pair of capacitors of value between 680nF -10% and 1000nF +10% shall be placed in
each PCI Express receive pair between the AdvancedMC connector and the receiver chip
for operation at 5 GT/s.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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8 Management and E-Keying
8.1
¶1
This section defines how to consistently implement AMC.0 Electronic-Keying (E-Keying)
requirements on AMC.1 Modules and Carriers. The intent of this section is to build on the Ekeying requirements of Chapter 3 of AMC.0 to define additional AMC.1-specific
requirements.
¶2
AMC E-Keying provides a mechanism by which the Carrier IPM Controller verifies
interoperability and determines configuration parameters for AdvancedMC Modules plugged
into AdvancedMC Carrier Slots. AMC E-Keying is defined and supported for both Moduleto-Module and Carrier-to-Module connections.
AMC Fabric E-Keying
¶3
8.1.1
The following sections provide details related to the various fabric E-Keying records and
fields.
AMC Point-to-Point Connectivity Record
¶4
The capabilities of an AdvancedMC Module to communicate over point-to-point
connections are described in the “AMC Point-to-Point Connectivity Record” (defined in
AMC.0 R2.0 Section 3.9.1.2, Table 3-16.) This record is included in both the AdvancedMC
Module and AdvancedMC Carrier FRU Information. These connections, each consisting of
some subset of AMC Ports, are generically referred to as “Links”. Table 8-1 identifies a
subset of this AMC Point-to-Point Connectivity Record and highlights those fields that are
directly applicable to this AMC.1 subsidiary specification. Additional fields further defined
in this record include: Record Type ID, End of List/Version, Record Length, Record
Checksum, Header Checksum, Manufacturer ID, PICMG Record ID, Record Format
Version, OEM GUID Count and OEM GUID List.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
Table 8-1 AMC.1 Applicable fields of an “AMC Point-to-Point Connectivity Record”
Length
(Bytes)
8.1.1.1
Definition
1
Record Type
An AdvancedMC Module or On-Carrier device. (See Section 8.1.1.1, “Record Type.” )
1
AMC Channel Descriptor Count
The total number, m, of AMC Channel Descriptors defined in this record to a maximum of 255.
(See Section 8.1.1.2, “AMC Channel Descriptor Count.” )
3*m
AMC Channel Descriptors
A list of m three-byte AMC Channel Descriptors, each defining up to four AMC.0 Ports that
make up an AMC Channel. (See Section 8.1.1.3, “AMC Channel Descriptors.” )
5*p
AMC Link Descriptors
Each AMC Link Descriptor details one type of point-to-point protocol supported by the
referenced Ports. Each Channel may support multiple, p, Link Descriptors.
A variable length list of p five-byte AMC Link Descriptors. (See Section 8.1.1.4, “AMC Link
Descriptors.” )
¶5
The AMC Point-to-Point Connectivity Record defines the AMC.1 options and requirements
supported by the Module and Carrier. The Carrier IPM Controller searches these records on
the AdvancedMC Module and Carrier (or on a pair of connected Modules) to determine if
there is a match.
¶6
When a Carrier IPM Controller is determining an E-Keying match, the AMC Link Descriptor
fields of AMC Link Designator, AMC Link Type, AMC Link Type Extension, and AMC
Asymmetric Match are compared.
¶7
The following sections within this chapter further outline and describe the E-Keying fields of
an AMC Point-to-Point Connectivity Record as outlined in Table 8-1.
Record Type
¶8
AMC.0 E-Keying defines a Record Type field to distinguish between a Module and a Carrier.
AMC.1 Modules are Record Type 1 and Carriers are Record Type 0 (See Table 8-2.)
Table 8-2 Record Type field description
Bits
7
8.1.1.2
Definition
Record Type
Carrier = 0
Module = 1
6:4
Reserved; write 0h.
3:0
Connected-device ID if Record Type =0; otherwise, reserved,
write as 0h.
AMC Channel Descriptor Count
¶9
The AMC Channel Descriptor Count is an 8-bit field that defines the total number of AMC
Channels up to a maximum of 255 defined in this AMC Point-to-Point Connectivity Record.
A Channel is defined as a set of up to four Ports.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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¶ 10
AMC.1 Types 1, 2, and 4 utilize a single Channel while Type 8 requires two four-Port
Channels (see Table 8-3) to specify 8 Lanes.
Table 8-3 Number of AMC Channel Descriptors for a Single AMC.1 Type
Fat Pipe Region
Number of AMC Channel
Descriptors per Type
Type 1
Type 2
Type 4
Type 8
1
1
1
2
¶ 11
The AMC Channel Descriptor Count is the sum of all the Channels defined in this record.
¶ 12
The AMC Channel Descriptor Count field is applicable to both an AMC.1 Module and a
Carrier, although their values may differ. AMC E-Keying does not compare this field for a
match as it indicates size of a data structure and not device compatibility. As a general rule,
one would expect the On-Carrier device to be more flexible in supporting multiple AMC.1
Types or multiple protocols in order to support a variety of AdvancedMC Modules.
Therefore, a Carrier record would be more likely to have a higher AMC Channel Descriptor
Count than a Module record.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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8.1.1.3
AMC Channel Descriptors
¶ 13
AMC Channel Descriptors define AMC Channels, each composed of up to four Ports, that
are implemented between AMC end-points. A Channel defines the binding between up to 4
logical Lanes and physical Ports. One or more Link Descriptors refer to a Channel Descriptor
with an index called the Channel ID.
¶ 14
Supported end-point pairings per the AMC.0 specification are Module-to-Module and
Carrier-to-Module. The AMC Channel Descriptor Count equals the total number of AMC
Channel Descriptors for each AMC Point-to-Point Connectivity Record. The general
structure of an AMC Channel Descriptor is defined in Table 8-4:
Table 8-4 AMC Channel Descriptor Definition
Bits
Description
23:20
Reserved. Must be 1111b.
19:15
Lane 3 Port Number. The Port within this AMC resource functions as Lane 3 of this AMC Channel.
14:10
Lane 2 Port Number. The Port within this AMC resource functions as Lane 2 of this AMC Channel.
9:5
Lane 1 Port Number. The Port within this AMC resource functions as Lane 1 of this AMC Channel.
4:0
Lane 0 Port Number. The Port within this AMC resource functions as Lane 0 of this AMC Channel.
¶ 15
Two AMC Channel Descriptors (Fat Pipe Channel, and Fat Pipe Extension Channel) are
defined below (see Table 8-5) to support all four AMC.1 “Types” (Types 1, 2, 4, and 8.) A
value of “31” is used to identify unused/undefined Lanes.
Table 8-5 AMC.1 Channel Descriptors
Lane Number
Port Number
Fat Pipe Channel: Supports AMC.1 Types 1, 2, 4 and 8
Lane 3 (Fat Pipe Lane 3)
7
Lane 2 (Fat Pipe Lane 2)
6
Lane 1 (Fat Pipe Lane 1)
5
Lane 0 (Fat Pipe Lane 0)
4
Fat Pipe Extension Channel: Supports AMC.1 Type 8 only
(Type 8 requires both the Fat Pipe Channel and Fat Pipe Extension Channel.)
¶ 16
Lane 3 (Fat Pipe Lane 7)
11
Lane 2 (Fat Pipe Lane 6)
10
Lane 1 (Fat Pipe Lane 5)
9
Lane 0 (Fat Pipe Lane 4)
8
A Port can only be defined/reserved once per AMC Point-to-Point Connectivity Record. As
such, the rationale for this approach includes:
• Reserve only those Ports that are needed when alternate uses are expected for unused
Ports.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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• Define a single AMC Channel to support multiple AMC.1 Types.
AMC.1 Types 1, 2 and 4 can later be defined/enabled by the AMC Link Designator field
of the AMC Link Descriptor category below. This approach makes the Record more
compact by requiring fewer overall fields.
• Reserve only those Ports needed to support Types 1 or 2, when alternate uses are
expected for the additional two or three Channel Ports.
It is acceptable to reserve all four Ports for Type 1 or Type 2 as long as there is no other
expected usage for the unused Ports. However, if Lanes 1 (with Type 1 only), 2, and 3
(Ports 5-7) are to be used as private Lanes or to support other AMC-defined functions
from other subsidiary specifications, then one would instead specify only the actual
Ports required to support the Type definition.
¶ 17
Table 8-5 provides the suggested records which provide for the most compact description but
this is not prescriptive. There is no prohibition or requirement for the reservation of unused
Lanes for AMC.1. Table 8-6 provides suggested records for Type 1 and 2 Channel
Descriptors which reserve only the used Ports for those Types.
Table 8-6 AMC.1 Channel Descriptors for Types 1 and 2 only
Lane Number
AMC Port Number
Fat Pipe Channel: Optimized for AMC.1 Type 2
Lane 3 Port Number
31
Lane 2 Port Number
31
Lane 1 Port Number
5
Lane 0 Port Number
4
Fat Pipe Channel: Optimized for AMC.1 Type 1
Lane 3 Port Number
31
Lane 2 Port Number
31
Lane 1 Port Number
31
Lane 0 Port Number
4
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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8.1.1.4
AMC Link Descriptors
¶ 18
AMC Link Descriptors define the Link(s) and the associated protocol for each Link. Each
AMC Channel may support multiple AMC Link Descriptor entries to indicate different
capabilities. An AMC Link Descriptor is 5 bytes in length and is described as a 40-bit entity.
The fields (or groups of fields) in Table 8-7 define an AMC Link Descriptor and will be
described in the following subsections.
Table 8-7 AMC Link Descriptor
Bits
39:34
33:32
Reserved. Must be 111111b.
AMC Asymmetric Match
Indicates asymmetric Port-matching information. (See Section 8.1.1.4.4)
31:24
Link Grouping ID
Indicates whether the Ports of this Channel are operated together with Ports in other
Channels. (See Section 8.1.1.4.5, “Link Grouping ID.” )
23:20
AMC Link Type Extension
Identifies the subset of a subsidiary specification that is implemented and is defined
entirely by the subsidiary specification identified in the Link Type field. (See
Section 8.1.1.4.3, “AMC Link Type Extensions.” )
19:12
AMC Link Type
Identifies the AMC.x subsidiary specification that governs this description or identifies
the description as proprietary. (See Section 8.1.1.4.2, “AMC Link Type.” )
11:0
8.1.1.4.1
Description
AMC Link Designator
Identifies the AMC Channel and the Ports within the AMC Channel that are being
described. (See Section 8.1.1.4.1, “AMC Link Designator.” )
AMC Link Designator
¶ 19
An AMC Link Designator field defines the subset of an AMC Channel’s Lanes that are
included in a Link and references the Channel Descriptor, which defines the binding to AMC
Connector Ports. Table 8-8 shows the defined fields in an AMC Link Designator.
Table 8-8 AMC Link Designator
Bits
Description
11
Lane 3 Bit Flag (1 = Lane Included; 0 = Lane Excluded)
10
Lane 2 Bit Flag (1 = Lane Included; 0 = Lane Excluded)
9
Lane 1 Bit Flag (1 = Lane Included; 0 = Lane Excluded)
8
Lane 0 Bit Flag (1 = Lane Included; 0 = Lane Excluded)
7:0
AMC Channel ID
Identifies an AMC Channel Descriptor defined in an AMC Point-to-Point
Connectivity Record.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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¶ 20
The AMC Channel ID references the index of the AMC Channel Descriptor that is being
described and binds the AMC Link Descriptor to a specific AMC Channel Descriptor. As
such, this value will be implementation specific and will depend on the location of the
associated AMC Channel Descriptor in the AMC Point to Point Connectivity Record.
¶ 21
The AMC Channel ID is the zero-based sequential index into the corresponding AMC
Channel Descriptor in a composite list combining the AMC Channel Descriptors from all the
AMC Point-to-Point Connectivity Records that occur in Module or Carrier FRU Information.
This list preserves the order of the groups of AMC Channel Descriptors to match the order of
the containing AM Point-to-Point Connectivity Records in FRU Information.
¶ 22
AMC Link Designators used in AMC.1 are defined in Table 8-9.(This is an example only,
showing reservation of only the required Lanes. Type 1 and Type 2 could choose to also
reserve unused Lanes.)
Table 8-9 AMC.1 Link Designators
Bit Flags
Channel
AMC
Lane 3
Lane 2
Lane 1
Lane 0
Channel ID
AMC.1 Type 1
0
0
0
1
Implementation
Specific
AMC.1 Type 2
0
0
1
1
Implementation
Specific
AMC.1 Type 4
1
1
1
1
Implementation
Specific
AMC.1 Type 8
1
1
1
1
Implementation
Specific
1
1
1
1
Implementation
Specific
Fat Pipe Channel
Fat Pipe Ext Channel
AMC.1 Type 8
¶ 23
Guidance was given in REQ 4.3a that an AdvancedMC Carrier support all legal sub-widths
of its maximum Link width. An AMC.1 Carrier indicates the widths that it supports by
defining multiple AMC Link Descriptors, one for each width, each with its AMC Link
Designator selecting a different subset of Lanes.
¶ 24
Guidance was given in REQ 4.4a that Modules support multiple Link widths. This is
accomplished by defining multiple AMC Link Descriptors each with a different AMC Link
Designator to indicate support for a particular sub-width. It is possible that the hardware on
the Module is capable of negotiating Link widths which are insufficient to support the needs
of the Module. The valid AMC Link Designators for a Module indicate only the widths that
the Module requires in order to operate properly, not what its hardware is capable of
negotiating. See the following examples:
Example 1: A Module requires a x4 Link width in order to function properly.
• When matched with a Carrier that supports x4, x2 and x1 Link widths, a x4 Link will be
established.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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• When matched with an On-Carrier device that supports x2 and x1 Link widths, a
Channel mismatch will be identified. This guarantees that the Module is matched with
only those Carriers that have the appropriate Link widths required.
Example 2: A Module accepts either a x2 or x4 Link width in order to function properly.
• When matched with an On-Carrier device that supports x2 and x1 Link widths, a x2
Link will be established. The Module is capable of operating with x4 but only requires
x2.
8.1.1.4.2
AMC Link Type
¶ 25
The AMC Link Type is a single-byte value used to specify the AMC subsidiary specification
supported. Typically, each AMC.0 subsidiary specification is assigned one AMC Link Type
value. Previously this specification defined two AMC Link Type values, however AMC Link
Type 3, associated with ASI, was removed in Revision 2.0 of this specification.
Requirements
8.1.1.4.3
REQ 8.2
AMC Link Descriptors for AMC.1 Carriers and Modules that indicate a PCI Express
AMC Link Type shall have an AMC Link Type value of “02h”.
REQ 8.3a
AMC Link Type 3 shall not be used. AMC Link Type 3, previously assigned to ASI, was
removed in Revision 2.0 of this specification.
AMC Link Type Extensions
¶ 26
The AMC Link Type Extension enables Modules and Carriers to claim compliance to multiple
variations and options within a given protocol (or AMC Link Type). Its initial use within
AMC.1 is to distinguish between Gen1-capable (2.5 GT/s) and Gen-2 capable (5 GT/s)
implementations of PCI Express (see Table 8-10). AMC Link Type Extension parameters
(Link Ext. Number) are identical for both AMC.1 Modules and Carriers.
Table 8-10 PCI Express (Link Type 02h) - AMC Link Type Extensions
Link Ext
Number
Description
0000b
This is a Gen 1-capable PCI Express Module or Carrier.
It is capable of normal operation when SSC is not enabled on FCLKA
0001b
This is a Gen 1-capable PCI Express Module or Carrier.
It is capable of normal operation when SSC is enabled on FCLKA
0010b
This is a Gen 2-capable PCI Express Module or Carrier.
It is capable of normal operation when SSC is not enabled on FCLKA
0011b
This is a Gen 2-capable PCI Express Module or Carrier.
It is capable of normal operation when SSC is enabled on FCLKA
0100b thru 1111b
<Reserved for future growth>
* Note: The capability mentioned in Table 8-10 is about a Module or Carrier being able or
not to use SSC is not an indication of the actual status of SSC. The actual status of
SSC is decided by a mechanism outside the scope of this specification.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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¶ 27
Only one AMC Link Type Extension may be defined within an AMC Link Descriptor.
Therefore, in order to support multiple variations, additional AMC Link Descriptors are
required. E-Keying requires an exact match to be found among the AMC Link Type Extension
values listed by the two peers sharing a Link (i.e. Module-to-Carrier and Module-toModule.)
Requirements
8.1.1.4.4
REQ 8.4
An AMC.1 Module and Carrier shall support the AMC.1 Link Type Extensions as
defined in Table 8-10 which appropriately describe that device's capabilities.
REQ 8.19
When a Module MMC or Carrier IPM Controller receives a “Set AMC Port State
(Enable)” command with a Link Type Extension that does not match its current SSC
capabilities, it should respond with a “Not supported in present state (D5h)” Completion
Code.
REQ 8.20
When a Carrier IPM Controller receives a “Not supported in present state (D5h)”
Completion Code in response to a “Set AMC Port State (Enable)” command, it should
continue through additional AMC Link Descriptors for the next matching pair.
Asymmetric Match
¶ 28
The Asymmetric Match field enables matching of asymmetric peers independent of their
location on a Module or Carrier. This is an important feature for PCI Express, since there are
certain Link partner relationships (e.g. Primary/Secondary, Upstream/Downstream) where an
exact match would require compatible devices to represent different capabilities with the
same code. Without this Asymmetric Match field, it would be impossible to define a single
Module that could support Link partner relationships in both Module-to-Module and
Module-to-Carrier configurations.
¶ 29
If the combination of AMC Link Designator, AMC Link Type, and AMC Link Type
Extensions form an exact match, the Asymmetric Match field is further compared for
compatibility. Section 8-11 defines the values that are used in this field.
Table 8-11 AMC Link Descriptor Asymmetric Match Field Values
Value
¶ 30
Definition
00b
Matches with '00b' (identical)
01b
Matches with ‘10b’ (complementary)
10b
Matches with ‘01b’ (complementary)
11b
Undefined
AMC.1 Asymmetric Match (Match Ext. Number) are identical for both AMC.1 Modules and
Carriers. This mechanism is used to determine a match between a Primary Port and a
Secondary Port (see Table 8-12.) A Module or Carrier which is capable of both modes
indicates this by expressing multiple PCI Express Link Descriptors that are identical except
for the Asymmetric Match field. Higher-level software can detect this and deduce that the
Module or Carrier supports a configurable Non-Transparent Bridge.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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Table 8-12 PCI Express (02h) - AMC Asymmetric Match Field
Match Ext Number
Description
Deprecated
00b
Formerly: Advanced Switching utilizes exact match to determine
compatibility
01b
This Module or Carrier provides a Primary Port
10b
This Module or Carrier provides a Secondary Port
Requirements
REQ 8.5a
8.1.1.4.5
An AMC.1 Module or Carrier shall support the AMC.1 Asymmetric Match as defined in
Table 8-12.
Link Grouping ID
¶ 31
Link Grouping ID indicates whether the Ports of this Channel are operated together with
Ports in other Channels. A value of 0 always indicates a Single-Channel Link. A common,
non-zero Link Grouping ID in multiple AMC Link Descriptors indicates that the Ports
covered by those AMC Link Descriptors must be operated together. A unique non-zero Link
Grouping ID also indicates a Single-Channel Link.
¶ 32
Since AMC.1 Types 1, 2 and 4 each require a single Channel, the associated Link Grouping
ID will equal 0 (or unique non-zero value.) AMC.1 Type 8 requires two Channels so a
common non-zero Link Grouping ID must be used in each Link Grouping ID to identify their
relationship.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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8.1.1.4.6
Summary of AMC.1 Link Descriptors
¶ 33
Table 8-13
Table 8-13 summarizes AMC.1 E-Keying information for Modules. AMC.1 Carrier
definitions are the same with the exception of Record Type bit within the Resource ID, which
has a value of “0”.
Example E-Keying Configurations for Modules of Type 1, 2, and 4
AMC.1 Type 1
AMC.1 Type 2
AMC.1 Type 4
Record Type
1
1
1
AMC Channel Descriptor Count
1*
1*
1*
Lane 3 Port Number
31
31
7
Lane 2 Port Number
31
31
6
Lane 1 Port Number
31
5
5
Lane 0 Port Number
4
4
4
0
0
0
AMC Channel Descriptor
AMC Link Descriptor
AMC Link Grouping ID
AMC Link Type Extensions
Implementation Specific
AMC Asymmetric Match
Implementation Specific
AMC Link Type
02h
02h
02h
Lane 3 Bit Flag
0
0
1
Lane 2 Bit Flag
0
0
1
Lane 1 Bit Flag
0
1
1
Lane 0 Bit Flag
1
1
1
AMC Link Designators
AMC Channel ID
Implementation Specific
NOTE: * The total AMC Channel Descriptor Count is implementation specific. The value shown in
this example reflects only this one Channel Descriptor.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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Table 8-14 Example E-Keying Configurations for Type 8 Modules
AMC.1 Type 8
Fabric Channel 1
Fabric Channel 2
Record Type
1
1
AMC Channel Descriptor Count
1*
1*
Lane 3 Port Number
7
11
Lane 2 Port Number
6
10
Lane 1 Port Number
5
9
Lane 0 Port Number
4
8
AMC Channel Descriptor
AMC Link Descriptor
AMC Link Grouping ID
<common unique non-zero value>
AMC Link Type Extensions
Implementation Specific, matches between Fabric Channels 1 & 2
AMC Asymmetric Match
Implementation Specific, matches between Fabric Channels 1 & 2
AMC Link Type
02h
02h
Lane 3 Bit Flag
1
1
Lane 2 Bit Flag
1
1
Lane 1 Bit Flag
1
1
Lane 0 Bit Flag
1
1
Implementation Specific
Implementation Specific
AMC Link Designators
AMC Channel ID
NOTE: * The total AMC Channel Descriptor Count is implementation-specific. The value shown in
this example reflects only this one Channel Descriptor.
8.1.2
Carrier Point-to-Point Connectivity Record
¶ 34
It is important to note that in addition to the AMC Point-to-Point Connectivity Record,
another “Record” is also included in the AdvancedMC Carrier FRU Information for EKeying definition. This additional record, called the Carrier Point-to-Point Connectivity
Record, establishes a Link between Ports on an On-Carrier device and Ports on a Module. It
is used to define the Port relationships for both Carrier-to-Module and Module-to-Module
implementations. Since this additional record does not contain AMC.1 specific definitions, it
is left to the reader to reference this information in AMC.0 Section 3.9.2.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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8.2
AMC Clock E-Keying
¶ 35
8.2.1
The following sections provide details related to the various aspects of AMC.1 clock EKeying.
AMC Direct Clock Descriptors
¶ 36
Table 8-15
The capabilities of an AdvancedMC Module to source or receive a PCI Express reference
clock are described in the “Direct Clock Descriptors” (defined in AMC.0 R2.0 Section
3.9.2.3, Table 3-38) contained within the “Clock Configuration Record.” This record is
included in both the AdvancedMC Module and AdvancedMC Carrier FRU Information.
Table 8-15 identifies a subset of the Direct Clock Descriptor fields that are directly
applicable to this AMC.1 subsidiary specification and the values to be used for FCLKA EKey records. Additional fields further defined in this Descriptor include PLL Connection and
Asymmetrical Match.
AMC.1 Applicable fields of an AMC.0 “Direct Clock Descriptor”
Direct Clock Descriptor Field Name
Clock Family
02h – PCI Express
Clock Accuracy level
E0h – PCI Express Generation 2
F0h – PCI Express Generation 1
Clock Frequency
100,000,000 Decimal (05F5E100 Hex)
Minimum Clock Frequency
100,000,000 Decimal (05F5E100 Hex)
Maximum Clock Frequency
100,000,000 Decimal (05F5E100 Hex)
REQ 8.17
8.2.2
Definition
AMC.1 Modules and Carriers shall use the values defined in Table 8-15 for the
specified fields.
FCLK Source
¶ 37
The PCI Express reference clock is provided on the FCLKA pins. FCLKA can be sourced
from either the Carrier or a Root Complex Module.
¶ 38
Many Root Complex devices use the PCI Express reference clock for other functions in
addition to PCI Express. For this reason, it is important that once established, the reference
clock remains stable to the Root Complex and cannot change directions.
¶ 39
Additionally, PCI Express peripherals must hold PERST# active until after the reference
clock is stable. For this reason, the clock source must be stable within a known time relative
to E-Keying. Typically, E-Keying for the FCLKA source involves the IPM Controller
controlling an “enable” signal to a clock buffer.
¶ 40
Typically, an AdvancedMC Module is not able to source FCLKA until Payload Power is
enabled and stable. For some Module designs, this might involve sequencing several onboard power converters. If the module is commanded to enable FCLKA as the source, but is
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
8-13
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
not yet ready to source FCLKA, the Module responds to the Set Clock State (Enable)
command with a “Node Busy (C0h)” Completion Code. In this case, the Carrier IPM
Controller is expected to retry the command after a short delay.
Requirements
8.3
REQ 8.6
The Carrier IPM Controller shall not enable FCLKA as a source from an AdvancedMC
that is providing a Primary Port.
REQ 8.7
When FCLKA is enabled to be sourced by a Carrier to an AdvancedMC Slot, the Carrier
IPM Controller shall not disable FCLKA to that AdvancedMC Slot until either that
AdvancedMC transitions to the M0, M1 or M2 state or the Carrier IPM Controller
receives a “Set Clock State” command to disable the clock.
REQ 8.8
Once FCLKA is enabled for output from a Module, the Carrier IPM Controller shall not
enable FCLKA on this Module for input unless the Module has transitioned through the
M1 state.
REQ 8.18
Once a Carrier IPM Controller disables FCLKA for both input and output via clock Ekeying commands for a Module configured to provide a Secondary Port, the Carrier IPM
Controller shall not enable FCLKA on this Module for input until the Module has
transitioned through the M1 state.
REQ 8.9
The Carrier IPM Controller shall enable the FCLKA source prior to enabling the
FCLKA receiver. The Carrier IPM Controller shall wait until receiving a “Command
Complete Normal (00h)” Completion Code in the response to the Set Clock State
(Enable) command from the clock source before sending the Set Clock State (Enable)
command to the clock receiver.
REQ 8.10
An FCLKA source shall be stable before sending a successful response to the
corresponding Set Clock State (Enable) command.
REQ 8.21
If a Module is not ready to source FCLKA when it receives a Set Clock State (Enable) to
enable sourcing FCLKA, the Module shall respond with a “Node Busy (C0h)”
Completion Code.
REQ 8.11
Modules shall not drive FCLKA contacts unless explicitly enabled to do so via EKeying.
PCI Express Interface Types
¶ 41
There are two types of PCI Express Ports: Primary Ports and Secondary Ports. Peripheral
devices implement a Primary Port. Root Complex devices implement a Secondary Port. PCI
Express switches implement one Primary Port per supported root and multiple Secondary
Ports.
Requirements
REQ 8.12
For PCI Express Ports that are capable of being configured through E-Keying as either a
Primary Port or a Secondary Port, once the interface has been enabled for one direction,
the Carrier IPM Controller should avoid changing the direction via subsequent E-Keying
activity, unless that Module or Carrier has subsequent transitions through the M1 state.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
8-14
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
8.3.1
Primary PCI Express interfaces
¶ 42
PCI Express devices which implement a Primary Port to the AMC Connector must have
PERST# asserted low until after the reference clock is stable. Because there is no PERST#
signal defined on the AdvancedMC Connector, Carriers and Modules are responsible for
generating their own local PERST#. This can be achieved by using either a hardware clock
detection circuit or based on E-Keying.
Requirements
8.3.2
REQ 8.13
Carriers and Modules which implement a Primary Port may generate a PERST# to the
Primary Port device based on a clock detection circuit and the PCI Express interface
having been enabled via E-Keying.
REQ 8.14
Carriers and Modules which implement a Primary Port that do not have a clock detection
circuit shall not de-assert PERST# to the Primary Port device until Payload Power is
good, FCLKA is enabled via clock E-Keying for at least 100 microseconds, and the PCI
Express interface has been enabled via E-Keying.
REQ 8.22
Carriers and Modules which implement a Primary Port shall assert PERST# to the
Primary Port device when either FCLKA is disabled via clock E-Keying, the PCI
Express interface has been disabled via E-Keying, or Payload Power is not good.
REQ 8.23
Carrier IPM Controllers should retry Set Clock State commands if they receive a “Node
Busy (C0h)” Completion Code.
Secondary PCI Express Interfaces
¶ 43
PCI Express Root Complexes implement a Secondary Port. Some Root Complex devices use
the PCI Express reference clock for other functions in addition to the PCI Express reference.
For this reason, the PCI Express reference clock might need to be established before the Root
Complex can be allowed to boot up. Additionally, the AdvancedMC connector interface does
not implement control and status signals specifically for Hot Plug Controllers. For some
designs, it might be beneficial for the IPM Controller to manipulate signals to a Hot Plug
controller in order to enable standard Hot Plug software to detect insertions and extractions
of Modules. A future revision of this specification might include details related to mapping
Hot Plug into the AMC environment.
Requirements
REQ 8.15
Modules and Carriers that provide a Secondary Port may remain in reset until after
FCLKA has been enabled via clock E-Keying, Payload Power is good, and the PCI
Express interface has been enabled via E-Keying.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
8-15
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
8-16
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
A AMC.0 Pin Assignments
Table A-1 AdvancedMC Module Edge Connector Pin Assignments
AMC Module Edge Connector Pin Assignment
Basic Side
(Component Side 1)
Pin No. Signal
84
83
81
80
78
77
75
74
72
71
69
68
66
65
63
62
60
59
57
56
54
53
51
50
48
47
45
44
42
41
39
38
36
35
33
32
30
29
27
26
24
23
21
20
18
17
15
14
12
11
9
8
6
5
4
3
2
Driven by
PWR
PS0#
FCLKAFCLKA+
TCLKBTCLKB+
TCLKATCLKA+
PWR
SDA_L
Rx7Rx7+
Tx7Tx7+
Rx6Rx6+
Tx6Tx6+
PWR
SCL_L
Rx5Rx5+
Tx5Tx5+
Rx4Rx4+
Tx4Tx4+
PWR
ENABLE#
Rx3Rx3+
Tx3Tx3+
Rx2Rx2+
Tx2Tx2+
PWR
GA2
Rx1Rx1+
Tx1Tx1+
PWR
GA1
Rx0Rx0+
Tx0Tx0+
PWR
RSRVD8
RSRVD6
GA0
MP
PS1#
PWR
Carrier
Carrier
FCLKA
driver
TCLKB
driver
TCLKA
driver
Carrier
IPMI Agent
Mating
First
Last
Third
Third
Third
Third
Third
Third
First
Second
Third
Carrier
Third
Third
AMC
Third
Third
Carrier
Third
Third
AMC
Third
Carrier First
IPMI Agent Second
Third
Carrier
Third
Third
AMC
Third
Third
Carrier
Third
Third
AMC
Third
Carrier First
Carrier Second
Third
Carrier
Third
Third
AMC
Third
Third
Carrier
Third
Third
AMC
Third
Carrier First
Carrier Second
Third
Carrier
Third
Third
AMC
Third
Carrier First
Carrier Second
Third
Carrier
Third
Third
AMC
Third
Carrier First
Second
Second
Carrier Second
Carrier First
AMC
Last
Carrier First
Basic Side
(Component Side 1)
Pin Function on the AMC
Payload Power
Presence 0
Fabric Clock A Fabric Clock A +
Telecom Clock B Telecom Clock B +
Telecom Clock A Telecom Clock A +
Payload Power
IPMB-L Data
Port 7 Receiver Port 7 Receiver +
Port 7 Transmitter Port 7 Transmitter +
Port 6 Receiver Port 6 Receiver +
Port 6 Transmitter Port 6 Transmitter +
Payload Power
IPMB-L Clock
Port 5 Receiver Port 5 Receiver +
Port 5 Transmitter Port 5 Transmitter +
Port 4 Receiver Port 4 Receiver +
Port 4 Transmitter Port 4 Transmitter +
Payload Power
AMC Enable
Port 3 Receiver Port 3 Receiver +
Port 3 Transmitter Port 3 Transmitter +
Port 2 Receiver Port 2 Receiver +
Port 2 Transmitter Port 2 Transmitter +
Payload Power
Geographic Addr. 2
Port 1 Receiver Port 1 Receiver +
Port 1 Transmitter Port 1 Transmitter +
Payload Power
Geographic Addr. 1
Port 0 Receiver Port 0 Receiver +
Port 0 Transmitter Port 0 Transmitter +
Payload Power
Reserved, not connected
Reserved, not connected
Geographic Addr. 0
Management Power
Presence 1
Payload Power
Pin No. Signal
87
88
90
91
93
94
96
97
99
100
102
103
105
106
108
109
111
112
114
115
117
118
120
121
123
124
126
127
129
130
132
133
135
136
138
139
141
142
144
145
147
148
150
151
153
154
156
157
159
160
162
163
165
166
167
168
169
Rx8Rx8+
Tx8Tx8+
Rx9Rx9+
Tx9Tx9+
Rx10Rx10+
Tx10Tx10+
Rx11Rx11+
Tx11Tx11+
Rx12Rx12+
Tx12Tx12+
Rx13Rx13+
Tx13Tx13+
Rx14Rx14+
Tx14Tx14+
Rx15Rx15+
Tx15Tx15+
TCLKCTCLKC+
TCLKDTCLKD+
Rx17Rx17+
Tx17Tx17+
Rx18Rx18+
Tx18Tx18+
Rx19Rx19+
Tx19Tx19+
Rx20Rx20+
Tx20Tx20+
TCK
TMS
TRST#
TDO
TDI
Driven by
Carrier
AMC
Carrier
AMC
Carrier
AMC
Carrier
AMC
Carrier
AMC
Carrier
AMC
Carrier
AMC
Carrier
AMC
TCLKC
Driver
TCLKD
Driver
Carrier
AMC
Carrier
AMC
Carrier
AMC
Carrier
AMC
Carrier
Carrier
Carrier
AMC
Carrier
Mating
Pin Function on the AMC
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Third
Second
Second
Second
Second
Second
Port 8 Receiver Port 8 Receiver +
Port 8 Transmitter Port 8 Transmitter +
Port 9 Receiver Port 9 Receiver +
Port 9 Transmitter Port 9 Transmitter +
Port 10 Receiver Port 10 Receiver +
Port 10 Transmitter Port 10 Transmitter +
Port 11 Receiver Port 11 Receiver +
Port 11 Transmitter Port 11 Transmitter +
Port 12 Receiver Port 12 Receiver +
Port 12 Transmitter Port 12 Transmitter +
Port 13 Receiver Port 13 Receiver +
Port 13 Transmitter Port 13 Transmitter +
Port 14 Receiver Port 14 Receiver +
Port 14 Transmitter Port 14 Transmitter +
Port 15 Receiver Port 15 Receiver +
Port 15 Transmitter Port 15 Transmitter +
Telecom Clock C Telecom Clock C +
Telecom Clock D Telecom Clock D +
Port 17 Receiver Port 17 Receiver +
Port 17 Transmitter Port 17 Transmitter +
Port 18 Receiver Port 18 Receiver +
Port 18 Transmitter Port 18 Transmitter +
Port 19 Receiver Port 19 Receiver +
Port 19 Transmitter Port 19 Transmitter +
Port 20 Receiver Port 20 Receiver +
Port 20 Transmitter Port 20 Transmitter +
JTAG Test Clock Input
JTAG Test Mode Select In
JTAG Test Reset Input
JTAG Test Data Output
JTAG Test Data Input
L e g e n d to th e c o lo r s u s e d in th e s ig n a l m a p p in g ta b le s
PW R
MP
1 2 V P a y lo a d P o w e r
F a b r ic In t e r f a c e d if f e r e n t ia l s ig n a l
3 .3 V M a n a g e m n e n t P o w e r
C lo c k In t e r f a c e d if f e r e n t ia l s ig n a l
G N D p in s r e m o v e d fr o m t h e p in c h a r t fo r c la r ity
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
A-1
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This page left blank intentionally.
A-2
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
B Carrier Topologies (Informative)
B.1
¶1
This appendix provides some example topologies for AMC.1 Carrier boards in order to
illustrate the kinds of systems in which AMC.1 Modules might be installed and to explain the
motivation for the configuration parameters defined herein. These topologies are provided
for illustration only and do not create or imply rules or limitations for Carrier boards.
¶2
All Carriers are described from a Module perspective; as there are many aspects of a Carrier
which are not visible to a Module, nor do they affect how the Module and Carrier connect,
such aspects are not addressed except in broad terms. All diagrams show eight PICMG®
AMC.1 Slots on a Carrier. In practice a Carrier could have more or fewer AMC.1 Slots, and
may also support other AMC.xx or other mezzanine types. AMC.0 limits a PICMG 3.0
Carrier to 8 Single Compact Modules maximum.
Basic PCI-E I/O Carrier, or With RC on the Carrier
¶3
Each Module provides a Primary Port. Root Complex could be remote on another blade or
local on this Carrier Board. The backplane fabric as shown is PCI Express, although it could
be another medium, which can carry PCI Express to a remote host. If the Root Complex is on
the Carrier Board the domain of this PCI Express hierarchy might be limited to being local to
the Carrier Board, or that Root Complex may be able to access remote End Nodes over the
backplane fabric, which might be native PCI Express or some other fabric carrying tunneled
PCI Express.
Figure B-1 Basic I/O Carrier
Backplane
PCI Express Switch
S
P
AMC.1
Module
(PCI-E)
P
AMC.1
Module
(PCI-E)
S
P
AMC.1
Module
(PCI-E)
S
S
S
P
AMC.1
Module
(PCI-E)
S
S
P
AMC.1
Module
(PCI-E)
S
P
AMC.1
Module
(PCI-E)
P
P
AMC.1
Module
(PCI-E)
AMC.1
Module
(PCI-E)
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
B-1
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
B.2
PCI-E Carrier Which Supports an RC on a Module
¶4
This is similar to the basic PCI Express Carrier example, but shows a Carrier with one Slot
which is either hardwired or optionally an Upstream Slot which supports a Module
containing a PCI Express Root Complex and which provides the host for that PCI Express
hierarchy.
Figure B-2 PCI-E Carrier with an RC on a Module
Backplane
PCI Express Switch
P
S
P
AMC.1
Module
(PCI-E)
Root
Complex
B.3
AMC.1
Module
(PCI-E)
S
P
AMC.1
Module
(PCI-E)
S
S
P
AMC.1
Module
(PCI-E)
S
S
S
P
AMC.1
Module
(PCI-E)
s
P
AMC.1
Module
(PCI-E)
P
AMC.1
Module
(PCI-E)
P
AMC.1
Module
(PCI-E)
PCI-E Carrier Which Supports Primary and
Secondary RC With NTB and Failover Support
¶5
As with the previous example, this Carrier has a Slot which is designated for a (possibly
optional) processor Module providing the Root Complex for the PCI Express hierarchy. In
addition this Carrier supports an optional Second Processor Module in a different designated
Slot, and the ability to migrate “RC” to the switch Port connected to the Secondary Processor
Module in support of failover for high availability. Each NTB in Figure B-3 is actually a
dual-mode bridge which can be transparent (supporting a Root Complex) or non-transparent.
The mechanisms required for failover and the non-transparent bridging support needed for
this function are beyond the scope of AMC.1.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
B-2
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
Figure B-3 PCI-E Carrier with support for dual hosts
Backplane
P = Primary Port
S = Secondary Port
PH= Primary Host Link
SH = Secondary Host Link
NTB = Non Transparent
Bridge
PCI-E Switch
Primary
NTB
P
PH
S
CPU &
Root
Cmplx
Secondary
NTB
P
S
S
S
S
S
S
SH
S
CPU &
Root
Cmplx
P
AMC.1
Module
(PCI-E)
P
AMC.1
Module
(PCI-E)
P
AMC.1
Module
(PCI-E)
P
AMC.1
Module
(PCI-E)
P
AMC.1
Module
(PCI-E)
P
AMC.1
Module
(PCI-E)
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
B-3
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
B.4
Carrier populated with NTB-isolated RC Modules
creating a compute farm
¶6
The Modules shown have a local NTB which isolates their RC’s domain to the Module and
presents an End Node (Primary Port) to the Carrier Slot.
Figure B-4 PCI-E Carrier populated with isolated RCs creating a compute farm
Backplane
PCI Express Switch
P
S
AMC.1
Module
(PCI-E)
Root
Complex
S
P
NTB
P
NTB
AMC.1
Module
(PCI-E)
AMC.1
Module
(PCI-E)
S
S
P
NTB
AMC.1
Module
(PCI-E)
S
S
S
s
P
NTB
P
NTB
P
NTB
AMC.1
Module
(PCI-E)
AMC.1
Module
(PCI-E)
AMC.1
Module
(PCI-E)
P
NTB
AMC.1
Module
(PCI-E)
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
B-4
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
C Signal Integrity Analysis
C.1
Signal Integrity Analysis Overview
¶1
This section discusses the signal integrity analyses performed for AMC.1 transmitter/
receiver configurations using typical Module, Carrier and MicroTCA backplane models. It is
intended to show that the AMC.1 estimated channel lengths will yield acceptable PCI
Express Links performance at 2.5 GT/s and 5 GT/s with the presence of a 0.68µF to 1µF
receiver-side AC coupling capacitor.
¶2
At 2.5GT/s, these simulations characterize PCI Express serial Link performance using PCI
Express compatible HSPICE models with nominal, fast and slow process tolerances. To
characterize interconnect response at 5GT/s passive frequency-domain analysis was
performed with no active driver model.
¶3
At both 2.5GT/s and 5GT/s interconnect was modeled using AdvancedTCA and MicroTCA
compliant connectors. Tolerances for interconnect parameters (differential impedances, trace
widths, voltage and temperature) were also modeled as part of the simulation effort.
¶4
At 2.5GT/s three simulation cases were investigated. The first case models a link between
two AdvancedMC Modules in a MicroTCA environment (Module-Backplane-Module). The
second models the link between two modules in an AdvancedTCA Carrier (Module-CarrierModule). The third models a link between a module and AdvancedTCA carrier (ModuleCarrier). At 5GT/s the module-carrier-module case was investigated as a passive interconnect
model only.
¶5
These simulations do not attempt to validate all possible PCI Express driver and interconnect
combinations. Rather, the intent is to confirm that adequate margin is achievable with the
longest link lengths and a receiver-side AC coupling capacitor.
¶6
This section includes an overview of the signal integrity analysis. The complete reports are
available in the “Members only” section of the PICMG website (www.picmg.org).
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
C-1
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
C.1.1
Modeling Parameters
Table C-1describes the assumptions and parameters used for AdvancedMC module, ATCA
carrier and MicroTCA backplane models.
Table C-1 Modeling Parameters
¶7
Parameter
Description
PCB Material
FR-4
Dielectric constant
r
4.2
Loss Tangent (tan X)
0.021
PCB Trace Details
Module: 0.09mm internal, 0.10mm external Carrier
Backplane: 0.10mm
Capacitors
Case size: 1.6mm x0.x, (EIA 0603)
Dielectric: X7R
Values: 0x01µF, 0.68uF, 1.0µF
¶8
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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C.1.2
Module Stackup and Via Details
¶9
The Module vias are based on a 18 layer “typical” stackup as shown in Figure C-1. The
model used for the BGA via has a 0.15 mm finished hole diameter with a 0.46 mm pad and
0.74 mm anti-pad. Ground vias are placed at a distance of 1mm from each BGA via. The
model used for the capacitor via has a 0.20 mm finished hole diameter with a 0.51 mm pad
and 0.81 mm anti-pad. All non-functional pads were deleted. For 2.5GT/s simulations the
vias model a worst-case interconnect stub that connects between layers 1 and 4. The 5GT/s
simulations minimize the via stub by connecting on layers 1 and 15.
Figure C-1 AdvancedMC Module Stackup
¶ 18-Layer
1.6mm (0.063”) Nominal Thickness
1
2
2.5Gbps via connects here
3
4
5
6
5Gbps via connects here
7
8
9
10
11
12
13
14
15
16
17
18
0.074mm
0.076mm
0.071mm
0.076mm
0.074mm
0.064mm
0.074mm
0.064mm
0.074mm
0.064mm
0.074mm
0.064mm
0.074mm
0.076mm
0.071mm
0.076mm
0.074mm
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
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C.1.3
Carrier Stackup and Via Details
¶1
The carrier vias are based on a 20 layer “typical” stackup as shown inFigure C-2. The model
used for the via has a 0.20 mm finished hole diameter with a 0.51 mm pad and 0.81 mm antipad. Ground vias are placed at a distance of 1.4mm from each signal via. All non-functional
pads were deleted. For 2.5GT/s simulations, the vias model a worst-case interconnect stub
that connects between layers 1 and 4. The 5GT/s simulations minimize the via stub by
connecting on layers 1 and 17.
Figure C-2 ATCA Carrier Stackup
¶ 18-Layer
2.4mm (0.095”) Nominal Thickness
1
2.5Gbps via connects here
2
3
4
5
6
7
5Gbps via connects here
8
9
10
11
12
13
14
15
16
17
18
19
20
0.076mm
0.076mm
0.102mm
0.102mm
0.076mm
0.140mm
0.140mm
0.140mm
0.140mm
0.076mm
0.140mm
0.140mm
0.140mm
0.140mm
0.102mm
0.102mm
0.102mm
0.076mm
0.076mm
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
C-4
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C.1.4
Backplane Stackup and Via Details
¶1
The backplane vias are based on a 16 layer “typical” stackup as shown in Figure C-3. The
model used for the via has a 0.25 mm finished hole diameter with a 0.61mm pad and 0.86
mm anti-pad. Ground vias are placed at a distance of 0.9mm from each signal via. All nonfunctional pads were deleted. For 2.5GT/s simulations the vias model a worst-case
interconnect stub that connects between layers 1 and 3. The backplane models are not used in
the 5GT/s simulations.
Figure C-3 MicroTCA Backplane Stackup
¶16-Layer
3.0mm (0.118”) Nominal Thickness
1
2.5Gbps via connects here
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0.178mm
0.178mm
0.178mm
0.178mm
0.178mm
0.127mm
0.127mm
0.127mm
0.127mm
0.127mm
0.178mm
0.178mm
0.178mm
0.178mm
0.178mm
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
C-5
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
C.2
C.2.1
Signal Integrity Analysis Overview
¶1
At 2.5GT/s three simulation cases were investigated: module-backplane-module,
module-carrier-module, and module-carrier. The module-carrier analysis was further divided
into module drive and carrier drive cases.
¶2
At 5GT/s the module-carrier-module case was investigated as a passive interconnect model
only.
Module to Backplane to Module Serial Link
¶3
The module-backplane-module serial link is shown schematically in Figure C-4. The link is a
total of 61cm (24”) from transmitter to receiver. The transmit and receive 0603 capacitors are
located 6.9cm (2.7”) from the transmitter and receiver respectively. The receive-side
capacitor was simulated at 0.68µf and 1.0µF. As a reference, the link was also simulated with
no receive-side capacitor.
Figure C-4 Module-Backplane-Module Model
Simulate with CRX = 0.68 μF, 1.0μF and with no cap.
For no cap, eliminate cap launch and bring the
capacitor
via to
internal trace to the surface with the blue
via to
connect to the 0.3 μstrip
”
Microstrip
(4 mil traces)
3.5 mil traces
Module
4 mil traces
Backplane
3.5 mil traces
Module
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
C-6
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
C.2.2
Module to Carrier to Module Serial Link
¶1
The module-backplane-module serial link is shown schematically in Figure C-4. The link is a
total of 46cm (18”) from transmitter to receiver. The transmit and receive 0603 capacitors are
located 6.9cm (2.7”old) from the transmitter and receiver respectively. The receive-side
capacitor was simulated at 0.68µf and 1.0µF. As a reference, the link was also simulated with
no receive-side capacitor.
Figure C-5 Module-Carrier-Module Model
Simulate with CRX= 0.68μF, 1.0μ F and with no cap.
For no cap, eliminate cap launch and bring the
via to
internal trace to the surface with the capacitor
blue via to
connect to the 0.3” μ strip
3.5 mil traces
Module
4 mil traces
Carrier
3.5 mil traces
Module
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
C-7
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
C.2.3
Module to Carrier Serial Link
¶1
The module-backplane-module serial link is shown schematically in figure C-4. The link is a
total of 30cm (12”) from transmitter to receiver. In a simulation of the Carrier to Module
reverse direction the net was driven back from the carrier in the same configuration, with the
transmit and receive capacitors switching locations. The receive-side capacitor was
simulated at 0.68µf and 1.0µF. As a reference, the link was also simulated with no receiveside capacitor.
Figure C-6 Module-Carrier Model
Driven in Both Directions
Simulate with CRX= 0.68 μF, 1.0μ F and with no cap.
For no cap, eliminate cap launch and bring the
capacitor
via to
internal trace to the surface with the blue
via to
connect to the 0.3”μ strip
Microstrip (4 mil traces)
Microstrip (4 mil traces )
C-8
3.5 mil traces
4 mil traces
Module
Carrier
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
C.2.4
2.5GT/s Representative Eye Patterns
¶1
All circuit traces included frequency dependent losses and were modeled by converting the
output from the Ansoft HFSS field solver to an H-SPICE compatible table model file format.
Via pair models and cap launches were generated in Ansoft HFSS version 10. The pulse
pattern consists of 2E7 PRBS encoded data. The resulting receiver waveform data was then
plotted as an “eye diagram” from which the minimum eye openings and peak deterministic
jitter were measured. The minimum PCI Express eye mask was overlaid on all receiver plots.
The results for Crx=0.68µF are nearly identical to Crx=1.0µF.
Figure C-7 Module to Backplane to Module, Crx = 1.0µF at 2.5GT/s
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
C-9
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
Figure C-8 Module to Backplane to Module, No Crx at 2.5GT/s
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
C-10
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
Figure C-9 Module to Carrier to Module, Crx = 1.0µF at 2.5GT/s
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
C-11
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
Figure C-10 Module to Carrier to Module, No Crx at 2.5GT/s
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
C-12
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
Figure C-11 Carrier to Module, Crx = 1.0µF at 2.5GT/s
Driven from Carrier
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
C-13
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
Figure C-12 Carrier to Module, No Crx at 2.5GT/s
Driven from Carrier
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
C-14
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
Figure C-13 Module to Carrier, Crx = 1.0µF at 2.5GT/s
Driven from Module
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
C-15
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
Figure C-14 Module to Carrier, No Crx at 2.5GT/s
Driven from Module
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
C-16
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
C.2.5
5GT/s Insertion Loss, Return Loss and Impulse Response
¶1
Plots of the channel insertion loss (SDD21), return loss (SDD11) and impulse response are
shown, specifically focusing on 2.5 GHz, the fundamental frequency for a 5 GT/s bandwidth.
¶2
The capacitor launches and associated via models were created in Ansoft HFSS version 10.
The launches were optimized and via stubs minimized to represent a realistic, well designed
5 GT/s implementation.
¶3
The insertion loss for the entire channel is shown in Figure C-15. With the optimized vias
and cap launch, it is virtually the same with and without the caps. Note that at the 2.5 GHz
fundamental frequency of a 5GT/s PCI Express link the loss is about -11.0 dB.
Figure C-15 Module to Carrier to Module Insertion Loss
-11 dB insertion loss at 2.5 GHz
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
C-17
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
¶1
Figure C-16 shows the return loss of the channel with and without the RX caps. The return
loss is better than 12 dB for the entire frequency range.
Figure C-16 Module to Carrier to Module Return Loss
¶2
The impulse response of the channel with Crx = 1µF is shown in Figure C-17. The impulse
response measures how long energy will continue propagate in the system before it damps
out. For the module-carrier-module channel with a 1UI pulse input, the energy is
significantly damped within 3UI. The tail shows the desired smooth response. The response
curve for Crx = 0.68µF and Crx = 0 are nearly identical.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
C-18
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
Figure C-17 Module to Carrier to Module Impulse response, Crx = 1.0µF
Smooth tail indicates energy
well damped within 3 UI.
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
C-19
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
C-20
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
D Requirements Index
Note: AMC.1 R1.0 requirements, modified by R2.0, are marked with an “a” after the requirement number.
REQ 3.1............................................................... 3-1
REQ 4.1 ............................................................... 4-1
REQ 4.3a ............................................................ 4-2
REQ 4.4a ............................................................ 4-2
REQ 4.5a ............................................................ 4-4
REQ 4.6a ............................................................ 4-6
REQ 4.7 Removed in AMC.1 R2.0
REQ 4.8a ............................................................ 4-6
REQ 4.9a ............................................................ 4-6
REQ 4.10 - New in AMC.1 R2.0 ...................... 4-6
REQ 4.11 - New in AMC.1 R2.0 ...................... 4-6
REQ 4.12 - New in AMC.1 R2.0 ...................... 4-6
REQ 4.13 Removed in AMC.1 R2.0.
REQ 4.14 - New in AMC.1 R2.0 ...................... 4-6
REQ 4.15 Removed AMC.1 R2.0
REQ 4.16 Removed AMC.1 R2.0
REQ 4.17 Removed in AMC.1 R2.0
REQ 4.18 Removed in AMC.0 R2.0
REQ 4.20 - New in AMC.1 R2.0 ...................... 4-6
REQ 4.21 - New in AMC.1 R2.0 ...................... 4-1
REQ 4.22 - New in AMC.1 R2.0 ...................... 4-6
REQ 4.23 - New in AMC.1 R2.0 ...................... 4-6
REQ 4.24 - New in AMC.1 R2.0 ...................... 4-6
REQ 4.25 - New in AMC.1 R2.0 ...................... 4-6
REQ 4.26 - New in AMC.1 R2.0 ...................... 4-6
REQ 4.27 - New in AMC.1 R2.0 ...................... 4-6
REQ 4.28 - New in AMC.1 R2.0 ...................... 4-6
REQ 4.29 - New in AMC.1 R2.0 ...................... 4-6
REQ 5.1 ............................................................... 5-2
REQ 5.2 ............................................................... 5-3
REQ 5.3 ............................................................... 5-5
REQ 5.4 ............................................................... 5-5
REQ 5.5............................................................... 5-6
REQ 5.6 Removed in AMC.1 R2.0.
REQ 5.7 Removed in AMC.1 R2.0.
REQ 5.8 Removed in AMC.1 R2.0.
REQ 5.9 Removed in AMC.1 R2.0
REQ 5.10 Removed in AMC.1 R2.0
REQ 5.11 Removed in AMC.1 R2.0.
REQ 5.12 Removed in AMC.1 R2.0.
REQ 5.13 Removed in AMC.1 R2.0.
REQ 5.14 Removed in AMC.1 R2.0
REQ 5.15 Removed in AMC.1 R2.0.
REQ 5.16 Removed in AMC.1 R2.0.
REQ 6.1 Removed in AMC.1 R2.0
REQ 7.1a ............................................................ 7-1
REQ 7.2a ............................................................ 7-1
REQ 7.3 ............................................................... 7-2
REQ 7.4 ............................................................... 7-2
REQ 7.5 ............................................................... 7-2
REQ 7.6 ............................................................... 7-2
REQ 7.7 .............................................................. 7-2
REQ 7.8 .............................................................. 7-2
REQ 7.9 .............................................................. 7-2
REQ 7.10 ............................................................ 7-2
REQ 7.11a .......................................................... 7-2
REQ 7.12 ............................................................ 7-3
REQ 7.13 ............................................................ 7-3
REQ 7.14 ............................................................ 7-3
REQ 7.15 ............................................................ 7-3
REQ 7.16 ............................................................ 7-3
REQ 7.17 ............................................................ 7-3
REQ 7.18 ............................................................ 7-3
REQ 7.19 ............................................................ 7-3
REQ 7.20 ............................................................ 7-3
REQ 7.21 - New in AMC.1 R2.0 ..................... 7-4
REQ 7.22 - New in AMC.1 R2.0 ..................... 7-4
REQ 7.23 - New in AMC.1 R2.0 ..................... 7-2
REQ 7.24 - New in AMC.1 R2.0 ..................... 7-2
REQ 8.2 .............................................................. 8-8
REQ 8.3a ............................................................ 8-8
REQ 8.4 .............................................................. 8-9
REQ 8.5a .......................................................... 8-10
REQ 8.6 - New in AMC.1 R2.0 ...................... 8-14
REQ 8.7 - New in AMC.1 R2.0 ...................... 8-14
REQ 8.8 - New in AMC.1 R2.0 ...................... 8-14
REQ 8.9 - New in AMC.1 R2.0...................... 8-14
REQ 8.10 - New in AMC.1 R2.0 ................... 8-14
REQ 8.11 - New in AMC.1 R2.0 ................... 8-14
REQ 8.12 - New in AMC.1 R2.0 ................... 8-14
REQ 8.13 - New in AMC.1 R2.0 ................... 8-15
REQ 8.14 - New in AMC.1 R2.0 ................... 8-15
REQ 8.15 - New in AMC.1 R2.0 ................... 8-15
REQ 8.17 - New in AMC.1 R2.0 ................... 8-13
REQ 8.18 - New in AMC.1 R2.0 ................... 8-14
REQ 8.19 - New in AMC.1 R2.0 ..................... 8-9
REQ 8.20 - New in AMC.1 R2.0 ..................... 8-9
REQ 8.21 - New in AMC.1 R2.0 ................... 8-14
REQ 8.22 - New in AMC.1 R2.0 ................... 8-15
REQ 8.23 - New in AMC.1 R2.0 ................... 8-15
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008
D-1
Property of SLAC National Accelerator Laboratory. - For Internal Use Only – External Distribution Prohibited
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B-2
PICMG AMC.1 PCI Express Specification R2.0, October 8, 2008