advertisement

First Name: Last Name: PID: CSE 140 Midterm 2 Tajana Simunic Rosing Winter 2012 Do not start the exam until you are told. Write your name and PID at the top of every page. Do not separate the pages. Turn off and put away all your electronics. This is a closed-book, closed-notes, nocalculator exam. You may only refer to one 8 ½ x 11” page of your handwritten notes. Do not look at anyone else’s exam. Do not talk to anyone but an exam proctor during the exam. If you have a question, raise your hand and an exam proctor will come to you. You have 80 minutes to finish the exam. When the time is finished, you must stop writing. Write your answers in the space provided. To get the most partial credit, clearly and neatly show all steps of your work. 1. 10 points 2. 15 points 3. 15 points 4. 15 points 5. 20 points 6. 25 points Total (100 pts.) First Name: Last Name: PID: Problem 1 Consider the following circuit with a NOR-based SR-latch that is sensitive to high level of clock. Timing information is as follows: Tlatch = 0.5 ns Tgate = 0.5 ns Clock period = 4 ns with 50% duty cycle a) Draw the output waveforms for Q, Q’, X, Y, Z, and OUT from t=0 to t=7 First Name: Last Name: PID: b) Identify and name (static-0, static-1, dynamic) any hazards in the above waveforms. The 101 glitch at t=2ns to t=2.5ns is a static-1 hazard. First Name: Last Name: PID: Problem 2 Answer the following questions assuming given information below. Signal IN is an input to the circuit, and OUT is an output from the circuit. Tsetup = 1 ns Thold = 1 ns Tpd = 2 ns Tgate = 2 ns D Q CLK IN D Q CLK D Q OUT CLK a) What is the minimum clock period for this circuit assuming delay from IN is zero? The critical path is from the lower left FF to the right right FF through two XOR gates and two NAND gates. Total delay is Tpd + TXOR + TXOR + TNAND + TNAND + Tsetup = 11ns. Thus the minimum clock period is 11ns. First Name: Last Name: PID: b) Is it possible to increase the clock frequency by modifying the circuit without changing its functionality? If so, show how can this be achieved, and calculate what would the clock period be. If not, clearly explain why not. The circuit is in fact a synchronous Mealy FSM design, and the combinations logics compute both the next state and output value (which is registered for one cycle). The circuit can be modified into a Moore FSM design, which would exhibit same functionality and timing behaviors as synchronous Mealy. In order to do this, the input to the upper right NAND can be moved to the output of the left registers, and the right register can be removed. This would reduce the critical path to 2 gates (either two XOR or two NANDs). In this case, the minimum clock period is 7ns. First Name: Last Name: PID: Problem 3 Draw a state transition diagram for the circuit below. Succinctly describe what the circuit does. Signal IN is an input to the circuit. The state transition diagram is as below. It’s a grey code counter, where it counts up when IN=1, and maintains value on IN=0. 0 A=0 B=0 1 1 0 A=0 B=1 A=1 B=0 1 1 A=1 B=1 0 0 First Name: Last Name: PID: Problem 4 Draw a state transition diagram for FSM that counts the cumulative number of 1’s in 2bit input sequence, and outputs 1 if it is a multiple of 3, and 0 otherwise. For example: 00 11 10 01 00 … 1 0 1 0 0 … Input: Output: You must not use more than 4 states. 00/1 mod 3 =0 01,10/1 01,10/0 11/1 11/0 11/0 00/0 mod 3 =1 mod 3 =2 01,10/0 00/0 First Name: Last Name: PID: Problem 5 Below is a FSM for a 2-bit saturating counter, commonly used as a simple hardware predictor. Design a circuit for the 2-bit saturating counter. Use minimum number of DFFs and as few gates as possible. Because the states transitions are only to two other states, it might be best to encode states in grey code. Lets say S0 = 00, S1=01, S2=11, S3=10 In 0 0 0 0 1 1 1 1 CS[1] 0 0 1 1 0 0 1 1 Out = CS[1] NS[1] = CS[1] CS[0]’ + CS[0] In NS[0] = In XOR CS[1] CS[0] 0 1 0 1 0 1 0 1 Out 0 0 1 1 0 0 1 1 NS[1] 0 0 1 0 0 1 1 1 NS[0] 0 0 1 1 1 1 0 0 First Name: Last Name: PID: Problem 6 Answer the following questions for the following state transition diagram. a) Fill in the state transition table below Current state S0 S1 S2 S3 S4 S5 Next state Input = 0 S2 S4 S1 S1 S2 S4 Output Input = 1 Input = 0 Input = 1 S1 1 0 S3 1 1 S0 0 0 S4 0 0 S5 1 0 S2 1 1 First Name: Last Name: PID: b) Fill in the implication table X X X S1-S5 X X X S0-S4 X X X S2-S3 X X X c) List all the original states, grouped into maximal classes of compatibility. Use only as many groups as necessary. g0 = {S1, S5} g1 = {S2, S3} g2 = {S0, S4} g3 = g4 = g5 = First Name: Last Name: PID: d) Identify a set that satisfies both covering and closure conditions on maximal class of compatibility. List the resulting state transition and outputs in the table. Fill in as many rows of the table as necessary. Current state g0 g1 g2 g3 g4 g5 Next state Input = 0 g2 g0 g1 Output Input = 1 Input = 0 Input = 1 g1 1 1 g2 0 0 g0 1 0 First Name: Last Name: PID: (This page is intentionally left blank. Use as scratch paper or to provide additional answers)