Asynchronous Sequential Logic
6-1
Outline
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Introduction
Analysis Procedure
Circuit with Latches
Design Procedure
Reduction of State and Flow Tables
Race-Free State Assignment
Hazards
Design Example
6-2
Synchronous Sequential Circuit
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State changes synchronized by the common
clock pulse
Input changes occur between clock pulses
Wait long enough after the external input
changes for all flip-flop inputs to reach a steady
value before applying the clock pulse
Outputs are read immediately proceeding the
clock pulse
6-3
Sequential Circuit
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Outputs are functions of inputs and present
states of storage elements
Two types of sequential circuits
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Synchronous (preferred !!)
Asynchronous
6-4
Synchronous Sequential Circuit
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Unsuitable Situations:
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Inputs change at any time and cannot be
synchronized with a clock
Circuit is large, Clock skew can not be avoided
High performance design
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The system must respond quickly without having to
wait for a clock pulse
6-5
Asynchronous Sequential Circuit
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Not Synchronized by a Common Clock
States Change Immediately after Input Changes
Timing is a Major Problem
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Unequal delays through various paths in the circuit
Fundamental Mode:
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The input signals change one at a time
The input signals change only when the circuit is in a
stable condition
6-6
Block Diagram
6-7
Stable State
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The system is stable if yi = Yi for all i
A transition from one stable state to another
occurs only in response to a change in an
input variable
6-8
Outline
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Introduction
Analysis Procedure
Circuit with Latches
Design Procedure
Reduction of State and Flow Tables
Race-Free State Assignment
Hazards
Design Example
6-9
Asynchronous Sequential Circuit
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Construction of Asynchronous Circuits
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Using only gates
Like a combinational ckt with feedback paths
6-10
Asynchronous Sequential
Circuit
6-11
Transition Table
6-12
Total State
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Combine the internal state with input
variables
Stable total states:
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y1y2x = 000, 011, 110 and 101
6-13
Analysis Procedure
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Determine all feedback loops
Designate Yi and yi
Derive the Boolean functions of all Yi as a
function of the external inputs and yi
Plot the transition table and label the stable
total states
6-14
Flow Table for Designs
Primitive flow table
6-15
Circuit Derivation
a = 0;
b = 1;
Flow table -> transition
table -> circuit
6-16
Race Conditions
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Two or more state variables must change
states in response to a single change in input
Noncritical Race
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The resulting stable state is the same no matter
in what order the state variables change
Critical Race
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The resulting stable state depends on the order
in which state variables change state
6-17
Noncritical Races
6-18
Critical Races
6-19
Race Avoidance
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Proper binary assignment to the state
variables in such a way that only one
variable can change at any one time when a
state transition occurs
Directing the circuit through intermediate
unstable states with a unique state-variable
change
6-20
Cycles
When a circuit goes through a unique sequence of unstable states
6-21
Unstable Circuit
Unstable when x1x2 = 11
6-22
Outline
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Introduction
Analysis Procedure
Circuit with Latches
Design Procedure
Reduction of State and Flow Tables
Race-Free State Assignment
Hazards
Design Example
6-23
SR Latch with NOR Gates
Reduced excitation func
6-24
SR Latch with NAND Gates
6-25
Analyzing a Circuit with SR
Latch
Y1 = S1 + R1‘ y1
Y2 = S2 + R2‘ y2
6-26
Analysis
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S1 = x1 y2 S2 = x1 x2
R1 = x1‘ x2‘ R2 = x2‘ y1
S1R1 = 0 S2R2 = 0
Y1 = S1 + R1‘ y1 = x1 y2 + x1 y1 + x2 y1
Y2 = S2 + R2‘ y2 = x1 x2 + x2 y2 + y1‘ y2
 transition table
6-27
Transition Table
1101 => 1100
(possible critical
race)
If y1 changes to 0
before y2,
y1y2x1x2=0100
instead of 0000
6-28
Circuit Derivation
a = 0;
b = 1;
Flow table -> transition
table -> circuit
6-29
Circuit Derivation by Latch
Excitation Table
0
6-30
Outline
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Introduction
Analysis Procedure
Circuit with Latches
Design Procedure
Reduction of State and Flow Tables
Race-Free State Assignment
Hazards
Design Example
6-31
Primitive Flow Table
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Primitive Flow Table - Has Exactly One
Stable Total State Per Row
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To Avoid the Timing Problems:
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Can be further reduced
Only one input variable changes at a time
Networks reach a stable total state between
input changes (Fundamental Mode)
Every Change in input Changes the State
6-32
Design Example 1
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Example: Asynchronous Network
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Two inputs, One output.
Input sequence X1X2 = 00,01,11 causes output to
become 1.
The next input change causes the output to return to 0.
Flow Table
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-:Double input change is not allowed.
Each input change goes through one unstable total state on
the way to the corresponding stable total state.
6-33
Design Example 1
6-34
Design Example 1
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State Diagram
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All arrows leading into a given state have the
same input.
6-35
Design Example 2
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Gated Latch
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Q = D when G == 1
Q retains its value when G goes to 0
6-36
Sample State Table
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All the total states
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combinations of the inputs and internal states
simultaneous transitions of two input variables are not allowed
If DG from 01 to 00 to 10, Q remains 0
If DG from 11 to 10 to 00, Q remains 1
37
Primitive Flow Table
6-38
Reduced Flow Table
6-39
Transition Table and
Output Map
a = 0; b = 1;
6-40
Gated-Latch Logic Diagram
6-41
Circuit with SR Latch
6-42
Output Assignment : Another
Example
6-43
Design Procedure
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Derive a primitive flow table (the most
difficult part)
Reduce the flow table
Conduct state assignment to obtain the
transition table and eliminate possible
critical races
Assign output values to the unstable states
Simplify the Boolean functions
6-44
Outline
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Introduction
Analysis Procedure
Circuit with Latches
Design Procedure
Reduction of State and Flow Tables
Race-Free State Assignment
Hazards
Design Example
6-45
Reduction of Primitive Flow Table
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Reduction of the Flow Table to a Minimum
Number of Rows
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Reduce the number of state variables
Reduce the amount of logic required
Reduction Method :
1.Equivalent states can be combined by using
implication table method for completely specified
state tables
2.Compatible rows can be merged for incompletely
specified tables
6-46
Equivalent States
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For all possible input combinations
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Same outputs
Next states are equivalent
6-47
State Table To Be Reduced
6-48
Implication Table
(a,b) (d,e) (d,g) (e,g)
(a,b) (c) (d,e,g) (f)
6-49
Reduced State Table
6-50
Incompletely Specified State
Table
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Certain combinations of inputs or input sequences may
never occur
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The corresponding next states and outputs are regarded as
don’t care conditions
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Primitive flow table is always incompletely specified
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Two incompletely specified states are compatible if for
each possible input they have the same output whenever
specified and their next states are compatible whenever
they are specified
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Don’t care represents unspecified condition
6-51
Merging of the Flow Table
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Determine all compatible pairs by using the
implication table
Find the maximal compatibles using a
merger diagram
Find a minimal collection of compatibles
that covers all states and is closed
6-52
Flow and Implication Tables
(from Gated Latch Example)
(a,b) (a,c) (a,d) (b,e) (b,f)
(c,d) (e,f)
6-53
Maximal Compatibles
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A group of compatibles that contains all
possible combinations of compatible states
Can be obtained from a merger diagram
Is reduced to find cliques in a graph
6-54
Merger Diagram
6-55
Row Merging
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The chosen set of maximal compatibles
must cover all states and must be closed
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Include all states of the original state table
No-implied states/the implied states are
included within the set
Example (Fig.9.24(a) removing (a, b))
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(a,c,d) (b,e,f)
No-implied states: (a,c) (a,d) (c,d) (b,e) (b,f)
(e,f)
6-56
Example Revisit
6-57
Another Example
6-58
Closed Covering Condition
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The Compatible Pairs
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The Maximal Compatibles
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(a,b) (a,d) (b,c) (c,d,e)
A set of compatibles that does not satisfy the
closed covering condition
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(a,b) (a,d) (b,c) (c,d) (c,e) (d,e)
(a,b) (c,d,e)
A set of compatibles that satisfies the closed
covering condition
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(a,d) (b,c) (c,d,e)
(a,b) (b,c) (d,e)
6-59
Systematic Way to Obtain a Set
V1: (a,b) V2: (a,d) V3: (b,c)
V4: (c,d,e) V5: (d,e)
 Closed Condition:
V1->V3 => V1’+V3
V2->V3 => V2’+V3
V3->(V5+V4) => V3’+V4+V5
V4->V2V3=> (V4’+V2)(V4’+V3)
6-60
Choosing a Set of Compatibles
Covering Condition
V1+V2 (state a)
V1+V3 (state b)
V3+V4 (state c)
V2+V4+V5 (state d)
V4+V5 (state e)
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6-61
Choosing a Set of Compatibles
(V1’+V3)(V2’+V3)(V3’+V4+V5)(V4’+V2)
(V4’+V3)(V1+V2)(V1+V3)(V3+V4)
(V2+V4+V5)(V4+V5) = 1
V1=0, V2=1, V3=1, V4=1, V5=0
=>(a,d) (b,c) (c,d,e)
V1=1, V2=0, V3=1, V4=0, V5=1
=> (a,b) (b,c) (d,e)
6-62
Outline
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Introduction
Analysis Procedure
Circuit with Latches
Design Procedure
Reduction of State and Flow Tables
Race-Free State Assignment
Hazards
Design Example
6-63
State Assignment
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Primary Objective of Synchronous Networks
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Simplification of Logic
Improvement of Performance
Improvement of Testability
Minimization of Power Consumption
Primary Objective of Asynchronous Networks
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Prevention of Critical Races
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Simplification of Logic
6-64
Flow Table Example
a -> c could cause critical race
6-65
Extra Row for Race-Free
6-66
Transition Table with Indicated
Binary State Assignment
6-67
1. Shared-Row Method
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Not assigned to any specific stable state
Used to convert a critical race into a cycle
that goes through adjacent transitions
between two stable states
May add two or more extra rows
Drawback: actual assignment is done by
trial and error
6-68
Another Example for
Shared-Row Method
6-69
Choosing Extra Rows
2 3
1
6-70
State Assignment
6-71
2. Don’t Care Assignment for
Race-Free
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Needed Transitions
All possible transitions between pairs of
rows are needed
6-72
Don’t Care Assignment
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Fill in Don’t Care to Eliminate Races
Direct transitions for columns 01, 10 (No
Don’t Care)
In column 00: d->a changed to d->c->a.
In column 11: b->c changed to b->a->c.
6-73
Four-Row Flow Table
Example Revisit
6-74
3. Multiple-Row Method
6-75
Outline
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Introduction
Analysis Procedure
Circuit with Latches
Design Procedure
Reduction of State and Flow Tables
Race-Free State Assignment
Hazards
Design Example
6-78
Asynchronous Sequential Circuits
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Operated in fundamental mode with only
one input changing at any time
Free of critical races
Free of hazards
6-79
Hazards
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A timing problem arises due to gate and
wiring delays
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Unwanted switching transients at the network
output caused by input changes in
combinational networks
Because different paths through the network
from input to output may have different
propagation delays
6-80
Circuit with Hazards
Y = x1 x2 + x2’ x3
1 -> 0 -> 1
6-81
Types of Hazards
6-82
Hazards
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Hazards in the combinational part of a
sequential network
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Cause the sequential network to malfunction
Hazards in the output network can produce
momentary false outputs
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Cause problems in the subsequent
asynchronous networks
6-83
Circuit with Hazards
Under transient conditions, x2 and x2’ are not
complement
6-84
Hazard Removal
x2= x2’= 0, the term x1 x3 remains
The hazard exists because the change in input results in a different product term
covering the two minterms
6-85
Hazards in Sequential Circuits
yx1x2=111 to 110
Y will go to 0 momentarily
6-86
Hazard-Free Circuit
6-87
Outline
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Introduction
Analysis Procedure
Circuit with Latches
Design Procedure
Reduction of State and Flow Tables
Race-Free State Assignment
Hazards
Design Example
6-91
Design Procedure
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State the design specifications
Derive a primitive flow table
Reduce the flow table by merging the rows
Make a race-free binary state assignment
Obtain the transition table and output map
Obtain the logic diagram using SR latches
6-92
Design: T Flip-Flop
Implementation
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A Negative-Edge-Triggered T FF
Two inputs : T (toggle), C (clock)
Flip-Flop changes state (complemented)
when T = 1 and C changes from 1 to 0
Q remains constant (unchanged) under all
other conditions
T and C do not change simultaneously
6-93
Design Procedure
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State the design specifications
Derive a primitive flow table
Reduce the flow table by merging the rows
Make a race-free binary state assignment
Obtain the transition table and output map
Obtain the logic diagram using SR latches
6-94
Primitive Flow Table
Start with TC=11 and
assign it state a
6-95
Design Procedure
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State the design specifications
Derive a primitive flow table
Reduce the flow table by merging the
rows
Make a race-free binary state assignment
Obtain the transition table and output map
Obtain the logic diagram using SR latches
6-96
Implication Table
6-97
Merger Diagram
(a,f) (b,g) (b,h) (c,h) (d,e) (d,f)
(e,f) (g,h)
The maximal compatible set is
(a,f) (b,g,h) (c,h) (d,e,f),
and satisfies the closed
condition
6-98
Reduced Flow Table
6-99
Design Procedure
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State the design specifications
Derive a primitive flow table
Reduce the flow table by merging the rows
Make a race-free binary state assignment
Obtain the transition table and output map
Obtain the logic diagram using SR latches
6-100
Transition Diagram
6-101
Transition Table and Output Map
6-102
Latch Input Maps
6-103
Edged Triggered T Flip-Flop
6-104