FR2A-2
Proceedings of Asia-Pacific Microwave Conference 2010
A 57-66 GHz Medium Power Amplifier in 65-nm CMOS Technology
Chia-Yu Hsieh 1, Jhe-Jia Kuo 2, Zuo-Min Tsai 3, Kun-You Lin 4
Department of Electrical Engineering and Graduated Institute of Communication Engineering, National Taiwan University
No. 1, Sec. 4, Roosevlt Road, Taipei, 10617 Taiwan
1
charlenefish@gmail.com
2
f94942020@ntu.edu.tw
3
zuomintsai@gmail.com
4
kunyou@ntu.edu.tw
Abstract — This paper presents the design and measurement
results of a 57-66 GHz medium power amplifier in 65-nm LP
CMOS process. This amplifier is designed with broadband
matching concern, which can achieve a measured gain more
than 21 dB from 57-66 GHz and have a 3-dB bandwidth more
than 14 GHz while consuming 54 mW from a 1.2 V supply. The
measured results exhibit Psat of 10.3 dBm, P1dB of 6.2 dBm, and
the peak PAE is 16 % at 58 GHz. The chip size is only 0.3 mm2.
Index Terms — Broadband, CMOS, 60 GHz, MMIC, power
amplifiers.
In this paper, the design flow and strategy of a CMOS
medium power amplifier is presented. Especially the
wideband design techniques for power amplifier are
discussed. With the proper device selection and wideband
matching networks, the proposed medium power amplifier
achieves a Psat of 10.3 dBm and 16% PAE. The design
methods described in this paper can be used in CMOS
wideband power amplifier designs.
II. CIRCUIT DESIGN
I. INTRODUCTION
To meet the requirement of high data rate, high speed, and
high quality wireless communication, high frequency circuit
design becomes more and more necessary. Since Federal
Communications Commission (FCC) released unlicensed
band from 57-66 GHz to support Wireless Personal Area
Networks (WPANs) in IEEE 802.15.3C, the researches of
high frequency integrated circuit grow rapidly [1].
Recently, CMOS millimeter-wave circuits become more
popular because of the high level integration with digital
circuits. Compared to III-V compound technologies for high
frequency circuits, the characteristic of rather low power
consumption makes CMOS technology more suitable in
hand-held devices.
Power amplifier plays an important role in the RF
transceiver circuits. It must deliver sufficient output power to
drive the following power amplifier or antenna. Recently,
numerous 60 GHz medium power amplifiers realized by
CMOS process were reported. Multi-stage common-source
medium power amplifiers are presented to achieve a linear
gain of 13-dB and a saturated output power of 7.9-dBm at 60
GHz [2]-[3]. Transformer coupled technique is used to realize
a three-stage pseudo-differential power amplifier to achieve a
16-dB linear gain, and a 11.5-dBm saturated output power
with a peak PAE of 15.2 % at 60 GHz [4]. In addition,
combined common-source topology at output stage [5] and
cascode topology at prior stages [6] are also applied in 60
GHz medium power amplifiers. However, some previous
works, cannot achieve high gain and high output power at the
same time, and others cannot achieve high gain and high
output power within wide bandwidth.
Copyright 2010 IEICE
This circuit was fabricated in 65-nm CMOS LP process in
1.2 V applications, which provides one poly layer for the
gates of CMOS transistors and nine metal layers with ultrathick top metal (metal 9) of 3.4 μm while featuring deep Nwell (DNW). The RF NMOS transistors can achieve
maximum oscillation frequency (fmax) of around 140 GHz
with 1.2 V supply. In addition, metal-insulator-metal (MIM)
capacitors are available between metal 8 and metal 7.
The circuit schematic of proposed medium power
amplifier is shown in Fig. 1. This amplifier consists of four
stages common-source devices with input, output and interstage matching networks. In order to achieve high output
power, the size of output stage transistor (M4) needs to be
chosen carefully. In general, the device with larger size can
deliver higher output power while dissipating more dc power.
Therefore, making a compromise to achieve design goal can
decide proper size of M4. The final chosen M4 with width of
63 μm and length of 65 nm can deliver maximum power of
9.9 dBm and maximum available gain of about 9 dB from 5766 GHz under class A operation. To achieve high gain
performance without high power consumption, other stages
device can be estimated from prior stage. Since the total
width of device is proportional to the output power it can
deliver, the device size of M3 can be calculated as
1617
OP3,1dB  IP4,1dB
OP4,1dB
OP3,1dB

w4
w3
(1)
(2)
Fig. 1 Schematic of proposed medium power amplifier.
, where IP4,1dB, OP4,1dB, and w4 are decided according to the
simulation already. Therefore, after the determination of the
OP3,1dB under the condition of (1), w3 can be computed by (2).
In this circuit, we choose
OP3,1dB  IP4,1dB  3 (dB)
(3)
to guarantee that the power won’t saturate at M3. Finally, the
device sizes of other stages can also be calculated by the
same formulas.
(a)
Output Matching Network
5
Term 1
50 Ω
3
4
1
2
Term 2
50 Ω
(b)
Fig. 2 (a) Simulated load-pull points and S11 of output matching
from 57-66 GHz with matching path at 60 GHz. (b) Output
matching network.
The matching networks of this circuit are realized by thinfilm microstrip (TFMS) lines with metal 9 as the signal lines
and metal 1 as the ground. In addition, the microstrip lines
with 60 Ω of characteristic impedance are used in matching
networks. In general, output matching network is the most
essential part in power amplifier since it can affect the
delivered power of amplifier directly. Therefore, the
matching network of the power amplifier should be designed
in sequence from output matching network, inter-stage
matching network, to input matching network.
The output matching circuit design is plotted in Fig. 2 (a)
and (b). The numbers in Fig. 2 (a) represent the sequence of
60 GHz matching path and the numbers in Fig. 2 (b) represent
the corresponding matching stubs. Notice that number 1 and
5 are absent on matching path since these two series line are
used to connect terminal with little matching effect. The
output matching is designed to make the input impedance
close to simulated load-pull positions from 57-66 GHz which
can result in broadband power matching, as shown in Fig. 2
(a). Notice that the load-pull positions from 57-66 GHz are
very close. The matching network which consists of one open
stub, one series line and one short stub with two series line
connecting to two terminals can achieve broadband matching.
Open stubs, series lines and short stubs affect S-parameters
differently from high frequency to low frequency. Open stubs
and series line manifest themselves on higher frequency
while short stubs manifest themselves on lower frequency.
Using these frequency-dependent properties, the loci of S11 in
the interested frequency band can finally circle the load-pull
position on the Smith chart.
Each inter-stage matching network is matched to output
conjugate impedance of prior stage device. The devices of
prior stages are smaller with high gain and low current
consumption benefits. However, stability will be a challenge
at inter-stage matching. In addition to fine tune the matching
network, source degeneration can make conjugate matching
easily with a little sacrifice on linear gain.
The input matching circuit design is plotted in Fig. 3 (a) and
(b). The numbers in Fig. 3 (a) represent the sequence of 60
GHz matching path and the numbers in Fig. 3 (b) represent
the corresponding matching stubs. The input matching
network is designed to match to 50 Ω from 57-66 GHz with
the same broadband matching technique in the output
matching network. It can be observed that S11 circles 50 Ω
1618
peak gain of 23.7 dB at 64 GHz while return losses are larger
than 7.8 dB from 57-66 GHz.
Power measurement was done by adding signal generator
Agilent E8257D at input while a power meter Agilent E4419
and a power sensor Agilent V8486A was set to measure the
output power at output. Fig.6 shows the large signal behavior
50j
25j
100j
57 GHz
10j
250j
4
3
60 GHz
10
25
50
5
100
RFout
VDD
250
2
Vg
66 GHz
-10j
-250j
Vg
1
-25j
GND
-100j
RFin
Input Matching from 0-100 GHz
Matching Path at 60 GHz
-50j
Fig. 4 The chip micro-photograph of proposed medium power
amplifier with chip size of 0.36 × 0.8 mm2 including all the
testing pads.
(a)
Interstage
Matching
Network
Input Matching Network
5
3
1
M1
Term 1
50 Ω
4
30
2
20
Output
Matching
Network
M4
M3
S-Parameters (dB)
Interstage
Matching
Network
Interstage
Matching
Network
Term 2
50 Ω
M2
(b)
Fig. 3 (a) S11 of input matching from 0-100 GHz with matching
path at 60 GHz. (b) Input matching network.
10
0
-10
-20
Measured |S21|
Measured |S11|
Measured |S22|
-30
-40
40
50
60
70
80
Frequency (GHz)
Fig. 5 Measured small signal gain and I/O return loss of the
proposed medium power amplifier under VDD of 1.2 V.
1619
20
30
15
25
10
20
5
15
0
10
Pout
PAE
Gain
-5
5
-10
0
-30
-25
-20
-15
-10
-5
0
Pin (dBm)
Fig. 6 Measured Pout, PAE, and Gain versus Pin at 58 GHz.
5
Gain (dB)
A four-stage medium power amplifier is designed focusing
on achieving high gain and high output power with
reasonable power consumption and compact size. The chip
micro-photograph is shown in Fig. 4 with a chip size of 0.36
× 0.8 mm2 including all the testing pads.
The measurements are performed by on-wafer probing. The
vector network analyzer Agilent E8361C and Anritsu 37397D
used to measure the small signal S-parameters from 40 MHz65 GHz and 65-90 GHz respectively. As all four transistors
are biased at class A operation for gain and linearity concern,
total dc current consumption is 45 mA with V DD of 1.2 V and
Vg of 0.8 V. Fig. 5 shows the measured small signal gain and
return losses of this amplifier. This amplifier achieves a
measured gain of more than 21 dB from 57-66 GHz with
Pout (dBm)
III. EXPERIMENTAL RESULT
PAE (%)
from 57-66 GHz to achieve the broadband matching. Since
the input and output matching networks dominate the
bandwidth of port return loss, both the input and output
matching are designed with more sections than that in the
inter-stage matching, which can be seen in Fig. 1.
P1dB, Psat (dBm)
18
10
15
8
12
6
9
4
6
P1dB
Psat
2
measured. This circuit achieves high gain and high output
power at the same time with simple structure but careful
broadband matching concern. From a 1.2-V supply, Psat of
10.3 dBm is achieved with PAE of 16 % at 58 GHz. The
linear gain is above 21 dB from 57-66 GHz with 3-dB
bandwidth of 14 GHz while consuming 54 mW.
Peak PAE (%)
12
ACKNOWLEDGEMENT
This work was supported in part by the National Science
Council of Taiwan, R.O.C. (under NSC 98-2219-E-002-009),
the Excellent Research Projects of National Taiwan
University (98R0062-03, 99R80300) and the University
Shuttle Program of Taiwan Semiconductor Manufacturing
Company (TSMC), Hsin-chu, Taiwan. The EDA tools are
provided by National Chip Implementation Center (CIC),
Hsinchu, Taiwan.
3
Peak PAE
0
57
58
59
60
61
62
63
64
65
0
66
Frequency (GHz)
Fig. 7 Measured power performance from 57-66 GHz, which
including P1dB, Psat, and peak PAE.
of this amplifier with increasing input power at 58 GHz. A
Psat of 10.3 dBm and a peak PAE of 16% are achieved. Fig. 7
shows measured P1dB, Psat, and peak PAE from 57-66 GHz. It
can be seen that the P1dB is larger than 4 dBm from 57-66
GHz with maximum P1dB of 6.2 dBm at 58 GHz. The Psat is
larger than 8.2 dBm from 57-66 GHz, and a maximum Psat of
10.3 dBm is achieved at 58 GHz. From 57-66 GHz, the peak
PAE exceeds 9.5 %.
Table I summarizes the performance of reported 60-GHz
CMOS medium power amplifiers. This work demonstrates
highest gain with broadband feature while achieving a
maximum Psat of 10.3 dBm and a peak PAE of 16 % with
reasonable power consumption of 54 mW and compact chip
size of 0.3 mm2.
VI. CONCLUSIONS
A wideband medium power amplifier at 60 GHz using 65
nm CMOS process has been designed, fabricated and
REFERENCES
[1] IEEE P802.15-05-0596-01-003c
[2] M. Varonen, M. Kärkkäinen, M. Kantanen, and K. A. I.
Halonen, “Millimeter-wave integrated circuits in 65-nm
CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 1991–
2002, Sep. 2008.
[3] Dan Sandström, Mikko Varonen, Mikko Kärkkäinen and Kari
Halonen, “60 GHz amplifier employing slow-wave
transmission lines in 65-nm CMOS,” NORCHIP, 2008. pp. 2124, Nov. 2008.
[4] Wei L. Chan and John R. Long, “A 58–65 GHz neutralized
CMOS power amplifier with PAE above 10% at 1-V supply,”
IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 554-564, Mar.
2010.
[5] Debasis Dawn, Saikat Sarkar, Padmanava Sen, Bevin
Perumana, Matthew Leung, Navin Mallavarpu, Stephane Pinel,
and Joy Laskar, “60GHz CMOS power amplifier with 20-dBgain and 12dBm Psat,” in IEEE MTT-S Int. Microw. Symp. Dig.,
2009, pp. 537-540.
[6] S. Pinel, S. Sarkar, P. Sen, B. Perumana, D. Yeh, D. Dawn, and
J. Laskar, “A 90 nm CMOS 60 GHz radio,” in IEEE Int. SolidState Circuits Conf. Tech. Dig., Feb. 2008, pp. 130–131.
TABLE I
REPORTED PERFORMANCES OF 60-GHZ MEDIUM POWER AMPLIFIERS.
Ref .
[3]
[4]
[5]
[6]
This Work
Process
65-nm CMOS
65-nm CMOS
90-nm CMOS
90-nm CMOS
65-nm CMOS
Topology
3-stage CS
3-stage CS Diff. w/
1-stage cascade+2-stage
1-stage cascode+2-stage
baluns
CS+1-stage combined 2 CS
CS
4-stage CS
Frequency [GHz]
51-67
58-65
57-65
57-65
57-66
(3-dB BW)
(19.6)
(8.5)
(8)
(8)
(14)
Peak Gain [dB]
13
16
20
17
23.7
OP1dB [dBm]
4
5
8.2
5.1
6.2
Psat [dBm]
7.9
11.5
12
8.4
10.3
Peak PAE [%]
8
15.2
9
5.8
16
PDC [mW]
54
50
146
(VDD)
(1.2 V)
(1 V)
(1.2 V)
Chip Size [mm2]
0.43
0.05*
0.65
1620
54
0.99
54
(1.2 V)
0.3