I
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deret
rnSa riia{or $uu
.
.
.
.
.
.
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(III)
Data-Acquisition Systems
Data-Acquisition Systems Components
AnaLog lnput-Output Comunication
DigitaL lnput-Output Comunication
Summary
ProbLems
7.6
DATA-ACQUTSTTION SYSTEMS
A data-acquisition syslsa is the portion of a measurement systen that quantifies and
stores data. There are many ways to do this. An engineer who reads a transducer dial
associates a number with the dial position. and records the information in a log book
performs all of the tasks germane to a data-acquisition system. [n this section, we focus
on microprocessor-based data-acquisition systems, rvhich are used to perform automated
data quantification and storage.
Figure 7.13 shows how a data-acquisition system (DAS) might fit into the general
measurement scheme between the actual measurement and the subsequent data reduction.
A typical signal flow scheme is shown in Figure 7.14 for multiple input signals to a single
microprocessor-based/controller DAS.
Dedicated microprocessor systems can continuously perform their programnting
instructions to measure, store, interpret and provide process control without any intervention. Such microprocessors have input/output (VO) ports to interface with other
devices to measure and to output instructions. Programming allows for such operations as
which sensors to measure, and when and how otten, and for data reduction. Programming
can allow for decision-making and feedback to control process variables.
Computer-based data-acquisition systems are hybrid systems combining a dataacquisition package with both the microprocessor and human interface capability of a
personal computer (PC). The interface between external instruments and the PC is done
using input/output (VO) boards, which either mate to a board in an expansion slot in
the computer or to an external communication port. These provide direct access to the
computer's bus, the main path used for all computer operations.
*'[,.*""_l
l's
[
I
:ff*_l L J L i
il;:Transducer
?"','r
Data-acquisition
system
Figure 7.13 Typical signal and measurement scheme.
Postprocessing
258
Chapter
7
Fundamentals
ol Sampling.
Data Acquisirion. and
Digital
Devices
Digrtal
i nputs
Analog
Srgnal
transducers condittontng Multiplexer
Controller
Figure 7.14 Signal florv scheme for
an automated
data-acquisition system
7.7
DATA-ACQUTSITION SYSTBMCOMPONENTS
Signal Conditioning: Filters and Amplification
Analog signals will usually require some type of signal conditioning lor the proper inrerface with a digitat system. Filters and amplifiers are the most common components used.
Filters
Analog flters are used to controI the frequency content o€ the signal being sarnpled. Antialias analog filters remove signal information above the Nyquist frequency' prior to
sampting. Not all data-acquisition boards contain analog filters, so these necessar)'
components are often overlooked.
Digitalflters, rvhich are software-based algorithms, are effective for signal analysis
after sampling. They cannot be used to prevent aliasing or to remove its eflects. A typical
digital filtering scheme involves taking the Fourier transform of the sampted signat.
multiplying the signal amplitude in the targeted frequency domain to attain the clesired
frequency response (i.e., type of filter and desired ftlter settings), and transforming the
signal back into time domain usingthe inverse Fourier transform It, 2].
A simpler digital filter is the moving average or smoothing filter, r.vhich is used tbr
removing noise. Essentiatly, this filter replaces a current data point value with an average
based on a series of successive data point values. A center-weighted moving averaging
scheme takes the form
.r',
:
()',-, + ...
+)i-r *)'r *)'i+r l- ... *y*)l(2n* l)
(7.f0)
r,vhere 1i is the averaged value that is calculated and used in place of
_1. ancl (2n + t)
represents the number of successive values used for the averaging. For exanrple. if r'1 : -i.
-]'c:2, then a three-term average of y5 produces )'j :3.
ln a similar manner, a forrvard-moving averaging smoothing scheme takes the tbrnr
)s:4,
l',:
: (l'i *)i+r *
1
.y;1"
)/(n *
I
)
\1.2t1
and a back'"vard moving averaging smoothing scheme takes the form
)'i
:(Yi-,+"'+)'r-r *
b
r-;)I@+l)
\1.r,\
1.7
Data-Acquisition Sl,stem Components 259
r---------t
t'=
I
Lru'
L'yl-:,1,i:-i
Figure 7.15 Voltage divider
circuit for signal amplitude
attenuation.
Light filtering might use three terms while heavy filtering might use l0 or more terms.
This filtering scheme is easily accomplished lr,ithin a spreadsheet program.
Amplifiers
All data-acquisition systems are input range limited; that is, there is a minimum value of
signal that they can resolve, and a maximum value that initiates the onset of saturation. So
some transducer signals rvill need ampliftcation or attenuation prior to conversion. Most
data-acquisition systems contain on-board instrumentation amplifiers, as depicted in
Figure 7.14, rvith selectable gains ranging from less than to greater than unity. Gain is
varied either by a resistor jumper or by logic switches set by software, which effectively
reset resistor ratios across op-amplifiers. Chapter 6.6 discusses amplifiers.
Although instrument amplifiers offer good output impedance characteristics, voltages
can also be attenuated using a voltage divider. The output voltage from the divider circuit
of Figure 7.15 is determined by
Eo:
"
Ei=
'R1
*t
*R2
(7.2i)
For example, a 0-50-V signal can be measured by a G-10-V A,/D converter using
:40kO and R2 : l0kQ.
Rr
When only the dynamic content of time-dependent signals is important, amplification
may require a strategy. For example, suppose the mean value of a voltage signal is large
but the dynamic content is small, such as with the 5-Hz signal
:2
(7.24)
+ o.l sinl0nt [V]
Setting the ampli{ier gain at or more than G: 2.5 to improve the resolution of the
dynamic content would saturate a *5-V A,/D converter. [n such situations, you can
)'(t)
remove the mean component from the signal prior to amplification by (1) adding a mean
voltage of equal but opposite sign, such as -2 V here, or (2) passing the signal through a
very low frequency high-pass filter (also known as ac coupling).
Shunt Circuits
An A/D converter requires a voltage signal at its input. [t is straightforward to convert
cun-ent signals into voltage signals using a shunt resistor. The circuit in Figure 7.16
provides a voltage
E,
: /Rrnunr
Q.25)
for signal current 1. For a transducer using a standard 4-to-20-mA current loop, a 250 Q
shunt would convert this current output to a l-to-5-V signal.
260
Chapter
7
Fundamenrals
of Sarnpling, Data Acquisition, and Digital Dcvices
L'l,'lrlgot:-.i
E, = I B.n*,
Figure 7.16 Simple shunt
resistor circuit.
E:
i
**"*
i
R2
Rnu,,
CH+
cH-
ift:
ftr
Figure 7.17 Circuit for applying
a null offset voltage. (Courtesy of
National Instruments, [nc.)
E;
Offset Nulling Circuit
Offset nulling is used to subtract out a small voltage from a signal, such as to zero out a
transducer output signal. The technique uses a trim potentiometer (R.rn) in conjunction with
a bridge circuit, such as shown in Figure 7 .17 , to produce the null voltage, Enuu. A common
use o[ this circuit is in conjunction with strain gauges. The available nu[[ voltage is
Enurr:-F-
EiRt(Rnr1
RnullR"en*
t
f
Rr"nror)
R3(Rnu11
*
(7 26)
Rr"nror)
Multiplexer
When multiple input signat lines are connected by a common throughput line to a single
A./D converter, a multiplexer is used to switch between connections, one at a time. This
is illustrated by the multiplexer depicted in Figure 7.18, which
uses parallel flip-flops
Figure 7.18 Multiplexer (four-channel shown).
d
1.1
Data-AcquisitronS;'sternCornponents 26L
(see Chapter6) to open and close the connection paths sequentially. The switching rate is
deterrnined by the conversion timing control logic.
A/D Converters
High-speed data-acquisition boards employ successive approximation converters with
conversion rates typically up to the l-kHz to l0-MI{z range or parallel converters for
rates up to and over 150 MHz. Lorv-level voltage measurements require the high noise
rejection of the dual-ramp con\/erter. Here the trade-off is in speed w'ith maximum
conversion rates of l-100 Hz more common.
D/A Converters
A
digital-to-analog converter permits a DAS to convert digital numbers into analog
voltages, which might be used flor process controi, such as to change a process variable,
activate a device, or to drive a sensor positioning motor. The digital-to-analog signal is
initiated by software or a controller.
Digital Input/Output
Digital signals represent a discrete state, either high or loiv. Digital input/output lines may
be used to communicate between instruments (see Section 7.9), control relays (to power
equipment on or off), or indicate the state or status of a device. A common way to
transmit digital information is the use o[ a 5-V TTL signal (e.g., see Figure 7.5).
Digital VO signals may be as a single state (HIGH or LOW; 5 Vor 0 V) or as a series
of pulses of HIGFVLOW states. The single-state signal might be used to operate a switch
or relay or to signal an alarm. A series of pulses transmits a data series. Gate pulse
counting entails counting pulses that occur over a specified period of time. This enables
frequency determination (number of pulses/unit time) and counting/timing applications.
Pulse stepping, sending a predetermined number ol pulses in a series, is used to drive
stepper motors and servos. Several VO ports can be grouped to send parallel information.
Central Processing Unit: Microprocessor
Data-acquisition and control systems are usually built around a microprocessor. A PC is
commonly used as it offers all the necessary components for elfective measurement, data
collection, program logic, and feedback control. This includes large amounts of memory
for programming and storage, control circuits, input/output peripherals, and a clock built
around a central processing unit (CPU).
The CPU controls operations, processes data, and sends and receives information to
and from memory and peripherals via a bus. It consists of a control unit, arithnretic and
logic unit (ALU), and registers. CPU timing is regulated about the regular pulses from its
clock, and this is used to sequence actions. [t perlorms arithmetic operations, comparisons, logical operations, and data management by combining the contents of registers.
The CPU moves bits between registers in blocks. For example, a 32-bit CPU can access
blocks of 32 bits representing 232 different integer numbers.
Special-purpose, direct-application microprocessors are also common. These are
found in many devices, including stand-alone data-acquisition systems and closed-loop
control[ers, and are quite flexible in their use. [n addition to data acquisition from sensors,
d
262
Chapter
7
Fundamentals
ol
Sanrptins. Data Acqui.ition. rrnd Digitat Dcviccs
BASIC STAMP II'', O:
:: : : : : : : :
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o o o o o o o o o o o o oo o o o o o
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oo
ooooo oo
ooooo oo
ITITIIIIIIII
ooooo oo
ooooo
(JU
Prototypr
area
n
g
BS2-lO
socket
ooooooo
ooooooo
ooooooo
IIIIIIITIIII
xxzooaNmso@sOOOOOOO
<-
FEFzLLLOLLLL
ooooooo
ooooooo
ooooooo
ooooooooooooooooooo
ooooooooooooooooooo
ooooooooooooooooooo
ooooooooooooooooooo
ooooooooooooooooooo
u;l;: " : 3 : : : : : : :
P,RAVX
fi
3
Figure 7.19 BASIC Stampt' typical ol special-purpose, reprogrammabte, muttiport microprocessors
(Basic Stamp is a registered trademark of Parallax. [nc.)
they are used to drive devices, such as motors, and to operate relays and to send control
signals. To illustrate this class o[ device, Figure 7. 19 shows the BASIC Stamp2o. There
are several versions of this l6-bit, 4-to 20-MHz battery-operated unit, but all offer fully
programmable VO ports that are easily interfaced rvith 5-V TTL-level devices and, with a
control card, are interfaced rvith non-TTL devices. This permits use of sensors and
control of devices ranging from data registers. A./D converters, and alarrns to sensors,
servos, relays, and serial Iines. Comrnunication rvith the microprocessor is also available
through a synchronous three-rvire interface that can couple rvith a serial communication
port, such as on a PC. [t can be prograrnmed using the serial poft to run interpreter-based
software algorithms, rvhich are stored in nonvolatile, reprogrammable memory called
EEPROM (see Memory section)- The utility and portability of such microprocessors is
incredible, with applications ranging ttom multipurpose robots to remote sensing stations.
Program logic controllers (PLC) are rvidely used to measure and output signals and
to perform logic, timing, sequencing. counting, and arithmetic operations in the control of
machines and processes. In this respect, they are similar to Pc-based data-acquisition and
control systems but their simple programming is primarily dedicated
switching operations. They are rugged and stand-alone units.
L
to logic and
7.1
Data-Acquisition Systenr Conrpone nts 263
Process
Output
adlustment
devtce
Data
acquisition
Signal
condrtron ing
Figure 7.20 Closed-loop control concept built around a data-acquisition-based
programmable controller.
Closed-Loop Controller
ln closed-loop control, the controller is used to compare the state o[ a process. as
determined through the value of a measured variable, with the value of a set condition and
to take appropriate action to reduce the dift-erence in value ol the two. This difference in
value is the error signal on rvhich the controller acts. This error can change as part o[ the
dynamics of the process, which causes the measured variable to change value, or because
the set condition itself is changed. The controller action is to adjust the process so as keep
the error to within a desired range.
The control process consists of this sequence: sample, compare, decide, and correct.
An example of a digital control loop is depicted in Figure 7.20. Here the controller
receives input about the process through a sensor that monitors the measured variable.
The controller measures the sensor signal by sampling through an A./D converter or some
digital input. The controller compares the measured value to the set value, computes
the error signal, executes calculations through its control algorithm to decide on the
conection needed, and acts to correct the process. [n this example, we anticipate that the
conective elements are analog based and so the controller sends the necessary signal for
appropriate corrective action at the output of a D/A converter. The controller repeats this
procedure at each cycle. A more extensive treatment ol feedback control is provided in
Chapter 12.
Memory
Memory provides
a
means
to store and retrieve information. Memory
consists of
registers. Registers are locations for the storage of numbers, the basic form of information
storage on a computer. Computers contain three types ol memory: Randoru Access
Memory (P'1.luI), Read-Only Memotl' (RO[O. and external storage device memory
et
264
Chaptcr
7
Fundamentals of Sanipling. Data Acquisirion. and Digital Devices
Figure 7.21 A PC bus is composed of an address bus, data bus, and control
bus.
RAM is memory used to store programs and data during computer operation. RAM is
temporary, reusable memory- ROM is dedicated memory typically used to store the basic
input/output system (BIOS) instructions
of a
computer
or a
dedicated component
algorithm- The BIOS contains tables and machine subrourines related to rhe most basic
operations- Variations o[ these memory forms include Electrically Erasable program-
rutble ROM (EEPROM), u'hich is nonvolatile mernory that n.ray be repeatedly reprogrammed, a useful feature for controlling devices. External memory relers
to peripheral
storage devices, such as hard disk drives, and memory cards.
Central Bus
The path for communication between the CPU and memory and peripheral devices is the
central bus. As depicted in Figure 7.21, the "central bus" is a collective term lor three
information paths: the address bus, the data bus, and the control bus. It can be considered
as a three-lane highway, one lane for each bus, connecting all devices that reside
along
branch roads on the highway. When information or data are to be sent berween devices,
the address bus will contain the address of the device and the location within that device
where the information is to be stored. The data bus rvill contain the execution instructions
or the data being relayed. The control bus sends status information over the central bus.
While information is being sent between any two devices connected to the central bus, a
busy flag is sent out over the control bus to alert all other devices that the data bus is busy.
This allows devices of different speeds to operate over the same lines.
7.8
ANALOG INPUT_OUTPUT COMMUNTCATTON
Data-Acquisition Boards
Analog interfacing with a computer is most often aft-ected using a general purpose DAS yO
board. Typical units are available in the form of an expansion plug-in board or a pCMCtA
card (Personal Computer Memory Card International Association). So the discussion
narrows on these devices. A layout of a typical board is given in Figure i.22. These
boards use an expansion slot on the computer to interface with the computer bus. Field
d
78
Analog [nput-OutputConrmunication 265
I
Figure 7.22 Typical layout for a data-acquisition plug-in board.
(Courtesy of National Instruments, Inc.)
wiring lrom transducers or other analog equipment is usually made to a screw terminal
board with subsequenr connecrion directly to rhe rear of the vo board. A typical
board allows for data transfer both to and from the computer memory using A/D
conversion, D/A conversion, digital Uo, and counter/timer ports. A multipurpose, multichannel high-speed data-acquisition board is shown in Figure 7.23.Hadware setup and
amplifier gain are set either manually, by a resistor jumper such as in Figure 7.24. or by
software controlled su,itches.
For example, the board in Figure 7.23 uses a [6-channel multiplexer and instrument
amplifier. with its l2-bit successive approximation A/D converrer with an 8-9-ps
conversion rate and its 800-ns sample-hold time, sample rates of up to 100,000 Hz are
possible. lnput signals may be unipolar (e.g..0-t0V) or bipolar (e.g., *5v). For the
board shown, this allows input resolution for the l2-bit converter with an Eese:10 v
range of approximately
o
: gi:!
:
2M
to,y
2t)
: 1.44 mV
The amplifier permits signal conditioning with gains from G :0.5 to 1000. This improves
the minimum detectable voltage when set at maxinrum gain to
,ru:
Epsn
(G)(z\:-
lOV
{toog12,1
:2'44ttY
Digital VO can usually be accomplished through these boards for instrumenr control
applications and external triggering. For the board shown, l6-TTL compatible lines are
available allowing for one 8-bit output and one 8-bit input line.
c(
266
Chlpter
7
[runcltrrticntals
of Samptirrg. Data .A.cquisition. antl Digirat Devices
7.23 Photograph of a drta-acquisition plug-in board. (Courtesl,
ol
National lnstruments.
Single- and Differential-Bnded Connections
Analog signal input conncctions to a DAS board ma1' be single or dift'erential ended.
Sittgle-e:rtdecl connection.t use only one signal line (* or HICH) that is nteasured relative
to ground (GRD), as shown in Figure 7.25. The return line (- or LOW) and ground are
connected together. There is a comrnen external ground point, usually through the DAS
board. lvlultiple single-ended connections to a DAS board are shorvn in Figure 7.26.
,umper prns
Jump€r block
Prns J 1 and J2 are to be connected
Ltigure7.24 A resistor jumper block
7.8
Io
To tuD
A/D
t/o
t/o
connector
connector
(c
Anatog lnput-Output Cotnnrunication 267
(b)
)
Figure 7.25 (a) Singte-ended connection. (b) Differential-ended connection.
all of the analog signals can be made
relative to the common ground point. There should be no additional local ground at
the signal source. Single-ended connecting rvires should never be long as they are
susceptible to ElvII noise.
Why the concern over ground points? Electrical grounds are not all at the same
Slngle-ended connectlons are suitable only when
voltage value (see -'Grounds and Ground Loops," Chapter 6). So if a signal is grounded at
nvo ditTerent poinrs. such as at its source and at the DAS board, the grounds could be at
dilferent '"'oltage levels. When a grounded source is wired as a single-ended connection,
the dift-erence bet'"veen the source ground voltage and the board ground voltage gives rise
to a comnen-ntocle t,oLtage (CMIa. The CMV r,vill combine with the input signal
superimposing interference and noise on the signal. This effect is referred to as a
"ground loop." The measured signal will be unreliable.
Dffirential-ervled connedions allow the voltage difference between trvo distinct
input signals to be measured. Here the signal input (* or HIGH) line is paired with a
signal return (- or LOW) tine, which is isolated from ground (GRD), as shown in
Figure 7.25. By using trvisted pairs, the effects of noise are greatly reduced. A
cRD
Source
Multiplexer
Data-acquisition board
Figure 7.26 lv{ultiple single-ended analog connections to a data-acquisition board
268
Chapter
7
Fundanrentals of Sampling. Data Acquisition. and Digital Devices
Analog
srgnal in
Channel 1N
f
rn.,*n
Channel
t
__-_!
c
I
I
I
Multiplexer
Signal
ground
Shreldedl
block
Figure 7.27 Multiple differential-ended analog connections to a data-acquisition
board-
differential-ended connection to a DAS board is shown in Figure 'l .27 . The measured
voltage is the voltage difference between these two (* and -) lines for each channel.
When signals from various instruments are connected to a single DAS board,
differential-ended connections are usually required. This is also the preferred tvay to
measure low-level signals. Hou,ever, for low-level measurements, a [0-k to 100-kf)
resistor should be connected betrveen the signal return (- or LOW) line and ground
(GRD) at the DAS board. The differential-ended connection is less prone to common-
mode voltage errors. But be careful.
common-mode (CMV) range
if
the measured voltage exceeds the board's
limit specification, you can damage
it!
Special Signal Conditioning Modules
Signal conditioning modules exist for different transducer applications. These connect
betrveen the transducer and the data-acquisition card. For example, resistance bridge
modules allorv the direct interfacing of strain gauges or other resistance sensors through
an on-board Wheatstone bridge, such as depicted in Figure 7.28. Temperature modules
allow for electronic thermocouple cold junction compensation and can provide for signal
linearization for reasonably accurate (down to i0.5"C) temperature measurements.
Data-Acquisition Triggering and Sample Sequence
With DAS boards, data acquisition can be triggered by software command, external pulse,
or on-board clock. The acquisition mode is sequential, one channel at a time. The channel
order of acquisition can be programmed on most boards. Normally, measured signals on
adjacent channels are separated by the sample time increment, 6r. Some systems
incorporate multiple A/D converters to allow for the simultaneous sampling of an
equal number of channels at high sample rates. In such arrangements, all channels are
measured simultaneously at each sampling with each channel's data points separated in
time by the sample time increment.
ob
1.g
Digitat tnput-Output Comrnunication 269
P
c
b
U
s
Figure 7.28 A strain-gauge interface. Gauges are connected by rvires to the interface
7.9
DTGTTAL TNPUT_OUTPUT CONTNIUNTCATTON
Certain standards exist for the manner in u,hich digital information is communicated
berrveen digitat devices t5, 61. Serial communication methods transmit data bit by bit.
Parallel communicarion methods transmit data in simultaneous groups of bits, for
example, byte by byte. Both methods use a handshake, an interface procedure. which
conrrols the data transfer betrveen devices and TTL-level signals. Most lab equipment can
be equipped to contmunicate by at least one of these means, and standards have been
defined to codify communications between der.ices of different manufacturers.
SeriaI Communications
RS-232C
The RS-232C prorocol, rvhich was initially set up to translate signals between telephone
lines and computers via a modem (modulator-denlodulator), is an interface for communication bet',veen a computer and any serial device. Basically, the protocol allows twoway communicarion using two single-ended signal (*) wires, noted as TRANSMIT and
RECEIVE, berrveen data-communications equipment (DCE), such as the modem or an
instrument, and data terminal equipment (DTE), such as the computer. These trvo signals
are analogous to a telephone's mouthpiece and earpiece signals. A signal GROUND
wire allorvs signal return (-) paths. The remaining wires in the original standard are used
to assess the state of the signal lines.
270
Ctrapter
25
7
Fundamentats of Sampling. Data Acquisition, and Digitat Der.ices
prn
Number
Descflption
(DIE)
I
2
3
:1
5
6
7
8
l5
l7
20
22
Protective ground
rransmitted data (TD)
Received data (RD)
Request to send (RTS)
Clear to send (CTS)
Data set ready (DSR)
Srgnal ground (GRD)
Data carrier detect (DCD)
lransmit signal element timing
(TSET)
Receive signal element taming (DTR)
Data terminal ready (DTR)
Ring indicator (Rl)
Figure 7.29 Standard
RS-232C assignments to
13
a 25-pin connector.
Most PC computers have an RS-232C compatible I/O port. The popularity ol rhis
interface is due to the wide range of equipment that can utilize it. Either a 9-pin or 25-pin
connector can be used. The full connection protocol is shown in Figure 7.29. Ofticially,
devices may be separated by distances up to about l5 m, but in practice longer distances
seem to rvork iI using a well-shielded cable. Communications can be half-duplex or fullduplex. Half-duptex allows one device to transmit while the other receives. Fult-duplex
allows for both devices to transmit simultaneously.
The RS-232C is a rather loose standard, and there are no strict guidelines on how to
implement the handshake. As such, compatibility problems will sometimes arise. The
minimum number of rvires required between DTE and DCE equipment is the three-r.vire
connection shown in Figure 7.30. This connects only the TRANSMIT, RECEIVE, and
GROUND lines while bypassing the handshake lines. The handshaking tines can be
junipered to fool either device into handshaking rvith itself thereby a[[or.r'ing the
communication.
Communication betrveen similar equipment, DTE to DTE or DCE, to DCE, needs
only the nine lines connected as shown in Figure 7.31, so a nine-pin conncctor can be
used. The nine-pin connector wiring scheme is shown in Figure 7.32.
2O-
-+J-2
3070-
-o3
€7
Figure 7.30 Minimum serial connections between DTE to
DCE, or DTE to DTE equipment (RS-232C).
9-prn
Number
Description
I
2
3
4
5
6
7
8
9
Shell
Data carrrer detect (DCD)
fransmrtted data (TD)
Received data (RD)
Data termrnal ready (DTR)
Signat ground (GRD)
Data set ready (DSR)
Request to send (RTS)
Clear to send (CTS)
9
I
6
Ring lndicator (Rl)
Chassrs ground
G',d,
Figure 7.31 Standard serial connections
between DTE to DTE or DCE to DCE
equipment using a nine-pin connector
(RS 232-C).
t-
Pin number
Devrce
L
9
Digrtal tnput-Ourput Conlntunicarion 271
Prn number
Devrce 2
I
2
3
J 1
5 j---__--l
g --------.---
14
5
g
6
9
6
9
7
7
Figure 7.32 Nine-rvire serial connection betrveen DTE
to DTE or DCE to DCE equipmcnt.
-
Serial communication implies that data are sent in successive streams of information,
one bit at a tirne. The value o[each bit is represented by an anatog voltage pulse with a I
and 0 distinguished by trvo equal volrages of opposite polarir), in the .i-to 25-V range.
Communication rates are measured in baud, which relers to the number of signal pulses
per second.
A typical asynchronous transmission is l0 serial bits comprised of a start bit follorved
by a 7-or 8-bit data stream, either one or no parity bit, and terminared by t or 2 stop bits.
The start and stop bits lorm the serial "handshake" at the beginning and end oFeach dara
byte. Asynchronous transmisslon means that inforrnation may be sent at randon intervals.
So the start and stop bits are signals used to initiate and to end the transmission of each
byte of data transmitted. The start bit allorvs for synchronizarion ol the clocks of the trvo
communicating devices. The parity bit alloivs for limited enor checking. Pari4, involves
counting the number of I's in a byte. In I byte of data. there ri'ill be an even or odd
number of bits rvith a value of l. An additional bit added to each byte to make the number
of I bits a predeterntined even or odd number is called a parity bit. The receiving device
rvill count the number of transmitted bits checking lor the predetermined even (even
parity) or odd (odd parity) number. Ia st'nchronous transmissirrrr, the two devices will
initialize synchronize communication '"vith each other. Even rvhen there is no data to
send, the devices will transmit characters just to rnaintain synchronization. Stop and start
bits are then unnecessary allowing lor higher data transfer rates.
Devices that ernploy data buffers, a region of preassigned RAM that serves as a data
holding area, rvill use a softrvare handshaking protocol such as XON/XOFF. With this, the
receiving device rvill transmit an XOFF signal to halt transmission as the buffer nears
and an XON signal when it has emptied and is again ready to receive.
full
RS-422Lt423N449/48s
RS-422A1423A provide recommendations lor the electrical interface, and RS-449
specifies functional and mechanical characteristics of a serial communication standard.
Equiprnent designed tbr RS-232C can be used with these standards with stight modification. Using a 37-pin connector and differential-ended cotinections to reduce noise, they
allorv for communication at rates up to 2-M baud and distances up to 1000 m. The
standard uses a l-5 V TTL (transistor-transistor logic) pulse signal to distinguish between
a I bit (+2:+5.5 V) and a 0 bit (-0.6:+0.8 V).
The RS-485 protocol allows for multidrop (allorvs up to 32:255 devices on one line)
operation that is well suited to local area netrvorks (LAN). It communicates in halfduplex along a two-wire bus rvhich makes it slower than RS-.122.
od
272
Chapter
7
Fundanrentals of Sampling, Data Acquisition. ancl Dicital l)evices
Prn
number
Descflption
Datd lanes
1
2
3
4
L3
T4
15
t6
Digttal l/O data Ine I
Digital l/0 data line 2
Digital
Digital
Digital
Digital
Digital
Digital
Handshake lines
6
7
8
Bus management lines
5
9
lo
UO data lrne 3
l/O data line 4
l/O data Ine 5
l/O data line 6
UO data
line 7
l/O data line
I
Data valid (DAV)
Not ready for data (NRFD)
Not data accepted (NDAC)
End or identify (EOl)
lnterface clear (lFC)
Service request (SRQ)
II
Attention
L7
Remote enable (REN)
(ATN)
Cround lrnes
l2
t8-24
Shield
Ground
Figure 7.33 CPIB bus assignments to a 25-pin
connector.
Universal Serial Bus and IBEB 1394
The universal serial bus (USB)permits periphe':al expansion fo5 up to 128 devices at lowto high-speed data transfer rates. The original USB (USBl.0/l.l) supports transfer rates
[r'om 1.5Mbs up to l2Mbs, and the high-speed usB (usB2.0) supports rares up to
480 Mbs. The USB supports a "hot srvap" feature that allorvs the user to plug in a USBcompatible device and to use it without reboot. This bus connects USB devices to a single
computer host through a USB root hub. The IEEE 1394 standard defines a high-speed
serial bus, which is also called Firevtire, supporting transler rates upto 400 Mbs betrveen
devices.
The USB physical interconnect is a tiered star topology. In this set-up, the root hub
permits one to four attachments, which can be a combination of USB peripheral devices
and additional USB hubs. Each successive hub can in turn support up to four devices or
hubs. Cable length between a device and hub or bet'uveen two hubs is limited to 5 m for
USB and 4.5 m for IEEE 1394. The connecting cable (Figure 7.33) is a four-line wire
consisting of a hub power line, two signat lines (+ and -), and a ground (GRD) line.
IEEE 1394 uses six wires consisting of two pairs of signal lines and two power lines.
Parallel Communications
cPrB (rEEE-488)
The general purpose interface bus (GPIB) is a high-speed parallel interface. Originally
developed by Hewlett-Packard, it is sometimes relerred to as rhe HP-IB. The GPIB is
usually operated under the IEEE-488 communication standard. The bus allows for the
control of other devices through a central controller, and it allows devices to receive/
transmit information from./to the controller. This standard is wetl defined and widely
used to interface communication between computers and printers and scientific
instru mentation.
ob
7.()
Digital tnput-Output Comtnunication 273
Power
Srgnal (+)
Srgnal
(-)
-
(a)
(6) Wrrrng connectroo
Star topology
Figure 7.34 Cable configuration tbr the Universal Serial Bus (USB)
The IEEE-488 standard for the GPIB operates from a [6-wire bus with a 24-wire
connector (Figure 7.34). A 25-pin connector is standard. The bus is lormed by eight data
tines plus eight lines for bus management and handshaking (two-rvay control communication). The additional eight lines are used for grounds and shield. Bit paratlel, byte
serial communicarion at data rates up to 1 Mbytes/s are possible, with 1:10 kbytes/s most
common. Connector lines are limited to a length of roughly 4 m.
The standard requires a controller, a function usually served by the laboratory
computer, and perrnits muttidrop operation, allowing up to l5 devices to be attached to
the bus at any time. Each device has its own bus address (addresses l-14). The bus
controller (address 0) controls att the bus activities and sequences al[ communications to
and between del,ices. such as ivhich bus device transmits or receives and when. This is
done along the bus management and handshaking lines. The communication along the
bus is bidirectional. Normally, ground true TTL logic (<0.8 V HIGH' > 2V LOW) is
used.
The IEEE-488 standard specifies the following:
Data Bus: This is an 8-bit parattel bus formed by the eight digital input-output data
lines (lines l-4 and 13-16). Data are transmitted as one S-bit byte at a time. The
handshake and bus management lines communicate through the transmission of a HIGI-{
or LOW signal along the line. A HIGH signal asserts a predetermined situation.
Handshake Brrs.' A three-wire handshake is specified. The Data Valid line (line 6)
asserts that data are available on the data bus and are valid. The Not Ready
for Data line
(line 7) is asserred by a device until it is ready to receive data or instructions. The Nor
Data Accepted line (line 8) is asserted by a device until it has accepted a set of data. To
illustrate the handshake concept, consider the handshake between a conl-roller (computer)
and a measuring instrument. The controller unasserts NRFD indicating that it is ready to
accept data. When ready, the measuring instrument asserts DAV indicating to the
controller that valid data are being sent over the data bus. When the controller has read
and accepted thc data, it unasserts NDAC.
Bus Managenrelrt.' There are five lines reserved to manage the flow of information on
the data bus. The tnte(ace Clearline (line 9) is used by the controller to clear devices.
such as during the initiat boot. The Senice Request line (line l0) is used by a device to
assert that it is ready to be serviced by the controller, such as when it is ready to transmit
data. The Attention line (line I [) asserts that the data on the data bus are commands from
the controller, devices are not to transmit. A low signal allows device messages onto the
oe,
27J
Chapter
7
Fundanrentals
of
Sampling, Data Acquisition. and Digital Dericcs
data line, such as the device data readings.The End or ltlent(r'Iinc tline 5) is used by the
transmitting de'uice to indicate the end ol a data transmission. \\'ith the Attention line
asserted. it is used by the controller to poll its de"ices to determine rihich derice asserted
itiService Request. The Rentote Enable line (line l7t is used b_v the controller to place a
device in its remote mode. When asserted, the tl'ont par.rels ol tlie clevice are deactivated
and the controller has command over device programming.
The interplay betu,een the controller and the devices on the bus is controlled b1'
software prograns. Most scientific devices rell'on sotnrare drirers, nlan)i of these are
built around menu-driven programs, which are designed to provide :omc tlexibility in the
specitic set-up or operating parameters of the der,'ice.
Although a parallel interface is more costly than a serial interface, the GPIB allou,s
multiple devices to be attached to a single computer, microprocessor, or network through
a common interface, lowering overall cost. [t is faster and more efficient at data transfer
than a serial interface. The parallel interface and 8-bit data bus is similarto those used by
microprocessor buses and more readily adapted.
EXAMPLE 7.7
A strain transducer has a static sensitivity of 2.5 Viunit strain (2.5 pV/pe) and requires a
suppty voltage ol5VDC. It is to be connected to a DAS having a t5 V. l2-bit A/D converter
and its signal measured at 1000 Hz. The transducer signal is to be amplified and filtered.
For an expected measurement range of 1-500pe, specify appropriate values for amplifier
gain, filter type and cut-offfrequency, and shor.v a signal llon diagran'r tbr the connections.
olf the dataacquisition board and routed to the transducer. Transducer signal n ires are shielded and
routed through the amplifier, filter, and connected to the data-acquisition board connector
block using twisted pairs to channel 0, as shorvn. Ttie ditterential-ended connection at the
btlard rvill reduce noise.
The amplifier gain is determined by considering the mininrunr and nraxirnum signal
magnitudes expected, and the quantization effor of the DAS. The norninal signal
magnitude rvill range from 2.5prV to 1.25 mV. An arnplifier gain ol G: 1000 q'itl
SOLUTION The signal florv diagram is shown in Figure 7.3i. Pouer is drawn
boost this from 2.5 mV to 1.25 V. This lorver value is on the order of the quantization
error of the l2-bit converter. A gain of G : 3000 rvill raise the lou end o[ the signal out of
quantization noise rvhile keeping the high end out of satLrration.
DATA ACQUISITION BOARD
con nector
block
OUI
+5V
cHZHt +
CHALd
8Hl
IRANSDUCER
(Grounded Source)
+
cHI Ht
AMPLIFIER
AND
FILTER
CH
Figure 7.35 Line connections for Example 7.7
@d
I
Lol
9Hl -
stcNAL
TOA/D
...
7.9
Digital tnput-Output Comnrunication
275
With a sample rate ofl : 1000 Hz, an anti-alias. lorv-pass Butterrvorth filter rvith t 2
dB/octave roll-off and a cutoff frequency set atfv:500 Hz would meet the task.
EXAMPLE 7.8
The output ttom an analogdevice (nominal output impedance of 600 W) is input to the
l2-brt A/D converter (nominal input impedance of I MW) of a data-acquisition system.
For a l-V signal, will interstage loading be a problem'l
I(rvOltN
Zt
:600Q Z^: IM{l Et = 2Y
FIND
eI
SOLUTION The loading error is given by €r
:
E^
-
81, where E1
is the true voltage and E^, is
the rneasured voltage. From equation (6.39),
er:
Er(oh,-r) : -r 2mV
The interstage loading enor at 2-V input actually rvill be less than the f2.4-mV
quantization error of the l2-bit device.
EXAMPLE 7.9
An analog signal is to be sampled at a rate of 200 Hz rvith a l2-bit A./D con!'erter that has
an input range of - t0 to l0-V input range. The signal contains a 200-Hz component,.fl,
u'ith an amplitude of 100 mV. Specify a suitable LC filter that will attenuate the 200-Hz
component down to the A/D converter quantization resolution level and rvill act as an
anti-irlias fi lter for quantization.
KNOIIiV
f' : 100 Hz
I :200 Hz Ar : 100 mV
Ensn:10V M:12
FIND Specify a suitable filter
SOLUTION Frorn equation (7.8), forf,:200H2,f* is 100 Hz. So an appropriatedesign flor an
anti-alias filter would have the properties oft: 100 Hz and M (100 Hz) = -3 dB. The
A/D converter quantization resolution level is
o
For
a
: E2M
:,* :'9',:
4096
100-mV signal at 200 Hz, this requires
4.88
mv
a low-pass Butteru,orth filter with
an
attenuation of
M(200",)
:1##:0.0488
:
or
t
(or
-
26dB)
fr* lf,frl-'": l, +effi/ roo)'*]
(f
= 4.3 = 5. Appropriate values for L
oGt
and C can be set from Table 6.
t/1
t
and Figure 6.30.
276
Chapter
7
Fundamentars
of Sar.pring, Data Acquisition, and Digitar Der.ices
EXAMPLP 7.10
-
To consider how the GPIB lines might be used, suppose u,e wish to use a computer to
instruct a !'oltmeter to take a reading and display ir. In thls case, the computer acts as the
controller and transmits commands to the \,oltmeter, the receiver. With bus addresses
set
by software to: Transmit address :0. Receive address : 3, the process begins rvith the
Attention line I I set HIGH (this halts activity white the bus devices listen to rhe computer
commands):
C :Computer; DV : voltmeter)
C : Initialize all devices : Line 9 (lFC) HIGH then LOW.
DV: voltmerer Ready (to receive instructions) : Line 7 (NRFD) Low.
(Below
C
:
:
Computer Sends Instrucrions: Line 5 (EOI) HIGH.
The computer addresses the voltmeter. The eight parallel data lines become active
instructions are sent to the voltmeter. Instructions are 7- or 8-bit ASCII codes using
as
DI0l-
8.
DV:
Voltmeter Acceprs
:
Line 8 (NDAC) LOW.
The voltmeter indicates it accepts the instructions.
DV:
Voltmerer Acrive: Line 7 (NRFD) HIGH.
The voltmeter takes a reading. The line 7 status informs the computer that the
voltmeter is busy so no new instructions should be sent.
DV
:
Voltmeter Ready: Line 7 (NRFD) LOW.
The voltmeter now displays its new reading.
Ttris signals that the voltmeter awaits new instructions. The next instruction might be
to t"nd th" n"ru ."uding ulong th" dutu lin"r to b" ,tor"d in .olpul", *"-ory.
7.LO SUMMARY
This chapter has focused on sampling concepts, the interfacing of analog and digital
devices' and data-acquisition systems. Despite the advantages of digital sysrems, they
must interact with an analog world, and the back-and-forth exchange between an analog
and digital signal has limitations. With this in mind, a thorough discussion has been
provided on the selection of sample rate and the number ol measurements required to
reconstruct a continuous process variable from a discrete representation. Equations 7.1
and 7 -9 explain the criteria by which a periodic waveform can be accurately iepresented
by such a discrete time series. The limitations resulting from improper sampling and the
discrete representation include frequency alias and leakage, and amplitude ambiguity.
The fact that practically any electrical instrument can be interfaced with
a
microcontroller or a data-acquisition system is significant. The working mechanics of
analog-to-digital and digital-to-analog converters is basic to interfacing such analog and
digital devices with data-acquisition systems. The limitations imposed by the resoiution
and range of these devices mandate certain signal conditioning requirements in terms of
signal gain and filtering prior to acquisition. These require analog amplifiers and filters,
devices discussed previously. Communication between digital devices surrounds us. But
their proliferation means that standards for communication must be set. These standards
are evaluated and replaced as newer devices demand faster data transfer.
bo
Nontenclature 277
REFERENCES
l.
Bendat, J., and A. Piersol, Random Data: Anall'sis and Measurement Proceclures.
Wiley-lnterscience, New York. 197 l.
2. Stanlej, \\'. D.. G. R. Dougherty, and R. Dougherty, Digitut Signal processing,zd ed.,
Reston (a Prentice Hall company), Reston, VA. 1984.
3.-Lyons, R., Understanding Digitat Signal Processing,2d ed., Prentice-Hall, Englewood
Clitfs, 2004.
4. Vandoren, A., Data-Acquisition S1'stenrs, Reston (a Prentice Hall company), Reston,
vA,
1982.
5. Krutz, R.. Interfacing Techniques in DigitaL Design: Emphasis on Microprocessors,
Wiley, New York, 19886. Hnatek, E., A User's Handbook of D/A and A/D Converters, Wiley-Inrerscience, New
York, 1976.
7. Money. S. A., Microprocessors
York,
in Instrumentation and Control, McGraw-Hil[, New
1985.
Suggested Reading
Ahmed, H-, and
P. J.
Spreadbu ry, Analogue and Digital Electronics for Engineers,2d ed-,
Cambridge University Press, Cambridge, UK, 1984.
Beauchamp, K-G., and C.K. Yuen., Data Acquisitionfor Signal Analy-sis,Allen & Unu,in,
London,
1980.
Evans, Alvis J., J. D. Mullen, and D. H. Smith, Basic Electronics Technology, Texas
lnstrumenrs [nc., Dallas, TX, 1985.
Seitzer, D-, G. Pretzl, and N. Hamdy., Electronic Analog-to-Digital Converters: Principles, Circuits, Devices, Testing, Wiley, Neu, york, 1983.
Wobschatl, D., Circuit Design
for
Electronic Instruntentation: AnaLog and Digitat
Hill. New york, 1979.
Devices from Seisor to Displa1,, McGraw
NOVTENCLATURE
e
eq
f
f"
f.
.fn,
"f,
f,
k
t
)'(t)
erTor
Eo
quantization error
frequency [r-t]
alias frequency [r-t]
Ensn
G
1
filter cutoff frequency [r-r]
M
maximum analog signal frequency [r-l] MA
Nyquist frequency [r-r]
N
sample rate frequency [r-'l
N 6t
cascaded filter stage number
R
time [rl
O
analog signal
6/
y,, y(r6l) discrere values of a signal,
5R
1'(r)
{1,(r 6t)f complete discrete time signal of y(r)
6t
A
amplifier open loop gain; also, constant t
E
voltage [V]
AA
Ei
input voltage [V]
bo
output voltage [V]
full-scale analog voltage range
amplifier gain
electric current [Al
digital component bit size
magnitude rario at frequency/
data set size
total digital sample period [l]
resistance [0]
A,/D converter resolution [V]
frequency resolurion of DFT
change in resistance [fl]
sample time increment [r]
time consrant [/l
phase shift at frequency/
[r-t]
278
Chapter
7
Fundamentals
of
Sanrpting. Data Acquisition. and Digital Devices
PROBLEIVTS
For many of these problems. using spreadsheet sotirvare or
the accompanying software
',vill facilitate solution.
Convert the analog voltage. E(ty : 5 sin 2nl nrV into a discrete time signat. Specifically,
using sample time increnrents of (a) 0. 125 s, (b) 0.30 s, and (c) 0.75 s, plot each series as a
function of time over at least one period. Discuss apparent differences between the
discrete representations oI the analog signal.
7.2 Computethe DFT foreach of the threediscrete signals in Problern 7.1. Discuss apparent
ditferences. Use a data set of 128 points.
7.3 Compute the DFT for the discrete time signal that results Frorn sampling the analog
signal, T(t)=2 sin 4nr"C, at sample rates of 4 and 8 Hz. Use adata setof 128 points.
Discuss and compare your results.
7.4 Determine the atias frequency that results from sampling fi at sample rate /s:
7
.l
a. -fr
b. -f,
:60 Hz: f,:
:
90 Hz
1.2 kflz f, :2
kHz
c. "fr: t0 Hz; -f':6
d. ,f, : 16 Hz: f,:8
Hz
Hz
data-acquisition system is used to convert the analog signal, E(t) : (sin 2nt *
2 sin 8nr) V, into a discrete time signal using a sample rate of 16 Hz. Build the discrete
time signal and from that use the Fourier transform to reconstruct the Fourier series.
Consider the continuous signal found in Example 2.3. What would be an appropriate
sample rate and sample period to use in sampling this signal if the resulting discrete series
must have a size of 2'11 ,,r,here If is an integer and the signal is to be filtered at and above 2
7.5 A particular
7.6
tIz?
7.7
Convert the follorving straight binary numbers to positive integer base l0 numbers:
a. l0l0
b. 1ilil
c. l0l I l0l I
d. I 10000t
7.8 Conveft:(a) ll00llt.ll0l(b.inary)intoabasel0number;(b)4B2Fintostraightbinary;
(c) 278.632 (base l0) into straight binary.
7.9 Convert the follorving decinral (base l0) numbers into bipolar binary numbers using
two's complement code:
a. l0
c. -247
b. -10
d.
a
r0 r3
7.10 A
7.lI
personal computer does integer arithmetic in t\^'o's complement binary code. How is
the largest positive binary number represented in this code for an 8-bit byte? Add one to
this number. What base l0 decimal numbers do these represent?
How is the largest negative binary number represented in twos complement code for an 8bit byte. Subtract oue from this number. What base l0 decimal numbers do these
represent?
7.12 List some
possible sources of uncertainty in the dual-slope procedure for A/D conversion.
Derive a relationship bern'een the uncertainty in the digital result and the slope of the
integration process.
7.13 Compute the resolution and SNR tbr an M-bit A/D converter having a full-scale range of
t5 V. Let Mbe4,8, 12, and 16.
7.14 A l2-bit A./D converter having an Ep5p:5 V has a relative accuracy of 0.03Vo FS (fullscale). Estimate its quantization error in volts. What is the total possible error expected in
volts? What value o[ relative uncertainty might be used for this device?
bb
Problerns 279
7.
15 An 8-bit
single ramp A/D converter rvith EFqq: l0 V uscs a 25-MHz clock and
comparator haring a threshold voltage of I mV. Estimate:
(i)
(ii)
(iii)
a
The binary output
the input voltage is E :6.000 V. \\'hen E : 6.015 V.
"r'hen
The actual conversion time for the 6.000-V input and average conversion times.
Tl.re resolution of the converter.
7.16 Courpare the maxirnum
7.17
7.
conversion times of a 1O-bit successive approximation A/D
converter to a dual-slope ramp converter if both use a l-lvlHz clock and Eesn: l0 V.
An S-bit D/A convener shows an output of 3.58 V rvhen straight binary lOtl00 ll is
applied. What is the output voltage when 0l100100 is applied?
18 A 0-10 V 4-bit
successive approximation A/D converter is used to measure an input
voltage of 4.9 V.
(i)
(ii)
7.I9
Determine the binary representation and its analog approximation of the input
signal. Explain your answer in terms of the quantization error of the A/D converter.
[f we rvanted to ensure that the analog approximation be rvithin 2.5 mV of the
actual input voltage, estimate the number of bits required of an A./D converter.
Discuss the trade-offs behr,een resolution and conversion rate for successive approxima-
tion, ralup, and parallel converters.
7.20 A0-10-V, 1O-bitA/Dconvefterdisplaysanoutputinstraightbinarycodeofl0l0ll0tll.
Estirnate the input voltage to rvithin I LSB.
7.21 A +5-V 8-bit A/D converterdisplays an output in twos-complementcode of l0l0l0ll.
Estimate tlie input voltage to rvithin I LSB.
7.22 A dual-slope A/D converter has l2-bit resolution and uses a l0-kl-Iz internal clock.
7.23
Estirnate the conversion time required for an output code equivalent to 20 111s.
Hou' long does it take an S-bit single ramp A./D converter using a 1-MHz clock to convert
the number 173111?
7-21 A
successive approximation A/D converter has a full-scale output ol 0-10 Vand
8-bit register. An input ol 6.2 V is applied. Estimate the final register value.
7.25
uses an
The voltage from a 0-to 5-kg strain gauge balance scale is expected to vary from 0 to 3.50
mV. The signal is to be recorded using a l2-bit A/D converter having a *5-V range rvith
the weight displayed on a computer monitor. Suggest an appropriate ampli{ier gain for
this situation.
7.26 An aircraft n,ing will
oscillate under rvind gusts. The oscillations are expected to be at
about 2 I{2. Wing mounted strain gauge sensors are connected to a *5-V l2-bit A/D
con\ielter and data-acquisition system to measure this. For each test block, l0 s ofdata are
sampled.
(i)
(ii)
(iii)
Suggest an appropriate sample rate. Explain.
[f the signal oscillates rvith an amplitude of 2 V, express the signal as a Fourierseries.
Based on (i) and (ii). sketch a plot of the expected amplitude spectrum. What is the
frequency spacing orr the abscissa? What is its Nyquist frequency?
7.27 An electrical signal frorn
7.28
a transducer is sampled at 20,000 Hz using a l2-bit successive
approximation A/D converter. A total of 5 s of data are acquired and passed to computer
memory. Ho."r' nruch l6-bit computer memory (in kbytes) is required?
Ho"v many data points can be sampled by passing a signal through a l2-bit parallel A/D
convefter and stored in cornputer memory, if 8 MB of 32-bit computer memory is
available? If the A/D converter uses a 100-MHz clock and acquisition is by DMA,
estimate the duration of, signal that can be measured.
ben
280
Chaptcr'
7
[juncl:irnentals
ot santpling. L)ata Acquisition, and Digital
Devices
sarnple rate and clata number to acquire-with minimal leakage the
first five rerrns ol' a square rvave signal having a furtdamental period of I s. Selcct an
appropriate cutotT frequency fbr an anti-alias frlter. Hint: approximate the square \\'ilvc as
1.29 Select an appropriate
a Fourier series.
7.30 A triansle
u ar,e rvith a pcriod
.v(r)
of 2 s can be expressed by the Fourier
: 1122,(l -
cos nn)f
nnlcosnnt
n
:
1.2'.
series,
-
Specify an appropriate sample rate and data number to acquire the first seven terms wittr
minin.ral leakage. Select an appropriate cutoff frequency lor an anti-alirs filter.
7.31 Using Fourier transform sotiware (or equivalent sothvare), generate the arnplitude
spectrum tbr Problem 7.29.
7.32 Using Fourier transtbrm software (or equivalent softn,are), generate the amplitirde
spectrum tbr Problem 7.30. Use Dr : t V.
7.33 A single-stage low-pass RC Butterworth filter with/.: 100 Hz is used to tllter an analog
signal. Derermine the attenuation of the filtered analog signal at 10, 50, 75, and 200 Hz
7.34 A three-stage LC Bessel filter with -f":100 Hz is used to filter an analog signal'
Derermine the artenuation of the filtered analog signal at 10, 50, 75, and 200 Hz.
7.35 Design a cascading RC Butterworth low-pass filter that has a magnitude ratio flat to
within 3 dB from 0 to 5 kHz but with an attenuation of at least 30 dB lor all frequencies at
and above t0 kHz.
7.36 A complex periodic analog signal consisting of frequencyfl and its harmonics is to be
sampled at 500 Hz. The signal is passed through a low-pass single-stage RC Butteru'orth
filter rate{ ar -3 dB at250Hz. What is the maxirnum frequency in thefiltered signal for
r',,hich the amplitude will be aft'ected by a dynamic error of no more than l07ol
7.37 Choose an appropriate cascading low-pass filter to remove a 500-Hz componcnt
7.38
contained rvirhin an analog signal which is to be passed through an 8-bit A/D converter
having l0-V range and 200-Hz sample rate. Attenuate the component to r'vithin the A/D
converter quantization error.
The voltage output from a J-type thermocouple referenced to 0'C is to be used to nleasure
remperatures lrom 50 to 70'C. The output voltages will vary linearly over this range lront
2.585 to 3.649 mV.
a. [f the thermocouple voltage is input to a 12-bit A/D converter having a *5-V range.
estimate the percent quantization error in the digital value.
b. tf the analog signal can be first
passed through an amplifier circuit, compute the
amplifier gain required to reduce the quantization error to 57o or less-
c. If rhe rario ol signal-to-noise
7.39
level (SNR) in the analog signal is 40 dB, compute the
magnitucle of the noise after amplification. Discu5s the results of (b) in light ol this.
Specily an appropriate +5-V M-bit AJD converter(8- or l2-bit), sample rate (up to 100
I{z) and signal conditioning to convert these analog signals into digital series. Estimate
the quantization error and dynamic error resulting flrom the system speci{ied:
a. E(t): 2 sin 20rt Y
b. E(t): 1.5 sin ftt + 20 sin 32nt - 3 sin (60nr * nl4) Y
c. P(/) : - l0 sin 4nl*5 sin Snr psi; K:0.4 V/psi
7.40 The follorving signat is to be sarnpled using a 12-bit, +5-V data-acquisition
)'(r)
:
4 sin 8nr
*
2sin Z0nt
*
board
3 sin 42trt
Select an appropriate sample rate and sample size that provide minimal spectral leakage-
Problcrrrs 28 I
7.41 Static
pressures are to be measured at eight locations unclcr the hood of a NASCAR race
car. The pressure transducers to be used have irn output span ot' -r I V tbr an input span of
cm HlO. The signals are nreasured and recordcd on a portable DAS rvhich uses a l0bit. t5-V A/D converter. Plessurc neecls to be resolved to u'ithin 0.25 cn-r H2O. The
tl5
d1'narnic content of the signals is iniportant and has a tundamcntal pcriod of about 0.-i s.
The systeur has -l-MB memory, po\\'ers alI instrun.rcnts. and has l0 min of usable batterl'
lit'e. Suggest an appropriate sarnple rate. total sample tirne. and signal conditioning lor
this application. Sketch a signal florv diagram through ttre measurement systern.
7.4 I has a rated accuracy of 0.2-i7o. Estimate the design stagc
uncertaintl, of the transducer-A/D convertel systenl based on knorvn information. Would a
Il,-bit converter improve things notably? If follorving measurements the engineer notes a
0. l0 cm [{2O uncertainty due to data scatter alone, u,hat uncertainty dominates thc
7.42 The transducer in Problern
7.43
measuretrlent?
A strain gauge sensor is used rvith a bridge circuit and connected to a DASas indicateci iu
Figure 7.17. Estimate the range of offset nulling voltage available ii: The bridgt:
excitation is 3.333 V sensor and bridge resistors are each at a nominal value of 120 Q.
and the adjustable trim potentiometer is rated at 39 kQ.
7.44 Design a lorv-pass Butter\l,orth filter around a l0 Hz cut-off (-3 dB) frequency. The filter
is to pass 957a of signal magnitude at -5 [{z but no more than l07o at20Hz. Source and
load impedances are l0 Q.
7.45 A two-stage LC Butterworth filter u,ith/"=
100 Hz is used as an anti-alias filter lor tn
at 10, 50, 75, and 200 Hz
analog signal. Determine the signal attenuation experienced
The lollowine problems make use of the accompanying softrvare.
7.16 InthediscussionsurroundingFigureT.4,rvepointouttheef'fectsofsamplerateandtotal
7.47
7.48
7
.49
sanrple period on the reconstructed time signal and its amplitude spectrum. Use progrant
Leaktge to duplicate Figure 7.-1. Then develop a similar exarnple (signal flrequency.
sanrple ratc. and sample period) in u,hich fewer points and a slou,er sample rate lead lo a
better reconstruction in both time and frequency domains. lncidentally, for a fixed sarup[e
rate. you can increment N and rvatch the acquired rvavefornt develop such that the
leakage decre:rses to zero as the acquired signal reaches an exact integer period of the
u,a','eform. For a fixed N, the same can be shown for changes in sample rate.
Using program Aliasing solve Example 7. I to find the alias frecluency. Observe the plot of'
the original and the acquired signal, as rvell as the amplitude spectrum. Decrement thc
signal frequency 0. I llz at a tirne until within the region where there no longer is aliasing,.
Based on these observations, discuss horv the acquired time signal changes and holv tl'ris
is related to aliasing.
Use program Aliasing to understand the folding diagram ol Figure 7.3. For a sample rate
ol l0 Hz, vary the signal lrcquency over its full range. Determine the frequencies
correspondlng to,fN, 2fu, 3fp, and 4f11 on Figure 7.3. Deterrnine the alias frequencies
corresponding to 1.6$,', 2 LfN. 2 6f^-, and 3.2fp.
Using progra m Signal_C7 exarnine the rule that when exact discrete representations ale not
possible, then a sample rate of at least 5 times the maximum signal frequency should be
used. Select a sine wave ol 2Hz and discuss the acquired rvaveform as the sample rate is
increased incrementally from a lorv to a high value. At what sample rate does the signal look
like a sine rvave? Compare with the corresponding frequency and amplitude content from
the amplitude spectrum. Write up a short discussion of your observations and conclusions.
7.50 Program l-eokagc samples a single frequency signal at a user-defined
sample rate and
period. Describe how sample period corresponds to the lengttr of the signal measured and
hoiv this affects leakage in the amplitude spectrum. Does frequcncy resolution matter?
bd