DK-DEV-5CSXC6N Dev Kit Schematic

8 7 6 5 4 NOTES: E 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing Schematic Drawing PCB Film Bill of Materials Schematic Design Files Functional Specification PCB Layout Guidelines Assembly Rework 3 REV DATE PAGES A1 09/27/2012 All 2 1 DESCRIPTION INITIAL REVISION A RELEASE Preliminary Schematic DO NOT COPY 100-0321003-A1 110-0321003-A1 120-0321003-A1 130-0321003-A1 140-0321003-A1 150-0321003-A1 160-0321003-A1 170-0321003-A1 180-0321003-A1 210-0321003-A1 220-0321003-A1 320-0321003-A1 E 2. 1172 Parts, 88 Library Parts, 1330 Nets, 6643 Pins Cyclone V SoC FPGA Development Kit Board D C B PAGE DESCRIPTION 1 Title, Notes, Block Diagram, Rev. History 30 Power 5 - Linear Regulator 2 FPGA Package Top 31 Power 6 - Power & Temp Monitor 3 PCI Express Edge Connector 32 Power 7 - Cyclone V GX SoC Power 4 Cyclone V GX SoC Bank 3 33 Power 8 - Cyclone V GX SoC GND 5 Cyclone V GX SoC Bank 4,5,6 34 Decoupling 6 Cyclone V GX SoC Bank 7 7 Cyclone V GX SoC Bank 8 8 Cyclone V GX SoC Transceiver Banks 9 Cyclone V GX SoC Clocks 10 PLL 11 Cyclone V GX SoC Configuration 12 JTAG 13 DDR3 - Part 1 of 2 14 DDR3 - Part 2 of 2 15 QDRII+ SRAM 16 RLDRAM II CIO 17 Flash 18 5M2210 System Controller 19 QSFP Interface 20 Display Port (x4) 21 SDI TX Cable Driver & SMB 22 HSMC Port A & Port B 23 Ethernet PHY & RJ-45 24 User I/O (LEDs, Buttons, Switches, LCD) 25 On-Board USB Blaster II 26 Power 1 - DC Input, 12V, 3.3V 27 Power 2 - 0.90V 28 Power 3 - 5V, 1.5V, 1.8V, 3.3V 29 Power 4 - 1.0V_GXB, 1.5V_FPGA A PAGE DESCRIPTION C B A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 D Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 1 of 1 40 C 8 7 6 5 4 3 2 1 FPGA Package Top View E E D D C C B B XCVR BANK QR2 A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 2 of 1 40 C 8 7 6 5 4 3 2 1 PCI Express Connector 3.3V 12V E E R554 0_Ohms 12V_EXP 3.3V_EXP R547 0_Ohms 12V_EXP 12V_EXP 3.3V_EXP PCIE_SMBCLK PCIE_SMBDAT J25 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 PCIE_SMBCLK PCIE_SMBDAT 9 9 3.3V R262 D PCIE_WAKEn 11 PCIE_TX_P0 PCIE_TX_N0 8 8 Add Pull up connected to same voltage as IO bank 4.70K, 1% C673 0.1uF C670 0.1uF PCIE_TX_C_P0 PCIE_TX_C_N0 PCIE_PRSNT2_X1 9 8 8 PCIE_TX_P1 PCIE_TX_N1 C662 0.1uF C656 0.1uF PCIE_TX_C_P1 PCIE_TX_C_N1 8 8 PCIE_TX_P2 PCIE_TX_N2 C650 0.1uF C649 0.1uF PCIE_TX_C_P2 PCIE_TX_C_N2 8 8 PCIE_TX_P3 PCIE_TX_N3 C638 0.1uF C637 0.1uF PCIE_TX_C_P3 PCIE_TX_C_N3 C PCIE_PRSNT2_X4 9 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 +12V PRSNT1_N +12V +12V +12V +12V GND GND SMCLK JTAG_TCK SMDAT JTAG_TDI GND JTAG_TDO +3_3V JTAG_TMS JTAG_TRSTN +3_3V +3_3VAUX +3_3V WAKE_N PERST_N KEY RSVD1 GND X1 GND REFCLK+ PET0P REFCLKPET0N GND GND PER0P PRSNT2_N_X1 PER0N GND GND PET1P X4 PET1N GND GND PET2P PET2N GND GND PET3P PET3N GND RSVD3 PRSNT2_N_X4 GND RSVD2 GND PER1P PER1N GND GND PER2P PER2N GND GND PER3P PER3N GND RSVD4 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 R271 3.3V_EXP R255 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 4.7K D PCIE_PERSTn 4,11 4.70K, 1% PCIE_REFCLK_SYN_P 10 PCIE_REFCLK_SYN_N 10 PCIE_RX_P0 PCIE_RX_N0 8 8 PCIE_RX_P1 PCIE_RX_N1 8 8 PCIE_RX_P2 PCIE_RX_N2 8 8 PCIE_RX_P3 PCIE_RX_N3 8 8 C PCIE-064-02-F-D-TH Add Pull up connected to same voltage as IO bank B B 12V_EXP A 3.3V_EXP C215 C232 220uF 16V 220uF 16V C236 47uF 20V C238 47uF 20V C687 22uF 25V C683 22uF 25V C237 C231 220uF 16V 47uF 20V C235 47uF 20V C678 22uF 25V C684 22uF 25V Title Size B Date: 8 7 6 5 4 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 3 of 1 40 C 8 7 6 5 4 3 2 1 Cyclone V GX SoC Bank 3 & 4 ENET2_TX_D[3..0] 5,19 ENET2_RX_D[3..0] 5,19 U21B E E ENET_DUAL_RESETn 19,21 CYCLONE V GX SoC BANK 4 U21A 100, 1% DDR3_FPGA_DQ2 CYCLONE V GX SoC BANK 3 HSMA_D0 HSMA_D1 HSMA_D2 HSMA_D3 HSMA_SDA HSMA_SCL SDI_CLK148_UP SDI_CLK148_DN PCIE_PERSTn 8 8 AF9 AF8 AG7 AG1 AH2 AA12 AB12 AF6 AG6 D USER_DIPSW_FPGA0 USER_DIPSW_FPGA1 USER_DIPSW_FPGA2 USER_DIPSW_FPGA3 USER_PB_FPGA0 USER_PB_FPGA1 USER_LED_FPGA0 USB_FULL USB_EMPTY USB_SCL USB_SDA USB_B2_CLK USB_RESETn USB_OEn USB_RDn USB_WRn DDR3_FPGA_WEn C DDR3_FPGA_A14 AG10 AH9 AF11 AG11 AA13 AB13 AK2 AK3 AJ4 AK4 AE13 AF13 AD14 AE14 AJ5 AK6 AJ6 AJ7 AG12 AG13 DIFFIO_TX_B8p,DQ1B Bank 3A 2.5 Volt DIFFIO_TX_B9p,DQ2B DIFFIO_TX_B9n DIFFIO_RX_B10p,DQ2B DIFFIO_RX_B10n,DQ2B DIFFIO_RX_B11p,DQS2B DIFFIO_RX_B11n,DQSn2B DIFFIO_TX_B12p DIFFIO_TX_B12n,DQ2B DIFFIO_TX_B17p,DQ3B DIFFIO_TX_B17n DIFFIO_RX_B18p,DQ3B DIFFIO_RX_B18n,DQ3B DIFFIO_RX_B19p,DQS3B DIFFIO_RX_B19n,DQSn3B DIFFIO_TX_B20p DIFFIO_TX_B20n,DQ3B DIFFIO_TX_B21p,DQ3B DIFFIO_TX_B21n,DQ3B DIFFIO_RX_B22p,DQ3B DIFFIO_RX_B22n,DQ3B DIFFIO_RX_B23p DIFFIO_RX_B23n DIFFIO_TX_B24p,DQ3B DIFFIO_TX_B24n,DQ3B DIFFIO_TX_B25p,DQ4B,B_WE# DIFFIO_TX_B25n,GND DIFFIO_RX_B26p,DQ4B,B_A_14 DIFFIO_RX_B26n,DQ4B,B_A_15 DIFFIO_TX_B13p,DQ2B DIFFIO_TX_B13n,DQ2B DIFFIO_RX_B14p,DQ2B DIFFIO_RX_B14n,DQ2B DIFFIO_RX_B15p DIFFIO_RX_B15n DIFFIO_TX_B16p,DQ2B DIFFIO_TX_B16n,DQ2B Bank 3B 1.5 Volt DIFFIO_RX_B27p,DQS4B,B_CS#_0 DIFFIO_RX_B27n,DQSn4B,B_CS#_1 DIFFIO_TX_B28p,B_A_12 DIFFIO_TX_B28n,DQ4B,B_A_13 DIFFIO_TX_B29p,DQ4B,B_A_10 DIFFIO_TX_B29n,DQ4B,B_A_11 DIFFIO_RX_B30p,DQ4B,B_A_8 DIFFIO_RX_B30n,DQ4B,B_A_9 DIFFIO_TX_B32p,DQ4B,B_CAS# DIFFIO_TX_B32n,DQ4B,B_RAS# DIFFIO_TX_B33p,DQ5B,B_BA_0 DIFFIO_TX_B33n,GND DIFFIO_RX_B34p,DQ5B,B_BA_1 DIFFIO_RX_B34n,DQ5B,B_BA_2 DIFFIO_RX_B35p,DQS5B,B_CK DIFFIO_RX_B35n,DQSn5B,B_CK# DIFFIO_TX_B36p,B_A_6 DIFFIO_TX_B36n,DQ5B,B_A_7 DIFFIO_RX_B38p,DQ5B,B_A_4 DIFFIO_RX_B38n,DQ5B,B_A_5 DIFFIO_TX_B40p,DQ5B,B_A_0 DIFFIO_TX_B40n,DQ5B,B_A_1 AG5 P0TXERR19 AH5 P1TXERR19 AJ1 AJ2 HSMA_CLK_OUT_P1 AC12 HSMA_CLK_OUT_N1 AD12 HSMA_PRSNTn AG2 HSMA_CLK_IN_P1 AH3 HSMA_CLK_IN_N1 AB15 DDR3_FPGA_CSn AC14 AK7 DDR3_FPGA_A12 AK8 DDR3_FPGA_A13 AJ9 DDR3_FPGA_A10 AK9 DDR3_FPGA_A11 AH13 DDR3_FPGA_A8 AH14 DDR3_FPGA_A9 AH7 DDR3_FPGA_CASn AH8 DDR3_FPGA_RASn AH10 DDR3_FPGA_BA0 AJ10 AJ11 DDR3_FPGA_BA1 AK11 DDR3_FPGA_BA2 AA14 DDR3_FPGA_CLK_P AA15 DDR3_FPGA_CLK_N AK12 DDR3_FPGA_A6 AK13 DDR3_FPGA_A7 AG15 DDR3_FPGA_A4 AH15 DDR3_FPGA_A5 AJ14 DDR3_FPGA_A0 AK14 DDR3_FPGA_A1 AG16 AE17 AF18 V16 W16 AE16 AF16 AJ16 AK16 AG21 DDR3_FPGA_DQ5 AH20 DDR3_FPGA_DQ4 AH17 DDR3_FPGA_DM0 AH18 DDR3_FPGA_DQ7 AG18 DDR3_FPGA_DQ10 AH19 AJ17 DDR3_FPGA_DQ9 AK18 DDR3_FPGA_DQ8 V17 DDR3_FPGA_DQS_P1 W17 DDR3_FPGA_DQS_N1 AJ19 AK19 DDR3_FPGA_DQ11 AJ20 DDR3_FPGA_DQ14 AJ21 DDR3_FPGA_CKE AF19 DDR3_FPGA_DQ13 AG20 DDR3_FPGA_DQ12 AG23 DDR3_FPGA_DM1 AH24 DDR3_FPGA_DQ15 AG22 DDR3_FPGA_DQ18 AH22 AE18 DDR3_FPGA_DQ17 AE19 DDR3_FPGA_DQ16 Y17 DDR3_FPGA_DQS_P2 AA18 DDR3_FPGA_DQS_N2 DDR3_FPGA_RESETn AK21 AK22 DDR3_FPGA_DQ19 AH23 DDR3_FPGA_DQ22 AJ22 DDR3_FPGA_DQ1 DDR3_FPGA_DQ0 DDR3_FPGA_DQS_P0 DDR3_FPGA_DQS_N0 DDR3_FPGA_ODT DDR3_FPGA_DQ3 DDR3_FPGA_DQ6 DIFFIO_TX_B41p,DQ6B,B_DQ_2 DIFFIO_RX_B42p,DQ6B,B_DQ_1 DIFFIO_RX_B42n,DQ6B,B_DQ_0 DIFFIO_RX_B43p,DQS6B,B_DQS_0 DIFFIO_RX_B43n,DQSn6B,B_DQS#_0 DIFFIO_TX_B44p,B_ODT_0 DIFFIO_TX_B44n,DQ6B,B_DQ_3 DIFFIO_TX_B45p,DQ6B,B_DQ_6 DIFFIO_TX_B45n,DQ6B,B_ODT_1 DIFFIO_RX_B46p,DQ6B,B_DQ_5 DIFFIO_RX_B46n,DQ6B,B_DQ_4 DIFFIO_TX_B48p,DQ6B,B_DM_0 DIFFIO_TX_B48n,DQ6B,B_DQ_7 DIFFIO_TX_B49p,DQ7B,B_DQ_10 DIFFIO_TX_B49n,GND DIFFIO_RX_B50p,DQ7B,B_DQ_9 DIFFIO_RX_B50n,DQ7B,B_DQ_8 DIFFIO_RX_B51p,DQS7B,B_DQS_1 DIFFIO_RX_B51n,DQSn7B,B_DQS#_1 DIFFIO_TX_B52p,B_CKE_1 DIFFIO_TX_B52n,DQ7B,B_DQ_11 DIFFIO_TX_B53p,DQ7B,B_DQ_14 DIFFIO_TX_B53n,DQ7B,B_CKE_0 DIFFIO_RX_B54p,DQ7B,B_DQ_13 DIFFIO_RX_B54n,DQ7B,B_DQ_12 DIFFIO_TX_B56p,DQ7B,B_DM_1 DIFFIO_TX_B56n,DQ7B,B_DQ_15 DIFFIO_TX_B57p,DQ8B,B_DQ_18 DIFFIO_TX_B57n,GND DIFFIO_RX_B58p,DQ8B,B_DQ_17 DIFFIO_RX_B58n,DQ8B,B_DQ_16 DIFFIO_RX_B59p,DQS8B,B_DQS_2 DIFFIO_RX_B59n,DQSn8B,B_DQS#_2 DIFFIO_TX_B60p,B_RESET# DIFFIO_TX_B60n,DQ8B,B_DQ_19 DIFFIO_TX_B61p,DQ8B,B_DQ_22 DIFFIO_TX_B61n,DQ8B,GND 5CSXFC6D_F896 Bank 4A 1.5 Volt RZQ_0,DIFFIO_TX_B41n DIFFIO_RX_B62p,DQ8B,B_DQ_21 DIFFIO_RX_B62n,DQ8B,B_DQ_20 DIFFIO_RX_B63p,GND DIFFIO_RX_B63n,GND DIFFIO_TX_B64p,DQ8B,B_DM_2 DIFFIO_TX_B64n,DQ8B,B_DQ_23 DIFFIO_TX_B65p,DQ9B,B_DQ_26 DIFFIO_TX_B65n,GND DIFFIO_RX_B66p,DQ9B,B_DQ_25 DIFFIO_RX_B66n,DQ9B,B_DQ_24 DIFFIO_RX_B67p,DQS9B,B_DQS_3 DIFFIO_RX_B67n,DQSn9B,B_DQS#_3 DIFFIO_TX_B68p,GND DIFFIO_TX_B68n,DQ9B,B_DQ_27 DIFFIO_TX_B69p,DQ9B,B_DQ_30 DIFFIO_TX_B69n,DQ9B,GND DIFFIO_RX_B70p,DQ9B,B_DQ_29 DIFFIO_RX_B70n,DQ9B,B_DQ_28 DIFFIO_RX_B71p,GND DIFFIO_RX_B71n,GND DIFFIO_TX_B72p,DQ9B,B_DM_3 DIFFIO_TX_B72n,DQ9B,B_DQ_31 DIFFIO_TX_B73p,DQ10B,B_DQ_34 DIFFIO_TX_B73n,GND DIFFIO_RX_B74p,DQ10B,B_DQ_33 DIFFIO_RX_B74n,DQ10B,B_DQ_32 DIFFIO_RX_B75p,DQS10B,B_DQS_4 DIFFIO_RX_B75n,DQSn10B,B_DQS#_4 DIFFIO_TX_B76p,GND DIFFIO_TX_B76n,DQ10B,B_DQ_35 DIFFIO_TX_B77p,DQ10B,B_DQ_38 DIFFIO_TX_B77n,DQ10B,GND DIFFIO_RX_B78p,DQ10B,B_DQ_37 DIFFIO_RX_B78n,DQ10B,B_DQ_36 DIFFIO_RX_B79p,GND DIFFIO_RX_B79n,GND DIFFIO_TX_B80p,DQ10B,B_DM_4 DIFFIO_TX_B80n,DQ10B,B_DQ_39 AG17 R449 RZQIN_1_5V AF20 DDR3_FPGA_DQ21 AF21 DDR3_FPGA_DQ20 Y18 AA19 AK23 DDR3_FPGA_DM2 AK24 DDR3_FPGA_DQ23 AJ24 DDR3_FPGA_DQ26 AJ25 AF23 DDR3_FPGA_DQ25 AF24 DDR3_FPGA_DQ24 AC20 DDR3_FPGA_DQS_P3 AD19 DDR3_FPGA_DQS_N3 AJ26 AK26 DDR3_FPGA_DQ27 AG25 DDR3_FPGA_DQ30 AH25 AE22 DDR3_FPGA_DQ29 AE23 DDR3_FPGA_DQ28 V18 W19 AJ27 DDR3_FPGA_DM3 AK27 DDR3_FPGA_DQ31 AK28 USB_B2_DATA0 AK29 AD20 USB_B2_DATA1 AD21 USB_B2_DATA2 Y19 USB_B2_DATA3 AA20 USB_B2_DATA4 AG26 AH27 USB_B2_DATA5 AF25 USB_B2_DATA6 AF26 AC22 USB_B2_DATA7 AC23 AA21 AB21 AD24 AE24 D C 5CSXFC6D_F896 HSMC LVCMOS INTERFACE HSMA_CLK_OUT_P1 HSMA_CLK_OUT_N1 HSMA_CLK_IN_P1 B HSMA_D[3:0] HSMA_SDA HSMA_SCL 17 23 23 LVCMOS Only 17 9,23 HSMA_CLK_IN_N1 HSMA_PRSNTn 17 DDR3_FPGA_CKE DDR3_FPGA_CLK_P DDR3_FPGA_CLK_N DDR3_FPGA_CKE 13 DDR3_FPGA_CLK_P 13 DDR3_FPGA_CLK_N 13 USER_DIPSW_FPGA[3:0] USER_PB_FPGA[1:0] USB_B2_DATA[7:0] 25 USB_B2_DATA[7:0] USER_LED_FPGA[3:0] 17 USB_FULL USB_EMPTY USB_SCL USB_SDA USB_B2_CLK USB_RESETn USB_OEn USB_RDn USB_WRn 16,17,23 17 25 25 25 25 16,25 25 25 25 25 USB_FULL USB_EMPTY USB_SCL USB_SDA USB_B2_CLK USB_RESETn USB_OEn USB_RDn USB_WRn DDR3_FPGA_DM0 DDR3_FPGA_DM1 DDR3_FPGA_DM2 DDR3_FPGA_DM3 13 13 13 13 DDR3_FPGA_DM0 DDR3_FPGA_DM1 DDR3_FPGA_DM2 DDR3_FPGA_DM3 DDR3_FPGA_CSn DDR3_FPGA_WEn DDR3_FPGA_RASn DDR3_FPGA_CASn 13 13 13 13 DDR3_FPGA_CSn DDR3_FPGA_WEn DDR3_FPGA_RASn DDR3_FPGA_CASn 13 13 13 13 13 DDR3_FPGA_BA0 DDR3_FPGA_BA1 DDR3_FPGA_BA2 DDR3_FPGA_RESETn DDR3_FPGA_ODT DDR3_FPGA_BA0 DDR3_FPGA_BA1 DDR3_FPGA_BA2 DDR3_FPGA_RESETn DDR3_FPGA_ODT 17 17 13 13 13 13 13 9,13 DDR3_FPGA_BA[2:0] DDR3_FPGA_DM[3:0] DDR3_FPGA_DQS_P[3:0] B DDR3_FPGA_DQS_N[3:0] DDR3_FPGA_DQ[31:0] DDR3_FPGA_A[14:0] PCIE INTERFACE A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 PCIE_PERSTn 3,11 Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 4 of 1 40 C 8 7 6 5 4 3 2 1 Cyclone V GX SoC Bank 5 & 6 U21D CYCLONE V GX SoC BANK 6 100, 1% E U21C CYCLONE V GX SoC BANK 5 ENET1_TX_D0 ENET1_TX_D1 ENET1_TX_D2 ENET1_TX_D3 ENET1_TX_EN ENET1_RX_D0 ENET1_RX_D1 ENET1_RX_D2 ENET1_RX_D3 ENET1_RX_ERROR ENET1_RX_DV ENET1_RX_CLK 19 D 19 19 19 19 19 19 C W20 Y21 AA25 AB26 AB22 AB23 AA24 AB25 AE27 AE28 Y23 Y24 ENET1_TX_CLK_FB W25 ENET2_RX_ERROR V25 AC28 ENET2_RX_DV SDI_TX_SD_HDn AC29 20 AB30 SDI_RSTI 20 SDI_TX_EN AA30 16,20 SDI_RX_BYPASSAB28 16,20 AA28 SDI_RX_EN 16,20 SDI_FAULT AD30 20 AC30 Bank 5A 2.5 Volt RZQ_1,DIFFIO_TX_R1p,DQ1R DIFFIO_RX_R4p,DQ1R DIFFIO_RX_R4n,DQ1R DIFFIO_TX_R12p,DQ2R DIFFIO_TX_R7p,DQ1R DIFFIO_TX_R12n,DQ2R DIFFIO_TX_R7n DIFFIO_RX_R13p,DQS2R DIFFIO_RX_R8p,DQ1R DIFFIO_RX_R13n,DQSn2R DIFFIO_RX_R8n,DQ1R DIFFIO_TX_R14p DIFFIO_RX_R9p DIFFIO_TX_R14n,DQ2R DIFFIO_RX_R9n DIFFIO_RX_R15p,DQ2R DIFFIO_TX_R10p,DQ2R DIFFIO_RX_R15n,DQ2R DIFFIO_TX_R10n,DQ2R DIFFIO_TX_R16p,DQ2R DIFFIO_RX_R11p,DQ2R DIFFIO_TX_R16n DIFFIO_RX_R11n,DQ2R DIFFIO_RX_R17p DIFFIO_RX_R17n DIFFIO_TX_R18p,DQ3R DIFFIO_TX_R18n,DQ3R DIFFIO_RX_R19p,DQ3R DIFFIO_RX_R19n,DQ3R DIFFIO_TX_R20p,DQ3R DIFFIO_TX_R20n,DQ3R DIFFIO_TX_R24p,DQ3R AG27 ENET2_TX_D0 AG28 ENET2_TX_D1 AF28 ENET2_TX_D2 V23 ENET2_TX_D3 W24 ENET2_TX_EN19 AF29 ENET2_RX_D0 AF30 ENET2_RX_D1 AD26 ENET2_RX_D2 AC27 ENET2_RX_D3 AH30 ENET2_RX_CLK 19 AG30 ENET2_TX_CLK_FB 19 Bank 5B 2.5 Volt RZQ_2,DIFFIO_TX_R24n 5CSXFC6D_F896 19 19 19 19 ENET1_TX_D[3..0] ENET1_RX_D[3..0] ENET2_TX_D[3..0] ENET2_RX_D[3..0] R410 DDR3_HPS_A0 DDR3_HPS_A1 DDR3_HPS_A2 DDR3_HPS_A3 DDR3_HPS_A4 DDR3_HPS_A5 DDR3_HPS_A6 DDR3_HPS_A7 DDR3_HPS_A8 DDR3_HPS_A9 DDR3_HPS_A10 DDR3_HPS_A11 DDR3_HPS_A12 DDR3_HPS_A13 DDR3_HPS_A14 D27 F26 G30 F28 F30 J25 J27 F29 E28 H27 G26 D29 C30 B30 C29 H25 G25 DDR3_HPS_CLK_P M23 DDR3_HPS_CLK_N L23 L29 DDR3_HPS_CKE L30 E29 DDR3_HPS_BA0 J24 DDR3_HPS_BA1 J23 DDR3_HPS_BA2 DDR3_HPS_RASn D30 DDR3_HPS_CASn E27 DDR3_HPS_WEn C28 H24 DDR3_HPS_CSn K21 DDR3_HPS_ODT H28 H29 DDR3_HPS_DM2 DDR3_HPS_DQS_P2 DDR3_HPS_DQS_N2 DDR3_HPS_DQ16 DDR3_HPS_DQ17 DDR3_HPS_DQ18 DDR3_HPS_DQ19 DDR3_HPS_DQ20 DDR3_HPS_DQ21 DDR3_HPS_DQ22 DDR3_HPS_DQ23 R28 R19 R18 U26 T26 N29 N28 P26 P27 N27 R29 DDR3_HPS_DM3 DDR3_HPS_DQS_P3 DDR3_HPS_DQS_N3 DDR3_HPS_DQ24 DDR3_HPS_DQ25 DDR3_HPS_DQ26 DDR3_HPS_DQ27 DDR3_HPS_DQ28 DDR3_HPS_DQ29 DDR3_HPS_DQ30 DDR3_HPS_DQ31 W30 R22 R21 P24 P25 T29 T28 R27 R26 V30 W29 HPS_RZQ_0 HPS_DDR,HPS_A_0 HPS_DDR,HPS_A_1 HPS_DDR,HPS_A_2 HPS_DDR,HPS_A_3 HPS_DDR,HPS_A_4 HPS_DDR,HPS_A_5 HPS_DDR,HPS_A_6 HPS_DDR,HPS_A_7 HPS_DDR,HPS_A_8 HPS_DDR,HPS_A_9 HPS_DDR,HPS_A_10 HPS_DDR,HPS_A_11 HPS_DDR,HPS_A_12 HPS_DDR,HPS_A_13 HPS_DDR,HPS_A_14 HPS_DDR,HPS_A_15 Bank 6A 1.5 Volt HPS_DDR,HPS_DM_1 HPS_DDR,HPS_DQS_1 HPS_DDR,HPS_DQS#_1 HPS_DDR,HPS_DQ_8 HPS_DDR,HPS_DQ_9 HPS_DDR,HPS_DQ_10 HPS_DDR,HPS_DQ_11 HPS_DDR,HPS_DQ_12 HPS_DDR,HPS_DQ_13 HPS_DDR,HPS_DQ_14 HPS_DDR,HPS_DQ_15 HPS_DDR,HPS_CK HPS_DDR,HPS_CK# HPS_DDR,HPS_CKE_0 HPS_DDR,HPS_CKE_1 HPS_DDR,HPS_BA_0 HPS_DDR,HPS_BA_1 HPS_DDR,HPS_BA_2 HPS_DDR,HPS_RAS# HPS_DDR,HPS_CAS# HPS_DDR,HPS_WE# HPS_DDR,HPS_CS#_0 HPS_DDR,HPS_CS#_1 HPS_DDR,HPS_ODT_0 HPS_DDR,HPS_ODT_1 HPS_DDR,HPS_DM_2 HPS_DDR,HPS_DQS_2 HPS_DDR,HPS_DQS#_2 HPS_DDR,HPS_DQ_16 HPS_DDR,HPS_DQ_17 HPS_DDR,HPS_DQ_18 HPS_DDR,HPS_DQ_19 HPS_DDR,HPS_DQ_20 HPS_DDR,HPS_DQ_21 HPS_DDR,HPS_DQ_22 HPS_DDR,HPS_DQ_23 HPS_DDR,HPS_DM_0 HPS_DDR,HPS_DQS_0 HPS_DDR,HPS_DQS#_0 HPS_DDR,HPS_DQ_0 HPS_DDR,HPS_DQ_1 HPS_DDR,HPS_DQ_2 HPS_DDR,HPS_DQ_3 HPS_DDR,HPS_DQ_4 HPS_DDR,HPS_DQ_5 HPS_DDR,HPS_DQ_6 HPS_DDR,HPS_DQ_7 HPS_GI14 HPS_GI13 HPS_GI11 HPS_GI12 Bank 6B 1.5 Volt HPS_DDR,HPS_DM_4 HPS_DDR,HPS_DQS_4 HPS_DDR,HPS_DQS#_4 HPS_DDR,HPS_DQ_32 HPS_DDR,HPS_DQ_33 HPS_DDR,HPS_DQ_34 HPS_DDR,HPS_DQ_35 HPS_DDR,HPS_DQ_36 HPS_DDR,HPS_DQ_37 HPS_DDR,HPS_DQ_38 HPS_DDR,HPS_DQ_39 HPS_DDR,HPS_DM_3 HPS_DDR,HPS_DQS_3 HPS_DDR,HPS_DQS#_3 HPS_DDR,HPS_DQ_24 HPS_DDR,HPS_DQ_25 HPS_DDR,HPS_DQ_26 HPS_DDR,HPS_DQ_27 HPS_DDR,HPS_DQ_28 HPS_DDR,HPS_DQ_29 HPS_DDR,HPS_DQ_30 HPS_DDR,HPS_DQ_31 HPS_GI10 HPS_GI9 HPS_GI8 HPS_GI7 HPS_GI6 HPS_GI5 HPS_GI4 HPS_GI3 HPS_GI2 HPS_GI1 HPS_DDR,HPS_RESET# B K28 N18 M19 K23 K22 H30 G28 L25 L24 J30 J29 DDR3_HPS_DM0 DDR3_HPS_DQS_P0 DDR3_HPS_DQS_N0 DDR3_HPS_DQ0 DDR3_HPS_DQ1 DDR3_HPS_DQ2 DDR3_HPS_DQ3 DDR3_HPS_DQ4 DDR3_HPS_DQ5 DDR3_HPS_DQ6 DDR3_HPS_DQ7 M28 N25 N24 K26 L26 K29 K27 M26 M27 L28 M30 DDR3_HPS_DM1 DDR3_HPS_DQS_P1 DDR3_HPS_DQS_N1 DDR3_HPS_DQ8 DDR3_HPS_DQ9 DDR3_HPS_DQ10 DDR3_HPS_DQ11 DDR3_HPS_DQ12 DDR3_HPS_DQ13 DDR3_HPS_DQ14 DDR3_HPS_DQ15 DDR3_HPS_BA0 DDR3_HPS_BA1 DDR3_HPS_BA2 DDR3_HPS_RASn DDR3_HPS_CASn DDR3_HPS_WEn DDR3_HPS_CSn W27 T24 T23 W26 R24 U27 V28 T25 U25 V27 Y29 DDR3_HPS_DM4 DDR3_HPS_DQS_P4 DDR3_HPS_DQS_N4 DDR3_HPS_DQ32 DDR3_HPS_DQ33 DDR3_HPS_DQ34 DDR3_HPS_DQ35 DDR3_HPS_DQ36 DDR3_HPS_DQ37 DDR3_HPS_DQ38 DDR3_HPS_DQ39 N30 P29 P22 V20 T30 U28 T21 U20 V29 Y28 USER_DIPSW_HPS0 USER_DIPSW_HPS1 USER_DIPSW_HPS2 USER_DIPSW_HPS3 USER_PB_HPS0 USER_PB_HPS1 USER_PB_HPS2 USER_PB_HPS3 P30 DDR3_HPS_RESETn DDR3_HPS_RESETn A 14 USER_PB_HPS[3:0] 23 HSMA_CLK_OUT_P[2:1] DDR3_HPS_BA[2:0] HSMA_TX_D_N[16:0] DDR3_HPS_DM[4:0] HSMA_RX_D_P[16:0] 14 14 14 DDR3_HPS_RESETn 14 4,7,17 B 4,7,17 7,17 7,17 7,17 HSMA_RX_D_N[16:0] DDR3_HPS_ODT 14 USER_DIPSW_HPS[3:0] 23 HSMA_CLK_OUT_N[2:1] 14 DDR3_HPS_BA0 DDR3_HPS_BA1 DDR3_HPS_BA2 DDR3_HPS_RASn DDR3_HPS_CASn DDR3_HPS_WEn DDR3_HPS_CSn DDR3_HPS_ODT 14 C HSMA_TX_D_P[16:0] DDR3_HPS_CLK_P DDR3_HPS_CLK_N DDR3_HPS_CKE 14 14 14 14 14 14 14 D M25 J26 M22 N23 5CSXFC6D_F896 DDR3_HPS_CLK_P14 DDR3_HPS_CLK_N14 DDR3_HPS_CKE 14 E 7,17 DDR3_HPS_DQS_P[4:0] DDR3_HPS_DQS_N[4:0] Si571 VCXO DDR3_HPS_DQ[39:0] SDI_CLK148_DN 4,8 DDR3_HPS_A[14:0] A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 5 of 1 40 C 8 7 6 5 4 3 2 Micro SD / USB INTERFACE Cyclone V GX SoC Bank 7 2.5V_HPS 3.3V 1 USB_DATA[7..0] 22 U21E USB_DATA[7..0] R393 R392 4.70K, 1% E 12 JTAG_HPS_TMS JTAG_HPS_TCK JTAG_HPS_TRST JTAG_HPS_TDI 12 12 12 J27 D CLK_OSC1 CLK_OSC2 10 10 3.3V TRACE_CLK_MIC TRACE_DATA0 TRACE_DATA1 TRACE_DATA2 CLKSEL0 R240 CLKSEL1 R242 HEADER, 1x3-PIN SD_CD_DAT3 SD_DAT2 SD_CLK 0 22 22 22 B26 B25 C25 A25 B20 G20 A20 K17 B21 E21 A21 F19 F21 J19 F20 B16 SD_CD_DAT3 D17 SD_DAT2 A16 SD_CLK USER_LED_HPS0 E17 USER_LED_HPS1 E18 USER_LED_HPS2 G17 22 22 22 USB_DATA6 USB_DATA5 USB_DATA7 D15 C14 M17 N16 A14 E14 C15 USB_DATA6 USB_DATA5 USB_DATA7 USB_CLK USB_NXT USB_DIR USB_STP 22 22 22 USB_CLK 22 22 USB_NXT 22 USB_DIR 22 USB_STP C R391 R375 R373 R374 ENET_HPS_RXD1 ENET_HPS_RX_CLK ENET_HPS_TX_EN ENET_HPS_RX_DV ENET_HPS_MDC ENET_HPS_MDIO ENET_HPS_RXD0 ENET_HPS_TXD3 ENET_HPS_TXD2 ENET_HPS_TXD1 ENET_HPS_TXD0 3.3V 1 10.0K R241 2 CAN_0_TX 3 1.00k C27 F23 B28 G23 A29 H22 A28 B27 F24 D25 F25 MICTOR_RSTn HPS_RESETn JTAG_HPS_TDO 2.5V_HPS HEADER, 1x3-PIN J26 1 10.0K R239 2 UART_TX 3 1.00k ETHERNET INTERFACE CYCLONE V GX SoC BANK 7 4.70K, 1% HPS_nRST HPS_nPOR HPS_TDO VCC_HPS HPS_TMS HPS_TCK HPS_TRST HPS_TDI HPS_PORSEL HPS_CLK1 HPS_CLK2 Bank 7A D24 E24 D22 C23 G22 B22 H20 B23 C22 A23 E23 C24 G21 A24 H23 CAN0_TX,UART0_TX,SPIM1_SS0,HPS_GPIO66 CAN0_RX,UART0_RX,SPIM1_MISO,HPS_GPIO65 I2C0_SCL,UART1_TX,SPIM1_MOSI,HPS_GPIO64 I2C0_SDA,UART1_RX,SPIM1_CLK,HPS_GPIO63 UART0_TX,CAN0_TX,SPIM1_SS1,HPS_GPIO62 UART0_RX,CAN0_RX,SPIM0_SS1,HPS_GPIO61 SPIM0_SS0,CAN1_TX,UART1_RTS,BOOTSEL0,HPS_GPIO60 SPIM0_MISO,CAN1_RX,UART1_CTS,HPS_GPIO59 SPIM0_MOSI,I2C1_SCL,UART0_RTS,HPS_GPIO58 SPIM0_CLK,I2C1_SDA,UART0_CTS,HPS_GPIO57 TRACE_D7,SPIS1_MISO,I2C0_SCL,HPS_GPIO56 TRACE_D6,SPIS1_SS0,I2C0_SDA,HPS_GPIO55 TRACE_D5,SPIS1_MOSI,CAN1_TX,HPS_GPIO54 TRACE_D4,SPIS1_CLK,CAN1_RX,HPS_GPIO53 TRACE_D3,SPIS0_SS0,I2C1_SCL,HPS_GPIO52 TRACE_CLK,HPS_GPIO48 TRACE_D0,SPIS0_CLK,UART0_RX,HPS_GPIO49 TRACE_D1,SPIS0_MOSI,UART0_TX,HPS_GPIO50 TRACE_D2,SPIS0_MISO,I2C1_SDA,HPS_GPIO51 NAND_DQ6,RGMII1_RXD1,USB1_D7,HPS_GPIO25 NAND_DQ5,RGMII1_RX_CLK,USB1_D6,HPS_GPIO24 NAND_DQ4,RGMII1_TX_CTL,USB1_D5,HPS_GPIO23 NAND_DQ3,RGMII1_RX_CTL,USB1_D4,HPS_GPIO22 NAND_DQ2,RGMII1_MDC,I2C3_SCL,HPS_GPIO21 NAND_DQ1,RGMII1_MDIO,I2C3_SDA,HPS_GPIO20 NAND_DQ0,RGMII1_RXD0,HPS_GPIO19 NAND_RB,RGMII1_TXD3,USB1_D3,HPS_GPIO18 NAND_RE,RGMII1_TXD2,USB1_D2,HPS_GPIO17 NAND_CLE,RGMII1_TXD1,USB1_D1,HPS_GPIO16 NAND_CE,RGMII1_TXD0,USB1_D0,HPS_GPIO15 Bank 7B NAND_ALE,RGMII1_TX_CLK,QSPI_SS3,HPS_GPIO14 NAND_DQ7,RGMII1_RXD2,HPS_GPIO26 NAND_WP,RGMII1_RXD3,QSPI_SS2,HPS_GPIO27 NAND_WE,QSPI_SS1,BOOTSEL2,HPS_GPIO28 QSPI_IO0,USB1_CLK,HPS_GPIO29 QSPI_IO1,USB1_STP,HPS_GPIO30 QSPI_IO2,USB1_DIR,HPS_GPIO31 QSPI_IO3,USB1_NXT,HPS_GPIO32 QSPI_SS0,BOOTSEL1,HPS_GPIO33 QSPI_CLK,HPS_GPIO34 QSPI_SS1,HPS_GPIO35 SDMMC_D3,USB0_NXT,HPS_GPIO47 SDMMC_D2,USB0_DIR,HPS_GPIO46 SDMMC_CLK,USB0_STP,HPS_GPIO45 SDMMC_CLK_IN,USB0_CLK,HPS_GPIO44 SDMMC_D7,USB0_D7,HPS_GPIO43 SDMMC_D6,USB0_D6,HPS_GPIO42 Bank 7C RGMII0_MDC ,USB1_D6,I2C2_SCL,HPS_GPIO7 RGMII0_MDIO,USB1_D5,I2C2_SDA,HPS_GPIO6 RGMII0_RX_CTL,USB1_D7,HPS_GPIO8 RGMII0_RX_CLK,USB1_CLK,HPS_GPIO10 RGMII0_RXD3,USB1_NXT,HPS_GPIO13 RGMII0_RXD2,USB1_DIR,HPS_GPIO12 RGMII0_RXD1,USB1_STP,HPS_GPIO11 Bank 7D UART_TX24 UART_RX 24 I2C_SCL_HPS 18,23,27 I2C_SDA_HPS 18,23,27 CAN_0_TX 24 CAN_0_RX 24 SPI_CSn SPI_MISO SPI_MOSI SPI_SCK R377 22 TRACE_DATA7 R376 22 TRACE_DATA6 R396 22 TRACE_DATA5 R395 22 TRACE_DATA4 R394 22 TRACE_DATA3 ENET_HPS_TXD[3..0] 18 ENET_HPS_TXD[3..0] ENET_HPS_GTX_CLK18 ENET_HPS_TX_EN 18 ENET_HPS_MDC 18 ENET_HPS_RESETn 18,21 ENET_HPS_GTX_CLK ENET_HPS_TX_EN ENET_HPS_MDC ENET_HPS_RESETn ENET_HPS_RXD[3..0] 18 ENET_HPS_RXD[3..0] ENET_HPS_RX_CLK 18 ENET_HPS_RX_DV 18 ENET_HPS_MDIO 18 ENET_HPS_INTn 18 ENET_HPS_RX_CLK ENET_HPS_RX_DV ENET_HPS_MDIO ENET_HPS_INTn HPS_RESETn H19 B18 D21 D20 C20 H18 A19 E19 A18 D19 C19 SDMMC_CMD,USB0_D0,HPS_GPIO36 SDMMC_PWREN,USB0_D1,HPS_GPIO37 SDMMC_D0,USB0_D2,HPS_GPIO38 SDMMC_D1,USB0_D3,HPS_GPIO39 SDMMC_D4,USB0_D4,HPS_GPIO40 SDMMC_D5,USB0_D5,HPS_GPIO41 RGMII0_RXD0,USB1_D4,HPS_GPIO5 RGMII0_TXD3,USB1_D3,HPS_GPIO4 RGMII0_TXD2,USB1_D2,HPS_GPIO3 RGMII0_TXD1,USB1_D1,HPS_GPIO2 RGMII0_TXD0,USB1_D0,HPS_GPIO1 RGMII0_TX_CLK,HPS_GPIO0 RGMII0_TX_CTL,HPS_GPIO9 ENET_HPS_GTX_CLK ENET_HPS_RXD2 ENET_HPS_RXD3 BOOTSEL2 QSPI_IO0 21 QSPI_IO1 21 QSPI_IO2 21 QSPI_IO3 21 QSPI_SS0 21 QSPI_CLK 21 ENET_HPS_INTn F18 B17 G18 C17 H17 C18 SD_CMD SD_PWREN SD_DAT0 SD_DAT1 A15 D14 D16 G16 E16 F16 B15 USB_DATA4 USB_DATA3 USB_DATA2 USB_DATA1 USB_DATA0 16,21 HPS_RESETn USER_LED_HPS[3..0] 23 HEADER, 1x3-PIN J28 R243 10.0K 1 BOOTSEL0 2 SPI_CSn 3 1.00k R244 SD_CMD SD_PWREN SD_DAT0 SD_DAT1 22 22 3.3V USER_LED_HPS3 BOOTSEL1 HEADER, 1x3-PIN USB_DATA4 USB_DATA3 USB_DATA2 USB_DATA1 USB_DATA0 22 22 22 22 22 J29 1 R245 10.0K 2 QSPI_SS0 3 1.00k R246 D USER_LED_HPS[3..0] 3.3V 22 E 3.3V J30 1 2 3 R247 10.0K BOOTSEL2 1.00k R248 C BOOTSEL2 CONV_HPS_USB_N HEADER, 1x3-PIN 3.3V 5CSXFC6D_F896 C685 C686 2.2uF 0.1uF 3.3V R3 R4 4.70K, 1% 4.70K, 1% JTAG_MICTOR_TMS JTAG_MICTOR_TDI 9V_VPP 3.3V J4 5.0V MICTOR_RSTn12,16,21 JTAG_MICTOR_TDI 12 J32 B MISO MOSI_SDA I2C_SDA_HPS R260 0 I2C_SCL_HPS R259 0 1 3 5 7 9 11 13 1 3 5 7 9 11 13 2 4 6 8 10 12 14 2 4 6 8 10 12 14 SCK_SCL CSn R310 10.0K MICTOR_RSTn JTAG_MICTOR_TDI R258 0 JTAG_MICTOR_TCK JTAG_MICTOR_TMS JTAG_MICTOR_TDO XJ4 JTAG_MICTOR_TCK JTAG_MICTOR_TMS JTAG_MICTOR_TDO MICTOR_TRST 12 12 12 881545-2 J16 1 2 HDR 2X7, VT, THM, 2mm JTAG_MIC_SEL 2.5V_REG_HPS R125 4.70K, 1% CON2 Logic 0 = pin 10 <--> pin 9 (TRST from JTAG) Logic 1 = pin 10 <--> pin 2 (TRST from MICTOR) U57 JTAG_MIC_SEL 1 MICTOR_TRST 2 IN1 NO1 COM1 NC1 10 9 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 5VDC GND CLKE D15E D14E D13E D12E D11E D10E D9E D8E D7E D6E D5E D4E D3E D2E D1E D0E 0 JTAG_HPS_TRST R318 JTAG_TRST 12,16 2.5V_REG_HPS MICTR_TRST SCL SDA CLKO D15O D14O D13O D12O D11O D10O D9O D8O D7O D6O D5O D4O D3O D2O D1O D0O GND1 GND2 GND3 GND4 GND5 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 39 40 41 42 43 3.3V U54 16 TRACE_CLK_MIC R338 10.0K R33 MICTOR_PWR1 MICTOR_PWR2 TRACE_DATA7 TRACE_DATA6 TRACE_DATA5 TRACE_DATA4 TRACE_DATA3 TRACE_DATA2 TRACE_DATA1 R327 R328 R330 MIC_34 MIC_36 R331 TRACE_DATA0 3.3V 2 SPI_MISO 3 0_Ohms 0_Ohms R32 5 SPI_MOSI I2C_SDA_HPS 6 VCC I0A YA MISO B XJ3 I0B YB 7 MOSI_SDA I1B 881545-2 11 SPI_SCK 10K 10K 10K 10K I2C_SCL_HPS 10 3.3V 14 SPI_CSn 3.3V 13 3.3V I0C YC 8 C24 9 SCK_SCL 3.3V I1C I0D YD I1D S C25 4 I1A GND E 12 1 R266 10.0K CSn J31 1 2 CODEC_SEL 15 CON2 IDTQS3VH257 A 3 Logic 0 = pin 6 <--> pin 7 (Bypass) Logic 1 = pin 6 <--> pin 4 (Enable) 4 5 GND V+ NO2 NC2 IN2 COM2 8 C244 0.1uF Mictor38P 0.1uF 0.001uf 7 Title MIC_34 MIC_36 6 R329 R332 DNI DNI Size B TS5A23157 Date: 8 7 6 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 6 of 1 40 C 8 7 6 5 4 3 2 Cyclone V GX SoC Bank 8 HSMA_D[3:0] 4,17 HSMA_TX_D_P[16:0] HSMA_TX_D_N[16:0] E 1 HSMA_RX_D_P[16:0] 17 17 E 17 HSMA_RX_D_N[16:0] 17 HSMA_CLK_OUT_P[2:1] 4,17 HSMA_CLK_OUT_N[2:1] 4,17 U21F HSMA_CLK_IN_P[2:1] CYCLONE V GX SoC BANK 8 D C 19 19 B13 A13 C13 B12 F15 F14 C12 B11 D11 D10 A9 A8 C7 B7 E9 D9 C8 B8 H14 G13 C10 C9 F13 E13 A6 A5 H8 G8 A4 A3 E12 D12 D6 C5 H13 H12 D5 C4 HSMA_TX_D_P15 HSMA_TX_D_N15 HSMA_RX_D_P15 HSMA_RX_D_N15 HSMA_RX_D_P16 HSMA_RX_D_N16 HSMA_TX_D_P16 HSMA_TX_D_N16 HSMA_RX_D_P12 HSMA_RX_D_N12 HSMA_TX_D_P12 HSMA_TX_D_N12 HSMA_TX_D_P11 HSMA_TX_D_N11 HSMA_RX_D_P11 HSMA_RX_D_N11 HSMA_TX_D_P13 HSMA_TX_D_N13 HSMA_RX_D_P0 HSMA_RX_D_N0 HSMA_TX_D_P14 HSMA_TX_D_N14 HSMA_RX_D_P14 HSMA_RX_D_N14 HSMA_TX_D_P10 HSMA_TX_D_N10 HSMA_RX_D_P6 HSMA_RX_D_N6 HSMA_TX_D_P8 HSMA_TX_D_N8 HSMA_RX_D_P13 HSMA_RX_D_N13 HSMA_TX_D_P1 HSMA_TX_D_N1 ENET_FPGA_MDIO ENET_FPGA_MDC HSMA_TX_D_P9 HSMA_TX_D_N9 4,9,17 HSMA_CLK_IN_N[2:1] 4,9,17 Bank 8A 2.5 Volt DIFFIO_TX_T2p,DQ1T DIFFIO_TX_T2n,DQ1T DIFFIO_RX_T3p,DQ1T DIFFIO_RX_T3n,DQ1T DIFFIO_RX_T5p,DQS1T DIFFIO_RX_T5n,DQSn1T DIFFIO_TX_T6p DIFFIO_TX_T6n,DQ1T DIFFIO_RX_T7p,DQ1T DIFFIO_RX_T7n,DQ1T DIFFIO_TX_T8p,DQ1T DIFFIO_TX_T8n DIFFIO_TX_T10p,DQ2T DIFFIO_TX_T10n,DQ2T DIFFIO_RX_T11p,DQ2T DIFFIO_RX_T11n,DQ2T DIFFIO_TX_T12p,DQ2T DIFFIO_TX_T12n,DQ2T DIFFIO_RX_T13p,DQS2T DIFFIO_RX_T13n,DQSn2T DIFFIO_TX_T14p DIFFIO_TX_T14n,DQ2T DIFFIO_RX_T15p,DQ2T DIFFIO_RX_T15n,DQ2T DIFFIO_TX_T16p,DQ2T DIFFIO_TX_T16n DIFFIO_RX_T17p DIFFIO_RX_T17n DIFFIO_TX_T18p,DQ3T DIFFIO_TX_T18n,DQ3T DIFFIO_RX_T19p,DQ3T DIFFIO_RX_T19n,DQ3T DIFFIO_TX_T20p,DQ3T DIFFIO_TX_T20n,DQ3T DIFFIO_RX_T21p,DQS3T DIFFIO_RX_T21n,DQSn3T DIFFIO_TX_T22p DIFFIO_TX_T22n,DQ3T DIFFIO_RX_T23p,DQ3T DIFFIO_RX_T23n,DQ3T DIFFIO_TX_T24p,DQ3T DIFFIO_TX_T24n DIFFIO_RX_T25p DIFFIO_RX_T25n DIFFIO_TX_T26p,DQ4T DIFFIO_TX_T26n,DQ4T DIFFIO_RX_T27p,DQ4T DIFFIO_RX_T27n,DQ4T DIFFIO_TX_T28p,DQ4T DIFFIO_TX_T28n,DQ4T DIFFIO_RX_T29p,DQS4T DIFFIO_RX_T29n,DQSn4T DIFFIO_TX_T30p DIFFIO_TX_T30n,DQ4T DIFFIO_RX_T31p,DQ4T DIFFIO_RX_T31n,DQ4T DIFFIO_TX_T32p,DQ4T DIFFIO_TX_T32n DIFFIO_RX_T33p DIFFIO_RX_T33n DIFFIO_TX_T34p,DQ5T DIFFIO_TX_T34n,DQ5T DIFFIO_RX_T35p,DQ5T DIFFIO_RX_T35n,DQ5T DIFFIO_TX_T36p,DQ5T DIFFIO_TX_T36n,DQ5T DIFFIO_RX_T37p,DQS5T DIFFIO_RX_T37n,DQSn5T DIFFIO_TX_T38p DIFFIO_TX_T38n,DQ5T DIFFIO_RX_T39p,DQ5T DIFFIO_RX_T39n,DQ5T DIFFIO_TX_T40p,DQ5T DIFFIO_TX_T40n F11 HSMA_RX_D_P9 E11 HSMA_RX_D_N9 E8 HSMA_TX_D_P0 D7 HSMA_TX_D_N0 J7 HSMA_RX_D_P5 H7 HSMA_RX_D_N5 B2 HSMA_TX_D_P6 B1 HSMA_TX_D_N6 B6 HSMA_RX_D_P10 B5 HSMA_RX_D_N10 C3 HSMA_TX_D_P7 B3 HSMA_TX_D_N7 K12 HSMA_RX_D_P1 J12 HSMA_RX_D_N1 D2 HSMA_TX_D_P5 C2 HSMA_TX_D_N5 G12 HSMA_RX_D_P4 G11 HSMA_RX_D_N4 E4 HSMA_TX_D_P2 D4 HSMA_TX_D_N2 K7 HSMA_RX_D_P3 K8 HSMA_RX_D_N3 E3 HSMA_TX_D_P3 E2 HSMA_TX_D_N3 G10 HSMA_RX_D_P7 F10 HSMA_RX_D_N7 E1 HSMA_TX_D_P4 D1 HSMA_TX_D_N4 J10 HSMA_RX_D_P2 J9 HSMA_RX_D_N2 E7 HSMA_CLK_OUT_P2 E6 HSMA_CLK_OUT_N2 F9 HSMA_RX_D_P8 F8 HSMA_RX_D_N8 G7 I2C_SCL_FPGA 0 F6 I2C_SDA_FPGA 0 D C I2C_SCL 16,20,26 I2C_SDA 16,20,26 R427 R426 5CSXFC6D_F896 B B A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 7 of 1 40 C 8 7 6 5 4 3 2 1 Cyclone V GX SoC Transceivers and Power E E U21M Cyclone V GX SoC Transceiver AE2 AE1 AC2 AC1 AA2 AA1 PCIE_RX_P0 PCIE_RX_N0 PCIE_RX_P1 PCIE_RX_N1 PCIE_RX_P2 PCIE_RX_N2 3 3 3 3 3 3 PCIE_REFCLK_QL0_P PCIE_REFCLK_QL0_N 10 10 GXB_RX_L0p,GXB_REFCLK_L0p GXB_RX_L0n,GXB_REFCLK_L0n GXB_RX_L1p,GXB_REFCLK_L1p GXB_RX_L1n,GXB_REFCLK_L1n GXB_RX_L2p,GXB_REFCLK_L2p GXB_RX_L2n,GXB_REFCLK_L2n W8 W7 GXB_LO GXB_TX_L0p GXB_TX_L0n GXB_TX_L1p GXB_TX_L1n GXB_TX_L2p GXB_TX_L2n AD4 AD3 AB4 AB3 Y4 Y3 PCIE_TX_P0 PCIE_TX_N0 PCIE_TX_P1 PCIE_TX_N1 PCIE_TX_P2 PCIE_TX_N2 3 3 3 3 3 3 REFCLK0Lp REFCLK0Ln CMU PLL (PCIe) D SDI_RX_P R137 SDI_RX_P SDI_RX_N 20 20 0 R135 0 R138 DNI HSMA_RX_P0 HSMA_RX_N0 17 17 SDI_RX_N CAD Note: Overlap R137 & R138 Overlap R135 & R136 PCIE_RX_P3 PCIE_RX_N3 3 3 GXB_RX_L4_P GXB_RX_L4_N R136 DNI CLK_148_P CLK_148_N W2 W1 U2 U1 R2 R1 GXB_RX_L3p,GXB_REFCLK_L3p GXB_RX_L3n,GXB_REFCLK_L3n GXB_RX_L4p,GXB_REFCLK_L4p GXB_RX_L4n,GXB_REFCLK_L4n GXB_RX_L5p,GXB_REFCLK_L5p GXB_RX_L5n,GXB_REFCLK_L5n T9 T8 GXB_L1 GXB_TX_L3p GXB_TX_L3n GXB_TX_L4p GXB_TX_L4n GXB_TX_L5p GXB_TX_L5n V4 V3 T4 T3 P4 P3 D PCIE_TX_P3 3 PCIE_TX_N3 3 GXB_TX_L4_P GXB_TX_L4_N HSMA_TX_P0 17 HSMA_TX_N0 17 R61 R63 R62 DNI REFCLK1Lp REFCLK1Ln 0 0 SDI_TX_P SDI_TX_N 20 20 CAD Note: Overlap R22 & R27 R60 Overlap R24 & R19 DNI SMA Connector Interface OPTION_SMA_XCVR_TX_P SMA Connector Interface J10 1 1OPTION_SMA_XCVR_RX_P 5 4 3 2 C J18 10 10 1OPTION_SMA_XCVR_RX_N HSMA_RX_P1 HSMA_RX_N1 HSMA_RX_P2 HSMA_RX_N2 HSMA_RX_P3 HSMA_RX_N3 N2 N1 L2 L1 J2 J1 REFCLK_QL2_P REFCLK_QL2_N P9 P8 GXB_RX_L6p,GXB_REFCLK_L6p GXB_RX_L6n,GXB_REFCLK_L6n GXB_RX_L7p,GXB_REFCLK_L7p GXB_RX_L7n,GXB_REFCLK_L7n GXB_RX_L8p,GXB_REFCLK_L8p GXB_RX_L8n,GXB_REFCLK_L8n GXB_TX_L6p GXB_TX_L6n GXB_TX_L7p GXB_TX_L7n GXB_TX_L8p GXB_TX_L8n REFCLK2Lp REFCLK2Ln RREF_TL M4 M3 K4 K3 H4 H3 G1 HSMA_TX_P1 17 HSMA_TX_N1 17 HSMA_TX_P2 17 HSMA_TX_N2 17 HSMA_TX_P3 17 HSMA_TX_N3 17 C CAD Note: Place resistors & capacitors near SMA connectors XCVR_RREF_TL 5CSXFC6D_F896 CAD Note: Place resistors & capacitors near SMA connectors J11 OPTION_SMA_XCVR_TX_N 1 2 3 4 5 17 17 17 17 17 17 2 3 4 5 GXB_L2 J19 5 4 3 2 SDI_TX_P SDI_TX_N R413 2.0K 1% CAD Note: Place resistor near RREF_TL pins. Route away frm aggressor SDI Reference Clocks 2.5V_REG_HPS DNI R54 B From MAXV 16 10,16 10,16 C62 C66 0.1uF 10uF B X3 SI571_EN 2 I2C_SDA_MAX 7 I2C_SCL_MAX 8 3 OE VDD SDA CLK+ SCL CLK- GND VC Si571 6 LVDS 4 CLK_148_CP C64 0.1uF CLK_148_P 5 CLK_148_CN C65 0.1uF CLK_148_N 1 SI571_VCONTROL SDI_CLK148_UP R58 4.99K From FPGA SDI_CLK148_DN 4 R59 4.99K 4 1000pF C53 R57 180K C50 0.1uF A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 8 of 1 40 C 8 7 HSMA_CLK_IN_P2 R412 6 5 4 3 2 1 Cyclone V GX SoC Clocks 100, 1% HSMA_CLK_IN_N2 E E U21N D D Cyclone V GX SoC Clocks CLK_BOT1 10 1.5 Volt R453 CLK_BOT1 AF15 AF14 0 R456 DNI USER_LED_FPGA[3:0] 4,23 USER_LED_FPGA1 USER_LED_FPGA2 Y16 W15 Bank 3B CLK0n,FPLL_BL_FBn,DIFFIO_RX_B31n CLK0p,FPLL_BL_FBp,DIFFIO_RX_B31p FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB,DIFFIO_TX_B37p,DQ5B,B_A_2 FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn,DIFFIO_TX_B37n,DQ5B,B_A_3 DDR3_FPGA_A[14:0] AH12 DDR3_FPGA_A2 AJ12 DDR3_FPGA_A3 4,13 CLK1n,DIFFIO_RX_B39n CLK1p,DIFFIO_RX_B39p 1.5 Volt USER_LED_FPGA3 CLK_ENET_FPGA_PHY CLK_ENET_FPGA_PHY 10 CLK_50M_FPGA 10 CLK_50M_FPGA AB17 AA16 AD17 AC18 C Bank 4A CLK2n,DIFFIO_RX_B47n CLK2p,DIFFIO_RX_B47p CLK3n,DIFFIO_RX_B55n CLK3p,DIFFIO_RX_B55p C 2.5 Volt CLK_TOP1 CLK_100M_FPGA Bank 5B 10 10 CLK_TOP1 CLK_100M_FPGA CLK_ENET_FPGA_P 10 CLK_ENET_FPGA_N 10 CLK_ENET_FPGA_P CLK_ENET_FPGA_N AA26 AB27 Y26 Y27 CLK5p,DIFFIO_RX_R21p,DQS3R CLK5n,DIFFIO_RX_R21n,DQSn3R FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB,DIFFIO_TX_R22p CLK4p,FPLL_BR_FBp,DIFFIO_RX_R23p,DQ3R CLK4n,FPLL_BR_FBn,DIFFIO_RX_R23n,DQ3R FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn,DIFFIO_TX_R22n,DQ3R AE29 PCIE_SMBCLK AD29 PCIE_SMBCLK PCIE_SMBCLK 3 PCIE_PRSNT2_X1 3 2.5 Volt Bank 8A HSMA_CLK_IN_P2 HSMA_CLK_IN_N2 17 17 HSMA_CLK_IN_P2 HSMA_CLK_IN_N2 H15 G15 HSMA_CLK_IN0 PCIE_SMBDAT 17 3 HSMA_CLK_IN0 PCIE_SMBDAT K14 J14 B CLK7p,DIFFIO_RX_T1p CLK7n,DIFFIO_RX_T1n FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn,DIFFIO_TX_T4n,DQ1T CLK6p,FPLL_TL_FBp,DIFFIO_RX_T9p CLK6n,FPLL_TL_FBn,DIFFIO_RX_T9n FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB,DIFFIO_TX_T4p,DQ1T A10 HSMA_CLK_OUT0 A11 PCIE_PRSNT2_X4 3 HSMA_CLK_OUT0 17 B 5CSXFC6D_F896 A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 9 of 1 40 C 8 7 6 5 4 3 2 1 PLL 3.3V DNI C214 PCIE_REFCLK_QL0_P C211 PCIE_REFCLK_SYN_P 2.5V_REG_HPS R250 2.5V_REG_HPS 0.1uF 2.2uF PCIE_REFCLK_QL0_N PCIE_REFCLK_SYN_N R252 E E DNI 1.00K SI570_EN DNI I2C_SDA_MAX DNI I2C_SCL_MAX C11 C7 0.1uF 2.2uF U49 1 10 X1 8,10,16 I2C_SDA_MAX 7 8,10,16 I2C_SCL_MAX 8 3 OE VCC SDA CLK+ SCL CLK- GND NC DanP:Consider to remove ac couplingl 4 REFCLK_QL2_C_P C19 100, 1% REFCLK_QL2_C_N C18 R18 5 C207 0.1uF REFCLK_QL2_P 8 4 Y4 25.00MHz 2 2 3 0.1uF REFCLK_QL2_N 8 DanP:Consider to DNI termination 1 DNI C206 DNI 4 5 SI570 Si570 Programmable Oscillator Use Clock Control GUI (Default 100MHz) I2C Address 66 HEX I2C_SCL_MAX I2C_SDA_MAX I2C_LSB FDBK_P FDBK_N 12 SCL 19 INTR CLK3B CLK3A SDA RSVD_GND EPAD 2.5V_REG_HPS 0.1uF 3 Y3 25.00MHz 2 2.5V_REG_HPS C134 DNI 2.5V_REG_HPS C142 C154 0.1uF 0.1uF A 1 2 VDD VDD XA_CLKIN XB_CLKINB VDDO0 VDDO1 VDDO2 VDDO3 1 4 C95 CLK125A_EN 12,16 CLK125A_EN D 12 19 3 5 6 8 7 24 11 15 16 20 8 9 10 13 14 X5 1 2 2.5V_PLL1 1V8_PLL 2.5V_REG_HPS 6 2.5V_PLL1 C465 C464 0.1uF 10uF EN OUT NC OUTn VCC GND CLK0A CLK0B P1 P2 P3 P5 P6 CLK1A CLK1B CLK2A CLK2B LOS CLK3A CLK3B GND RSVD_GND EPAD 24 7 L27 1V8 2.5V_PLL1 R111 C483 C484 0.1uF 0.1uF 1.00K CLK_BOT1 C503 C504 CLK_ENET_FPGA_N9 3 0.1uF 0.1uF OSC1_CLK_SEL = HIGH selects (OSC1_CLK_SMA) SMA input 2.5V_REG_HPS OSC1_CLK_SEL = LOW selects (OSC1_CLK_SYN) Si5356A input 2.5V_CLK_MUX L29 742792780 C674 C679 0.1uF 0.1uF 100MHz 9 742792780 25Mhz U52 10 7 OSC1_CLK_SYN 17 18 CLK_OSC2 21 22 CLK_TOP1 156.25MHz 9 J36 25Mhz 6 1 LTI-SASF546-P26-X1 OSC1_CLK_SMA 1 6 11 16 OSC1_CLK_SEL 23 25 R103 DNI R263 DNI 2.5V_REG_HPS 9 CMOS Clk_in0 Clk_in1 SEL3 SEL2 SEL1 SEL0 EN ICS83054I-01 2 R556 5 12 15 Q3 Q2 Q1 Q0 C 22CLK_OSC1 6 J13 1 2 OSC1_CLK_SEL 2.5V_REG_HPS R74 1.00K CON2 1V8 2.5V_REG_HPS R71 10K B 1V8 X4 CLK50_EN 16 2 1V8 CLK_ENET_FPGA_PHY 9 1 C115 C114 0.1uF 0.1uF EN GND 1V8 VCC OUT 50MHz U23 4 2 3 C361 CLKIN_50 1V8 C362 2.2uF 0.1uF 3 6 7 5 25Mhz 18 17 CLK_DUAL_ENET_PHY 19 14 13 CLK_100M_MAX 10 9 CLK_100M_FPGA 9 VDD CLKIN OE1 OE2 OE3 CLKOUT1 CLKOUT2 CLKOUT3 OE_OSC GND 25Mhz 8 R72 9 R64 10 22 22 4 CLK_50M_MAX CLK_50M_FPGA 16 9 1V8 1 SL18860DC 16 C391 C392 0.1uF 0.1uF 100Mhz TP7 100Mhz A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 4 23 25 Title Size B Date: 7 5 125.0MHz 1V8_PLL Si5335 8 CLK_ENET_FPGA_P 9 1V8 20 16 15 11 22 21 4 Si5356 Programmable Oscillator Use Clock Control GUI (Defaults 25MHz, 25MHz,25MHz,25MHz, 100MHz, 100MHz,50MHz, 50MHz) I2C Address 70 HEX 0.1uF B DNI CLK_DIFF2_N Si5338A-CUSTOM C153 U35 C135 9 0 PCIE_REFCLK_SYN_P 3 R249 0 PCIE_REFCLK_SYN_N 3 R251 3 14 4 5 6 DNI DNI CLK0B CLK0A C169 CLK_DIFF2_P VDDQ0 VDDQ1 2.5V_PLL1 R110 R109 CLKIN_P CLKIN_N CLKIN CLK1B CLK1A 0.1uF DIFF2 8 8 1 2 3 VDD1 VDD2 VDDO3 VDDO2 VDDO1 VDDO0 CLK2B CLK2A 0.1uF C84 U29 8,10,16 C165 VSS VSS2 CLK_DIFF1_N VDD Y2 25.00MHz 2 C C155 DIFF2 7 0 PCIE_REFCLK_QL0_P 8 R253 0 PCIE_REFCLK_QL0_N 8 R254 Si52112 2.5V_REG_HPS C102 742792780 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 8,10,16 1V8 XIN/CLKIN CLK_DIFF1_P VSS0 VSS1 C113 C83 1 DNI DIFF1 2.5V_REG_HPS R436 1.00K CLK125A_EN 4 C101 XOUT 6 L7 DNI 3 C89 DIFF1 5 4 3 2 D 2.5V_PLL1 VDD VDD2 4 13 12,16 6 3 2 1 SI570_EN PLL R13 R7 R14 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 10 of 1 40 C 8 7 6 5 4 3 2 1 Cyclone V GX SoC Configuration DNI C463 DNI U21G R432 DNI Cyclone V GX SoC Configuration E 15,16 FPGA_CONFIG_D0 FPGA_CONFIG_D1 FPGA_CONFIG_D2 FPGA_CONFIG_D3 FPGA_CONFIG_D4 FPGA_CONFIG_D5 FPGA_CONFIG_D6 FPGA_CONFIG_D7 FPGA_CONFIG_D8 FPGA_CONFIG_D9 FPGA_CONFIG_D10 FPGA_CONFIG_D11 FPGA_CONFIG_D12 FPGA_CONFIG_D13 FPGA_CONFIG_D14 FPGA_CONFIG_D15 D U7 FPGA_DCLK AE6 AE5 AE8 AC7 AB8 AE9 AE12 AD9 AD11 AF10 AD10 AE11 AC9 AH4 AE7 AG3 CLKUSR,DIFFIO_RX_B5p,DQ1B DCLK AS_DATA0,ASDO,DATA0 AS_DATA1,DATA1 AS_DATA2,DATA2 AS_DATA3,DATA3 nCSO,DATA4 DATA5,DIFFIO_TX_B2n DATA6,DIFFIO_RX_B1n,DQ1B DATA7,DIFFIO_TX_B2p,DQ1B DATA8,DIFFIO_RX_B1p,DQ1B DATA9,DIFFIO_TX_B4n,DQ1B DATA10,DIFFIO_RX_B3n,DQSn1B DATA11,DIFFIO_TX_B4p DATA12,DIFFIO_RX_B3p,DQS1B DATA13,DIFFIO_TX_B6n,DQ1B DATA14,DIFFIO_RX_B5n,DQ1B DATA15,DIFFIO_TX_B6p,DQ1B 2.5V_REG_FPGA D 10K 10K 10K 10K PR_READY,DIFFIO_TX_B8n,DQ1B PR_DONE,DIFFIO_RX_B7n PR_ERROR,DIFFIO_RX_B7p Bank 5A 2.5V BANK CPU_RESETn MAX_FPGA_MOSI 16,23 MAX_FPGA_MOSI 16 C MAX_FPGA_MISO MAX_FPGA_MISO 16 AD27 AE26 AD25 J5 F4 F3 FPGA_nCONFIG FPGA_nSTATUS FPGA_CONF_DONE 16 16 16 USER I/O INTERFACES PR_REQUEST,DIFFIO_TX_R1n,DQ1R CvP_CONFDONE,DIFFIO_TX_R3n,DQ1R CRC_ERROR,DIFFIO_RX_R2n DEV_CLRn,DIFFIO_TX_R5n,DQ1R DEV_OE,DIFFIO_TX_R5p nPERSTL0,DIFFIO_RX_R6p,DQS1R nPERSTR0,DIFFIO_RX_R6n,DQSn1R INIT_DONE,DIFFIO_RX_R2p nCEO,DIFFIO_TX_R3p,DQ1R nCONFIG nSTATUS CONF_DONE MSEL4 MSEL3 MSEL2 MSEL1 MSEL0 Bank 9A 2.5V BANK 2.5V_REG_FPGA R397 10K FPGA_nSTATUS R411 10K FPGA_CONF_DONE R415 10K FPGA_nCONFIG R414 10KJTAG_FPGA_TDI G5 R448 FPGA_CONFIG_D[15:0] Bank 3A 2.5V BANK R458 AD7 15,16 TMS TCK TDI TDO R457 V9 AC5 U8 AB9 JTAG_FPGA_TMS JTAG_MUX_TCK JTAG_FPGA_TDI JTAG_FPGA_TDO 12 12,16,17 12 12 E R459 R433 FPGA_DCLK AG8 AF5 AF4 AH28 AH29 AC25 MAX_FPGA_SSEL 16 FPGA_PR_READY FPGA_PR_DONE FPGA_PR_ERROR 16 16 16 FPGA_PR_REQUEST FPGA_CvP_CONFDONE 16 16 MAX_FPGA_SSEL W21 W22 PCIE_WAKEn PCIE_PERSTn AJ29 MAX_FPGA_SCK16 L9 L7 G6 K6 L8 3 3,4 C MAX_FPGA_SCK MSEL416 MSEL316 MSEL216 MSEL116 MSEL016 nCE 5CSXFC6D_F896 B B 2.5V_REG_FPGA 1 2 3 4 5 6 OPEN SW3 12 11 10 9 8 7 MSEL0 MSEL1 MSEL2 MSEL3 MSEL4 R306 R305 R304 R303 R302 1.00k 1.00k 1.00k 1.00k 1.00k TDA06H0SB1 A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 11 of 1 40 C 8 7 2.5V_REG_HPS R212 6 5 USB Blaster Programming Header (uses JTAG mode only) 1.00k 4 2.5V_REG_HPS J23 E 2 4 6 8 10 R209 0 1 3 5 7 9 JTAG_TCK 12,25 JTAG_BLASTER_TDI JTAG_TMS 12,25 JTAG_BLASTER_TDO 12,25 R210 1.00k R201 1.00k OPEN HPS_JTAG_EN FPGA_JTAG_EN HSMA_JTAG_EN MAX_JTAG_EN JTAG_BLASTER_TDI Populate R58 if you would like to Master the JTAG chain through HSMA HPS Logic 0 = pin 6 <--> pin 7 (HPS Bypass) Logic 1 = pin 6 <--> pin 4 (HPS Enable) 2.5V_REG_HPS JTAG Chain Control 8 7 6 5 DNI IN1 2 COM1 NO1 NC1 1 JTAG_TRST 6,16 MICTOR_RSTn 6,16,21 SW4 0 R40 JTAG_MUX_HPS_TDI R202 R325 R324 R323 R322 JTAG_MUX_TMS 1.00k 1.00k 1.00k 1.00k 1 U7 1 HPS_JTAG_EN JTAG_BLASTER_TDO 1 2 3 4 Logic 0 = pin 10 <--> pin 9 (HPS Bypass) Logic 1 = pin 10 <--> pin 2 (HPS Enable) 70247-1051 2 When Pins 1 & 5 are: TS5A23157 Switch FunctionsLOW --> NC to/from COM = ON and NO to/from COM = OFF HIGH --> NC to/from COM = OFF and NO to/from COM = ON JTAG 2.5V_REG_HPS USB_DISABLEn 25 3 HPS_JTAG_EN 3 NO2 5 V+ 1 JTAG_MUX_TDO 9 FPGA 2.5V_REG_HPS 8 C266 0 R24 E JTAG_FPGA_TDI 11,12 0 GND 4 10 0 IN2 NC2 COM2 Logic 0 = pin 10 <--> pin 9 (FPGA Bypass) Logic 1 = pin 10 <--> pin 2 (FPGA Enable) 0.1uF 2.5V_REG_HPS 7 6 BP_HPS_TMSR25 1.00k JTAG_HPS_TMS 6,12 TS5A23157 U8 TDA04H0SB1 ON = not-in-chain OFF = in-chain SW2 D OPEN 8 7 6 5 1 2 3 4 CLK125A_EN SI570_EN FACTORY_LOAD SECURITY_MODE CLK125A_EN 10,16 SI570_EN 10,16 FACTORY_LOAD16 SECURITY_MODE 16 2.5V_REG_HPS 10.0K 10.0K 1V8 10.0K 10.0K R317 R308 R307 R287 CLK125A_EN SI570_EN FACTORY_LOAD SECURITY_MODE FPGA_JTAG_EN 3.3V JTAG_MUX_TMS U16 16 2 JTAG_MICTOR_TCK 6,12 JTAG_MICTOR_TCK JTAG_MUX_TMS12 JTAG_MICTOR_TMS JTAG_MICTOR_TDO JTAG_MUX_HPS_TDI 11,12 6,12 11 10 JTAG_MICTOR_TDO 6,12 JTAG_FPGA_TDI JTAG_MICTOR_TDI 5 JTAG_MUX_TMS JTAG_MICTOR_TMS6 6,12 JTAG_MUX_HPS_TDI C 3 JTAG_FPGA_TDI 14 JTAG_MICTOR_TDI 13 VCC I0A YA I1A 4 I0B YB I1B DNI DNI 7 R401 R400 YC I1C YD I1D GND E 9 JTAG_HPS_TDI 12 1 HSMA_JTAG_EN Logic 0 = pin 6 <--> pin 7 (HSMA Bypass) Logic 1 = pin 6 <--> pin 4 (HSMA Enable) 6 JTAG_MUX_TMS R380 R381 DNI DNI JTAG_HPS_TDO JTAG_HPS_TDO 3.3V C41 2.2uF 0.1uF 3 4 5 HSMA_JTAG_EN 1 2 3 4 5 JTAG_HPS_SEL JTAG_HPS_SEL 881545-2 J6 1 2 CON2 MAX_JTAG_EN JTAG_MAX_TDO 16 Logic 0 = pin 6 <--> pin 7 (HSMBBypass) Logic 1 = pin 6 <--> pin 4 (HSMB Enable) JTAG_MUX_TMS U15 16 JTAG_TCK JTAG_MICTOR_TCK 12,25 JTAG_MICTOR_TCK 6,12 JTAG_TMS 12,25 JTAG_MICTOR_TMS 6,12 JTAG_BLASTER_TDI JTAG_MICTOR_TDI A JTAG_MICTOR_TDO 25 6,12 12,25 2 3 JTAG_TMS 5 JTAG_MICTOR_TMS 6 JTAG_BLASTER_TDI JTAG_MICTOR_TDI 6,12 JTAG_BLASTER_TDO JTAG_TCK JTAG_BLASTER_TDO JTAG_MICTOR_TDO 11 10 14 13 YA I1A 4 0 IN2 NC2 COM2 YB I1B 7 1 2 3 4 5 DNI JTAG_MUX_TCK DNI JTAG_MUX_TCK JTAG_BLASTER_TDI JTAG_MICTOR_TDI I0C YC I1C R405 R404 DNI JTAG_MUX_TMS DNI JTAG_MUX_TMS JTAG_MUX_TMS 12 9 IN1 COM1 NO1 1 NC1 0 GND NO2 V+ 1 IN2 0 NC2 COM2 D 0.1uF 2.5V_REG_HPS 7 BP_FPGA_TMS 6 JTAG_FPGA_TMS 11 R27 1.00k 10 9 0 JTAG_MAX_TDI R28 MAX 16 JTAG_HSMA_TDI 2.5V_REG_HPS 8 C264 0.1uF 2.5V_REG_HPS 7 6 BP_HSMA_TMS R29 C 1.00k JTAG_HSMA_TMS 17 TS5A23157 IN1 COM1 NO1 NC1 GND V+ NO2 NC2 IN2 COM2 R402 R403 DNI DNI 10 9 MUX 0 JTAG_MUX_TDI R30 12 JTAG_MAX_TDI 2.5V_REG_HPS 8 C263 0.1uF 2.5V_REG_HPS 7 BP_MAX_TMS 6 JTAG_MAX_TMS R31 1.00k 16 B I0D YD I1D E 12 JTAG_MUX_TDO JTAG_MUX_TDO BP_HPS_TMS R360 DNI JTAG_HPS_TMS JTAG_FPGA_TDO JTAG_FPGA_TDI JTAG_MUX_TMS BP_FPGA_TMS R359 R345 R358 R357 DNI HSMA DNI HSMA DNI JTAG_FPGA_TMS DNI JTAG_FPGA_TMS JTAG_HSMA_TDO JTAG_HSMA_TDI JTAG_MUX_TMS BP_HSMA_TMS R356 R344 R355 R354 DNI DNI DNI DNI MAX MAX JTAG_HSMA_TMS JTAG_HSMA_TMS JTAG_MUX_TDI JTAG_MUX_TDI JTAG_MUX_TDI JTAG_BLASTER_TDO R384 JTAG_MICTOR_TDO R385 DNI DNI DNI DNI JTAG_MUX_TDO JTAG_MUX_TDO JTAG_MAX_TDO JTAG_MAX_TDI JTAG_MUX_TMS BP_MAX_TMS R353 R343 R352 R351 DNI DNI DNI DNI MUX MUX JTAG_MAX_TMS JTAG_MAX_TMS XJ6 JTAG_MUX_TDO 3.3V 1 JTAG_SEL C38 C39 15 JTAG_SEL 2.2uF 0.1uF Title Size CON2 1.00k 6 B JTAG_SEL 5 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 881545-2 J7 1 2 Date: 7 C265 TS5A23157 R361 R346 HPS FPGA JTAG_MUX_TMS JTAG_MUX_TDI 12 IDTQS3VH257 3.3V R44 8 8 JTAG_MUX_TCK 11,12,16,17 JTAG_MUX_TCK JTAG_TMS JTAG_MICTOR_TMS I0B GND V+ 1 JTAG_FPGA_TDI11,12 2.5V_REG_HPS 0 GND NO2 9 0 JTAG_HSMA_TDI 17 R26 HSMA TS5A23157 I0A S 8 MAX_JTAG_EN R387 JTAG_TCK JTAG_MICTOR_TCK R386 VCC NC1 Logic 0 = pin 10 <--> pin 9 (MAX II Bypass) Logic 1 = pin 10 <--> pin 2 (MAX II Enable) U10 3.3V B NO1 10 XJ5 3.3V C40 JTAG_HSMA_TDO 17 JTAG_HPS_SEL 15 COM1 Logic 0 = pin 10 <--> pin 9 (HSMA Bypass) Logic 1 = pin 10 <--> pin 2 (HSMA Enable)U9 DNIJTAG_HPS_TDI DNIJTAG_HPS_TDI JTAG_HPS_TDO 6 IDTQS3VH257 1.00k FPGA_JTAG_EN JTAG_HPS_TMS 6,12 JTAG_FPGA_TDI JTAG_MICTOR_TDI I0D JTAG_HPS_TCK JTAG_HPS_TCK DNIJTAG_HPS_TMS DNIJTAG_HPS_TMS JTAG_MUX_HPS_TDI R398 JTAG_MICTOR_TDO R399 I0C R43 R383 R382 JTAG_HPS_TCK 6 JTAG_MUX_TMS JTAG_MICTOR_TMS S 8 JTAG_MUX_TCK JTAG_MICTOR_TCK 2 IN1 1 Logic 0 = pin 6 <--> pin 7 (FPGA Bypass) Logic 1 = pin 6 <--> pin 4 (FPGA Enable) TDA04H0SB1 JTAG_MUX_TCK11,12,16,17 JTAG_MUX_TCK JTAG_FPGA_TDO 11 1 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 12 of 1 40 C 8 7 DDR3_FPGA_CLK_P 100, 1% 6 5 4 E 4 4 4 4,9 3 2 1024MB DDR3 (x32) - FPGA DDR3_FPGA_CLK_N R469 4 4 VTT_FPGA_DDR3 DDR3_FPGA_BA[2:0] VTT_FPGA_DDR3 DDR3_FPGA_DM[3:0] 1 2 3 4 DDR3_FPGA_DQS_P[3:0] DDR3_FPGA_DQS_N[3:0] VTT_FPGA_DDR3 CN6 8 7 6 5 1 2 3 4 CN4 0.1uF 0.1uF VTT_FPGA_DDR3 CN5 8 1 7 2 6 3 5 4 0.1uF 8 7 6 5 V31 V30 V32 V28 V10 V37 V18 V24 V20 DDR3_FPGA_A11 DDR3_FPGA_A1 DDR3_FPGA_BA1 DDR3_FPGA_A9 DDR3_FPGA_ODT DDR3_FPGA_A14 DDR3_FPGA_BA2 DDR3_FPGA_A5 DDR3_FPGA_CKE RN4A 1 4 RN4D RN4G 7 2 RN5B RN5E 5 RN5H 8 3 RN6C RN6F 6 R472 16 51 V38 13 51 V33 10 51 V19 15 51 V36 12 51 V12 9 51 V15 14 51 V23 11 51 4.70K, 1% V35 VTT_FPGA_DDR3 1.5V_REG_FPGA RN4B 2 5 RN4E RN4H 8 3 RN5C RN5F 6 RN6A 1 4 RN6D RN6G 7 DDR3_FPGA_RESETn 2.00K 15 51 12 51 9 51 14 51 11 51 16 51 13 51 10 51 R497 DDR3_FPGA_A8 DDR3_FPGA_A4 DDR3_FPGA_A10 DDR3_FPGA_A13 DDR3_FPGA_CASn DDR3_FPGA_CSn DDR3_FPGA_A3 D C N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 K9 DDR3_FPGA_CKE DDR3_FPGA_CLK_P J7 DDR3_FPGA_CLK_N K7 DDR3_FPGA_CKE 4 DDR3_FPGA_CLK_P 4 DDR3_FPGA_CLK_N 4 E7 D3 DDR3_FPGA_DM2 DDR3_FPGA_DM3 4 4 DDR3_FPGA_DM2 DDR3_FPGA_DM3 DDR3_FPGA_CSn DDR3_FPGA_WEn DDR3_FPGA_RASn DDR3_FPGA_CASn 4 4 4 4 L2 DDR3_FPGA_CSn DDR3_FPGA_WEn L3 DDR3_FPGA_RASn J3 DDR3_FPGA_CASn K3 4 DDR3_FPGA_BA0 4 DDR3_FPGA_BA1 4 DDR3_FPGA_BA2 DDR3_FPGA_RESETn4 DDR3_FPGA_ODT 4 M2 DDR3_FPGA_BA0 N8 DDR3_FPGA_BA1 M3 DDR3_FPGA_BA2 DDR3_FPGA_RESETnT2 DDR3_FPGA_ODT K1 L8 DDR3_FPGA_ZQ1 VREF_FPGA_DDR3 H1 R473 M8 C590 B2 0.1uF D9 G7 240 K2 K8 N1 N9 R1 R9 1.5V_REG_FPGA A1 A8 C1 C9 D2 E9 F1 H2 H9 B 1.5V_REG_FPGA CS WE RAS CAS NC1 NC2 NC3 NC4 NC5 BA0 BA1 BA2 RESETn ODT ZQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VREFDQ VREFCA VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DDR3_FPGA_A0 DDR3_FPGA_A1 DDR3_FPGA_A2 DDR3_FPGA_A3 DDR3_FPGA_A4 DDR3_FPGA_A5 DDR3_FPGA_A6 DDR3_FPGA_A7 DDR3_FPGA_A8 DDR3_FPGA_A9 DDR3_FPGA_A10 DDR3_FPGA_A11 DDR3_FPGA_A12 DDR3_FPGA_A13 DDR3_FPGA_A14 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DDR3_FPGA_DQ16 DDR3_FPGA_DQ21 DDR3_FPGA_DQ17 DDR3_FPGA_DQ19 DDR3_FPGA_DQ20 DDR3_FPGA_DQ18 DDR3_FPGA_DQ22 DDR3_FPGA_DQ23 DDR3_FPGA_DQ24 DDR3_FPGA_DQ26 DDR3_FPGA_DQ25 DDR3_FPGA_DQ27 DDR3_FPGA_DQ29 DDR3_FPGA_DQ30 DDR3_FPGA_DQ28 DDR3_FPGA_DQ31 F3 G3 C7 B7 DDR3_FPGA_DQS_P2 DDR3_FPGA_DQS_N2 DDR3_FPGA_DQS_P3 DDR3_FPGA_DQS_N3 DDR3_FPGA_DM0 DDR3_FPGA_DM1 4 4 DDR3_FPGA_DM0 DDR3_FPGA_DM1 M2 DDR3_FPGA_BA0 N8 DDR3_FPGA_BA1 M3 DDR3_FPGA_BA2 DDR3_FPGA_RESETnT2 DDR3_FPGA_ODT K1 L8 DDR3_FPGA_ZQ VREF_FPGA_DDR3 H1 R471 M8 C586 B2 0.1uF D9 G7 240 K2 K8 N1 N9 R1 R9 1.5V_REG_FPGA A1 A8 C1 C9 D2 E9 F1 H2 H9 J2 J8 A9 M1 M9 B3 P1 P9 E1 T1 T9 G8 C572 C585 C601 C571 C598 C569 C589 C583 C597 C570 C574 C587 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 3.3nF 3.3nF 4.7nF 4.7nF 4.7nF E7 D3 L2 DDR3_FPGA_CSn DDR3_FPGA_WEn L3 DDR3_FPGA_RASn J3 DDR3_FPGA_CASn K3 B1 B9 D1 D8 E2 E8 F9 G1 G9 C602 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 K9 DDR3_FPGA_CKE DDR3_FPGA_CLK_P J7 DDR3_FPGA_CLK_N K7 J1 J9 L1 L9 M7 C568 DDR3 Device A0 A1 DQ0 A2 DQ1 A3 DQ2 A4 DQ3 A5 DQ4 A6 DQ5 A7 DQ6 A8 DQ7 A9 DQ8 A10/AP DQ9 A11 DQ10 A12/BCn DQ11 A13 DQ12 A14 DQ13 DQ14 CKE DQ15 CK_P CK_N LDQS_P LDQS_N LDM UDQS_P UDM UDQS_N CS WE RAS CAS BA0 BA1 BA2 RESETn ODT ZQ VREFDQ VREFCA VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 14 51 11 51 16 51 13 51 10 51 15 51 12 51 9 51 E VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DDR3_FPGA_DQ0 DDR3_FPGA_DQ1 DDR3_FPGA_DQ2 DDR3_FPGA_DQ3 DDR3_FPGA_DQ4 DDR3_FPGA_DQ5 DDR3_FPGA_DQ6 DDR3_FPGA_DQ7 DDR3_FPGA_DQ8 DDR3_FPGA_DQ9 DDR3_FPGA_DQ10 DDR3_FPGA_DQ11 DDR3_FPGA_DQ12 DDR3_FPGA_DQ13 DDR3_FPGA_DQ14 DDR3_FPGA_DQ15 F3 G3 C7 B7 DDR3_FPGA_DQS_P0 DDR3_FPGA_DQS_N0 DDR3_FPGA_DQS_P1 DDR3_FPGA_DQS_N1 D J1 J9 L1 L9 M7 C B1 B9 D1 D8 E2 E8 F9 G1 G9 B J2 J8 A9 M1 M9 B3 P1 P9 E1 T1 T9 G8 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 C603 C577 C596 C576 C579 C575 C578 C588 C584 Size 0.01uF 0.1uF 0.1uF 0.1uF 0.1uF 0.47uF 0.47uF 0.47uF 0.47uF B Date: 8 NC1 NC2 NC3 NC4 NC5 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Title 0.01uF 3 6 1 4 7 2 5 8 MT41K256M16HA-125:E 1.5V_REG_FPGA 0.01uF RN4C RN4F RN5A RN5D RN5G RN6B RN6E RN6H U38 DDR3 Device A0 A1 DQ0 A2 DQ1 A3 DQ2 A4 DQ3 A5 DQ4 A6 DQ5 A7 DQ6 A8 DQ7 A9 DQ8 A10/AP DQ9 A11 DQ10 A12/BCn DQ11 A13 DQ12 A14 DQ13 DQ14 CKE DQ15 CK_P CK_N LDQS_P LDQS_N LDM UDQS_P UDM UDQS_N MT41K256M16HA-125:E C599 DDR3_FPGA_A6 DDR3_FPGA_A12 DDR3_FPGA_A7 DDR3_FPGA_WEn DDR3_FPGA_RASn DDR3_FPGA_BA0 DDR3_FPGA_A0 DDR3_FPGA_A2 DDR3_FPGA_A[14:0] DDR3_FPGA_A0 DDR3_FPGA_A1 DDR3_FPGA_A2 DDR3_FPGA_A3 DDR3_FPGA_A4 DDR3_FPGA_A5 DDR3_FPGA_A6 DDR3_FPGA_A7 DDR3_FPGA_A8 DDR3_FPGA_A9 DDR3_FPGA_A10 DDR3_FPGA_A11 DDR3_FPGA_A12 DDR3_FPGA_A13 DDR3_FPGA_A14 C600 V34 V29 V25 V17 V11 V16 V26 V27 VTT_FPGA_DDR3 DDR3_FPGA_DQ[31:0] U37 A 1 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 13 of 1 40 C 8 7 DDR3_HPS_CLK_P 100, 1% E VTT_HPS_DDR3 1 2 3 4 DDR3_HPS_DQS_N[4:0] 5 2 VTT_HPS_DDR3 CN2 8 7 6 5 1 2 3 4 0.1uF VTT_HPS_DDR3 CN1 8 1 7 2 6 3 5 4 CN3 0.1uF DDR3_HPS_A8 DDR3_HPS_A6 DDR3_HPS_A10 DDR3_HPS_A0 DDR3_HPS_A14 DDR3_HPS_A1 DDR3_HPS_RASn DDR3_HPS_A7 DDR3_HPS_CKE 8 7 6 5 0.1uF 1 4 7 2 5 8 3 6 R420 RN1A RN1D RN1G RN2B RN2E RN2H RN3C RN3F 16 51 13 51 10 51 15 51 12 51 9 51 14 51 11 51 4.70K, 1% VTT_HPS_DDR3 RN1B 2 5 RN1E RN1H 8 3 DDR3_HPS_A13 RN2C 6 DDR3_HPS_CASn RN2F RN3A 1 DDR3_HPS_ODT 4 DDR3_HPS_A3 RN3D DDR3_HPS_A5 RN3G 7 DDR3_HPS_RESETn 2.00K VTT_HPS_DDR3 1.5V_REG_HPS 15 51 12 51 9 51 14 51 11 51 16 51 13 51 10 51 R431 DDR3_HPS_BA2 DDR3_HPS_A12 1 DDR3_HPS_A4 DDR3_HPS_BA1 DDR3_HPS_A9 DDR3_HPS_A2 DDR3_HPS_A11 DDR3_HPS_CSn DDR3_HPS_BA0 DDR3_HPS_WEn RN1C RN1F RN2A RN2D RN2G RN3B RN3E RN3H 3 6 1 4 7 2 5 8 14 11 16 13 10 15 12 9 51 51 51 51 51 51 51 51 E DDR3_HPS_DQ[39:0] 5 DDR3_HPS_A[14:0] 5 U30 N3 DDR3_HPS_A0 P7 DDR3_HPS_A1 P3 DDR3_HPS_A2 N2 DDR3_HPS_A3 P8 DDR3_HPS_A4 P2 DDR3_HPS_A5 R8 DDR3_HPS_A6 R2 DDR3_HPS_A7 T8 DDR3_HPS_A8 R3 DDR3_HPS_A9 DDR3_HPS_A10 L7 DDR3_HPS_A11 R7 DDR3_HPS_A12 N7 DDR3_HPS_A13 T3 DDR3_HPS_A14 T7 D K9 DDR3_HPS_CKE DDR3_HPS_CLK_P J7 DDR3_HPS_CLK_N K7 DDR3_HPS_CKE 5 DDR3_HPS_CLK_P5 DDR3_HPS_CLK_N5 1.5V_REG_HPS DDR3_HPS_CSn DDR3_HPS_WEn DDR3_HPS_RASn DDR3_HPS_CASn C DDR3_HPS_BA0 DDR3_HPS_BA1 DDR3_HPS_BA2 DDR3_HPS_RESETn DDR3_HPS_ODT DDR3_HPS_DM4 R452 240 E7 D3 5 5 5 5 DDR3_HPS_CSn DDR3_HPS_WEn DDR3_HPS_RASn DDR3_HPS_CASn L2 L3 J3 K3 5 5 5 5 5 M2 DDR3_HPS_BA0 N8 DDR3_HPS_BA1 M3 DDR3_HPS_BA2 DDR3_HPS_RESETn T2 K1 DDR3_HPS_ODT L8 DDR3_HPS_ZQ1 VREF_HPS_DDR3 H1 R447 M8 C493 B2 0.1uF D9 G7 240 K2 K8 N1 N9 R1 R9 1.5V_REG_HPS A1 A8 C1 C9 D2 E9 F1 H2 H9 B 1.5V_REG_HPS U22 DDR3 Device A0 A1 DQ0 A2 DQ1 A3 DQ2 A4 DQ3 A5 DQ4 A6 DQ5 A7 DQ6 A8 DQ7 A9 DQ8 A10/AP DQ9 A11 DQ10 A12/BCn DQ11 A13 DQ12 A14 DQ13 DQ14 CKE DQ15 CK_P CK_N LDQS_P LDQS_N LDM UDQS_P UDM UDQS_N N3 DDR3_HPS_A0 P7 DDR3_HPS_A1 P3 DDR3_HPS_A2 N2 DDR3_HPS_A3 P8 DDR3_HPS_A4 P2 DDR3_HPS_A5 R8 DDR3_HPS_A6 R2 DDR3_HPS_A7 T8 DDR3_HPS_A8 R3 DDR3_HPS_A9 DDR3_HPS_A10 L7 DDR3_HPS_A11 R7 DDR3_HPS_A12 N7 DDR3_HPS_A13 T3 DDR3_HPS_A14 T7 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DDR3_HPS_DQ35 DDR3_HPS_DQ32 DDR3_HPS_DQ34 DDR3_HPS_DQ39 DDR3_HPS_DQ36 DDR3_HPS_DQ38 DDR3_HPS_DQ37 DDR3_HPS_DQ33 R438 10.0K R462 10.0K R439 10.0K R463 10.0K R441 10.0K R464 10.0K R440 10.0K R465 10.0K F3 G3 C7 B7 DDR3_HPS_DQS_P4 DDR3_HPS_DQS_N4 R450 240 R451 240 K9 DDR3_HPS_CKE DDR3_HPS_CLK_P J7 DDR3_HPS_CLK_N K7 1.5V_REG_HPS CS WE RAS CAS NC1 NC2 NC3 NC4 NC5 BA0 BA1 BA2 RESETn ODT ZQ VREFDQ VREFCA VDD VDD VDD VDD VDD VDD VDD VDD VDD VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ J1 J9 L1 L9 M7 DDR3_HPS_DM2 DDR3_HPS_DM3 E7 D3 DDR3_HPS_CSn DDR3_HPS_WEn DDR3_HPS_RASn DDR3_HPS_CASn L2 L3 J3 K3 M2 DDR3_HPS_BA0 N8 DDR3_HPS_BA1 M3 DDR3_HPS_BA2 DDR3_HPS_RESETn T2 K1 DDR3_HPS_ODT L8 DDR3_HPS_ZQ2 VREF_HPS_DDR3 H1 R425 M8 C285 B2 0.1uF D9 G7 240 K2 K8 N1 N9 R1 R9 1.5V_REG_HPS A1 A8 C1 C9 D2 E9 F1 H2 H9 B1 B9 D1 D8 E2 E8 F9 G1 G9 J2 J8 A9 M1 M9 B3 P1 P9 E1 T1 T9 G8 MT41K256M16HA-125:E A 3 VTT_HPS_DDR3 DDR3_HPS_DQS_P[4:0] 5 4 1024MB DDR3 (x32 + ECC) - HPS DDR3_HPS_DM[4:0] 5 5 DDR3_HPS_CLK_N R428 DDR3_HPS_BA[2:0] 5 6 U14 DDR3 Device A0 A1 DQ0 A2 DQ1 A3 DQ2 A4 DQ3 A5 DQ4 A6 DQ5 A7 DQ6 A8 DQ7 A9 DQ8 A10/AP DQ9 A11 DQ10 A12/BCn DQ11 A13 DQ12 A14 DQ13 DQ14 CKE DQ15 CK_P CK_N LDQS_P LDQS_N LDM UDQS_P UDM UDQS_N CS WE RAS CAS BA0 BA1 BA2 RESETn ODT ZQ VREFDQ VREFCA VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ NC1 NC2 NC3 NC4 NC5 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DDR3_HPS_DQ21 DDR3_HPS_DQ23 DDR3_HPS_DQ20 DDR3_HPS_DQ22 DDR3_HPS_DQ16 DDR3_HPS_DQ18 DDR3_HPS_DQ17 DDR3_HPS_DQ19 DDR3_HPS_DQ29 DDR3_HPS_DQ27 DDR3_HPS_DQ24 DDR3_HPS_DQ31 DDR3_HPS_DQ28 DDR3_HPS_DQ30 DDR3_HPS_DQ25 DDR3_HPS_DQ26 F3 G3 C7 B7 DDR3_HPS_DQS_P2 DDR3_HPS_DQS_N2 DDR3_HPS_DQS_P3 DDR3_HPS_DQS_N3 J1 J9 L1 L9 M7 N3 DDR3_HPS_A0 P7 DDR3_HPS_A1 P3 DDR3_HPS_A2 N2 DDR3_HPS_A3 P8 DDR3_HPS_A4 P2 DDR3_HPS_A5 R8 DDR3_HPS_A6 R2 DDR3_HPS_A7 T8 DDR3_HPS_A8 R3 DDR3_HPS_A9 DDR3_HPS_A10 L7 DDR3_HPS_A11 R7 DDR3_HPS_A12 N7 DDR3_HPS_A13 T3 DDR3_HPS_A14 T7 DDR3 Device A0 A1 DQ0 A2 DQ1 A3 DQ2 A4 DQ3 A5 DQ4 A6 DQ5 A7 DQ6 A8 DQ7 A9 DQ8 A10/AP DQ9 A11 DQ10 A12/BCn DQ11 A13 DQ12 A14 DQ13 DQ14 CKE DQ15 CK_P CK_N LDQS_P LDQS_N LDM UDQS_P UDM UDQS_N K9 DDR3_HPS_CKE DDR3_HPS_CLK_P J7 DDR3_HPS_CLK_N K7 DDR3_HPS_DM0 DDR3_HPS_DM1 E7 D3 DDR3_HPS_CSn DDR3_HPS_WEn DDR3_HPS_RASn DDR3_HPS_CASn L2 L3 J3 K3 CS WE RAS CAS M2 DDR3_HPS_BA0 N8 DDR3_HPS_BA1 M3 DDR3_HPS_BA2 DDR3_HPS_RESETn T2 K1 DDR3_HPS_ODT L8 DDR3_HPS_ZQ VREF_HPS_DDR3 H1 R372 M8 C445 B2 0.1uF D9 G7 240 K2 K8 N1 N9 R1 R9 1.5V_REG_HPS A1 A8 C1 C9 D2 E9 F1 H2 H9 B1 B9 D1 D8 E2 E8 F9 G1 G9 J2 J8 A9 M1 M9 B3 P1 P9 E1 T1 T9 G8 MT41K256M16HA-125:E BA0 BA1 BA2 RESETn ODT ZQ VREFDQ VREFCA VDD VDD VDD VDD VDD VDD VDD VDD VDD C283 C289 C518 C366 C549 C517 C364 C520 C443 C288 C420 C419 C491 C396 C324 C369 C495 C310 C447 C519 C545 C444 C325 C284 C365 C492 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 3.3nF 3.3nF 4.7nF 4.7nF 4.7nF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF Title C446 C294 C367 C506 C546 C309 C418 C496 C287 C370 C497 C371 C286 C368 C494 C327 C448 C548 Size 0.01uF 0.01uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.47uF 0.47uF 0.47uF 0.47uF 0.47uF 0.47uF 0.47uF 0.47uF B Date: 8 DDR3_HPS_DQS_P0 DDR3_HPS_DQS_N0 DDR3_HPS_DQS_P1 DDR3_HPS_DQS_N1 J1 J9 L1 L9 M7 DDR3 ECC TEST C TP5 DDR3_HPS_DQ14 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B1 B9 D1 D8 E2 E8 F9 G1 G9 R390 10.0K TP6 DDR3_HPS_DQ15 J2 J8 A9 M1 M9 B3 P1 P9 E1 T1 T9 G8 B TP3 R389 10.0K A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 1.5V_REG_HPS 0.01uF F3 G3 C7 B7 D MT41K256M16HA-125:E C311 C326 DDR3_HPS_DQ2 DDR3_HPS_DQ4 DDR3_HPS_DQ7 DDR3_HPS_DQ5 DDR3_HPS_DQ3 DDR3_HPS_DQ0 DDR3_HPS_DQ6 DDR3_HPS_DQ1 DDR3_HPS_DQ10 DDR3_HPS_DQ13 DDR3_HPS_DQ8 DDR3_HPS_DQ12 DDR3_HPS_DQ11 DDR3_HPS_DQ15 DDR3_HPS_DQ9 DDR3_HPS_DQ14 TP4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ C328 C547 NC1 NC2 NC3 NC4 NC5 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 14 of 1 40 C 8 7 6 5 4 3 2 1 FLASH, EPCQ FM BUS EPCQ FM_A[26:1] 16 E NOR PARALLEL FLASH FM_D[15:0] 16 E FLASH 512Mb (32M X 16) U6 5.0V FM_A1 FM_A2 FM_A3 FM_A4 FM_A5 FM_A6 FM_A7 FM_A8 FM_A9 FM_A10 FM_A11 FM_A12 FM_A13 FM_A14 FM_A15 FM_A16 FM_A17 FM_A18 FM_A19 FM_A20 FM_A21 FM_A22 FM_A23 FM_A24 FM_A25 FM_A26 3.3V C316 C315 0.1uF 0.1uF C30 C31 0.1uF 0.1uF U13 1 2 VCC NC01 NC02 NC03 NC04 NC05 NC06 NC07 NC08 EPCQ256 DATA0 DATA1 DATA2 DATA3 DCLK nCS GND U20 3 4 5 6 11 12 13 14 FPGA_AS_DATA0 FPGA_AS_DATA1 FPGA_AS_DATA2 FPGA_AS_DATA3 FPGA_nCSO 15 8 9 1 16 7 FPGA_AS_DATA0 FPGA_AS_DATA1 FPGA_AS_DATA2 FPGA_AS_DATA3 FPGA_DCLK 11,16 FPGA_nCSO 2 3 4 5 6 7 8 9 10 11 23 10 D NC VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BE GND 24 22 21 20 19 18 17 16 15 14 13 FPGA_CONFIG_D0 FPGA_CONFIG_D1 FPGA_CONFIG_D2 FPGA_CONFIG_D3 FPGA_CONFIG_D4 11,16 11,16 11,16 11,16 11,16 FPGA_CONFIG_D0 FPGA_CONFIG_D1 FPGA_CONFIG_D2 FPGA_CONFIG_D3 FPGA_CONFIG_D4 12 IDTQS3861 MAX_AS_CONF 16 9V_VPP XJ1 C J5 1 2 881545-2 VPP CON2 12V 9V_VPP C22 4.7uF 3 4.7K R335 VIN VOUT ADJ/BYPASS SHDN GND LT1761 5 4 2 D13 LT1761_CSENSE R333 16 FLASH_CLK 16 16 16 16 16 FLASH_RESETn FLASH_CEn0 FLASH_OEn FLASH_WEn FLASH_ADVn FLASH_WPn VPP U4 1 VPP PC28FxxxP30B85 FLASH 1V8 A1 B1 C1 D1 D2 A2 C2 A3 B3 C3 D3 C4 A5 B5 C5 D7 D8 A7 B7 C7 C8 A8 G1 H8 B6 B8 E6 D4 B4 F8 G8 F6 C6 VPP A1 A2 VCC A3 VCC A4 A5 VCCQ A6 VCCQ A7 VCCQ A8 A9 D0 A10 D1 A11 D2 A12 D3 A13 D4 A14 D5 A15 D6 A16 D7 A17 A18 D8 A19 D9 A20 D10 A21 D11 A22 D12 NC(64M)/A23 D13 NC(64M,128M)/A24 D14 NC/A25(512M) D15 NC/A26(1G) WAIT CLK GND RESET# GND CE# GND OE# GND WE# ADV# RFU0 WP# RFU1 RFU2 RFU3 1V8 A4 A6 H3 1V8 D5 D6 G4 D F2 E2 G3 E4 E5 G5 G6 H7 FM_D0 FM_D1 FM_D2 FM_D3 FM_D4 FM_D5 FM_D6 FM_D7 E1 E3 F3 F4 F5 H5 G7 E7 FM_D8 FM_D9 FM_D10 FM_D11 FM_D12 FM_D13 FM_D14 FM_D15 F7 FLASH_RDYBSYn 16 C B2 H2 H4 H6 H1 G2 F1 E8 36K PC28F512P30BF CMDSH-3 R334 5.62k C17 4.7uF 1V8 1V8 B R363 R336 R326 10K 10K 10K FLASH_WPn FLASH_WEn FLASH_RDYBSYn R362 10K FLASH_RESETn 1V8 B C246 C247 C257 C253 C268 C267 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF - When using a single x16 flash device a word consists of 16 data bits so addressing starts with FM_A1 mapped to address bit 1 in software. A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 15 of 1 40 C 8 7 6 5 4 3 5M2210 System Controller U19A E D FPGA_CONFIG_D0 FPGA_CONFIG_D1 FPGA_CONFIG_D2 FPGA_CONFIG_D3 FPGA_CONFIG_D4 FPGA_CONFIG_D5 FPGA_CONFIG_D6 FPGA_CONFIG_D7 D3 C2 C3 E3 D2 E4 D1 E5 FPGA_CONFIG_D8 FPGA_CONFIG_D9 FPGA_CONFIG_D10 FPGA_CONFIG_D11 FPGA_CONFIG_D12 FPGA_CONFIG_D13 FPGA_CONFIG_D14 FPGA_CONFIG_D15 F3 E1 F4 F2 F1 F6 G2 G3 MAX_FPGA_MOSI MAX_FPGA_MISO MAX_AS_CONF MAX_FPGA_SSEL MAX_FPGA_SCK G1 G4 H2 G5 H3 J1 H4 J2 H5 J5 USB_B2_CLK CLK_100M_MAX DIFFIO_L1P DIFFIO_L1N DIFFIO_L2P DIFFIO_L2N DIFFIO_L3P DIFFIO_L3N DIFFIO_L4P DIFFIO_L4N DIFFIO_L13P DIFFIO_L13N DIFFIO_L14P DIFFIO_L14N DIFFIO_L15P DIFFIO_L15N DIFFIO_L16P DIFFIO_L16N DIFFIO_L5P DIFFIO_L5N DIFFIO_L6P DIFFIO_L6N DIFFIO_L7P DIFFIO_L7N DIFFIO_L8P DIFFIO_L8N DIFFIO_L17P DIFFIO_L17N DIFFIO_L18P DIFFIO_L18N DIFFIO_L19P DIFFIO_L19N DIFFIO_L20P DIFFIO_L20N DIFFIO_L9P DIFFIO_L21P DIFFIO_L9N DIFFIO_L21N DIFFIO_L10P DIFFIO_L10N IOB1_1 DIFFIO_L11P IOB1_2 DIFFIO_L11N IOB1_3 DIFFIO_L12P IOB1_4 DIFFIO_L12N IOB1_5 IOB1/CLK0 IOB1/CLK1 J4 K1 J3 K2 K5 L1 L2 0 K3 0 FPGA_nSTATUS FPGA_CONF_DONE FPGA_DCLK M1 M2 L4 L3 N1 M4 N2 M3 I2C_SCL_MAX I2C_SDA_MAX N3 P2 FPGA_CvP_CONFDONE FPGA_PR_ERROR HSMA_PRSNTn E2 F5 H1 K4 L5 FPGA_PR_READY FPGA_PR_REQUEST FPGA_PR_DONE CLK50_EN CLK125A_EN R552 R546 JTAG_TRST 6,12 MICTOR_RSTn 6,12,21 A5 D7 B6 E7 C8 B7 D8 A7 FPGA_nCONFIG Si570_EN M570_PCIE_JTAG_EN B8 A8 A9 E9 B9 D9 A10 C9 DIFFIO_T1P DIFFIO_T1N DIFFIO_T2P DIFFIO_T2N DIFFIO_T3P DIFFIO_T3N DIFFIO_T4P DIFFIO_T4N DIFFIO_T13P DIFFIO_T13N DIFFIO_T14P DIFFIO_T14N DIFFIO_T15P DIFFIO_T15N DIFFIO_T16P DIFFIO_T16N DIFFIO_T5P DIFFIO_T5N DIFFIO_T6P DIFFIO_T6N DIFFIO_T7P DIFFIO_T7N DIFFIO_T8P DIFFIO_T8N DIFFIO_T17P DIFFIO_T17N DIFFIO_T18P DIFFIO_T18N IOB2_6 IOB2_7 DIFFIO_T9P DIFFIO_T9N DIFFIO_T10P DIFFIO_T10N DIFFIO_T11P DIFFIO_T11N DIFFIO_T12P DIFFIO_T12N IOB2_8 IOB2_9 IOB2_10 IOB2_11 IOB2_12 IOB2_13 IOB2_14 IOB2_15 IOB2_16 IOB2_17 IOB2_18 IOB2_19 IOB2_20 JTAG_MUX_TCK P3 L6 M5 N4 TCK TDI TDO TMS D4 B1 C5 C4 B4 D6 E6 B5 SI571_EN MAX V BANK2 11,12,17 JTAG_MAX_TDI 12 JTAG_MAX_TDO 12 JTAG_MAX_TMS 12 E10 A11 B11 A12 E11 B12 C11 B13 F13 E15 E16 F15 G14 F16 G13 G15 FM_A8 FM_A9 FM_A10 FM_A11 FM_A12 FM_A13 FM_A14 FM_A15 B G12 G16 H14 H15 H13 H16 J13 J16 FM_A16 FM_A17 FM_A18 FM_A19 FM_A20 FM_A21 FM_A22 FM_A23 CLK_50M_MAX J12 H12 PGM_CONFIG PGM_LED0 PGM_LED1 PGM_LED2 MAX_FPGA_SSEL 11 MAX_FPGA_SCK11 DIFFIO_R1P DIFFIO_R1N DIFFIO_R2P DIFFIO_R2N DIFFIO_R3P DIFFIO_R3N DIFFIO_R4P DIFFIO_R4N DIFFIO_R13P DIFFIO_R13N DIFFIO_R14P DIFFIO_R14N DIFFIO_R15P DIFFIO_R15N DIFFIO_R16P DIFFIO_R16N DIFFIO_R5P DIFFIO_R5N DIFFIO_R6P DIFFIO_R6N DIFFIO_R7P DIFFIO_R7N DIFFIO_R8P DIFFIO_R8N DIFFIO_R17P DIFFIO_R17N DIFFIO_R18P DIFFIO_R18N DIFFIO_R19P DIFFIO_R19N DIFFIO_R20P DIFFIO_R20N DIFFIO_R9P DIFFIO_R9N DIFFIO_R10P DIFFIO_R10N DIFFIO_R11P DIFFIO_R11N DIFFIO_R12P DIFFIO_R12N DIFFIO_R21P DIFFIO_R21N DIFFIO_R22P DIFFIO_R22N IOB3/CLK2 IOB3/CLK3 IOB3_21 IOB3_22 IOB3_23 IOB3_24 IOB3_25 IOB3_26 IOB3_27 L15 L12 M16 L13 M15 L14 N16 M13 R1 P4 T2 P5 R3 N5 P6 N6 FM_D0 FM_D1 FM_D2 FM_D3 FM_D4 FM_D5 FM_D6 FM_D7 R5 M6 T5 P7 R6 N7 M7 R7 FM_D8 FM_D9 FM_D10 FM_D11 FM_D12 FM_D13 FM_D14 FM_D15 N15 N14 P15 P14 FLASH_WEn FLASH_CEn0 FLASH_OEn FLASH_RDYBSYn D13 D14 F11 FLASH_RESETn FLASH_CLK FLASH_ADVn F12 K12 M14 N13 FM_A24 FM_A25 FM_A26 USB_CFG2 USB_CFG3 USB_CFG4 USB_CFG5 USB_CFG6 USB_CFG7 USB_CFG8 USB_CFG9 P8 T7 N8 R8 T8 T9 R9 P9 MAX_RESETn USB_CFG10 M9 M8 MAX_FPGA_SSEL MAX_FPGA_SCK CLK_50M_MAX CLK_100M_MAX DIFFIO_B5P DIFFIO_B5N DIFFIO_B6P DIFFIO_B6N DIFFIO_B7P DIFFIO_B7N DIFFIO_B8P DIFFIO_B8N DIFFIO_B19P DIFFIO_B19N DIFFIO_B18P DIFFIO_B18N DIFFIO_B20P DIFFIO_B20N DIFFIO_B21P DIFFIO_B21N I2C_SCL_MAX I2C_SDA_MAX 0 I2C_SCL R424 0 I2C_SDA R423 10K I2C_SCL_MAX 10K I2C_SDA_MAX DIFFIO_B9P DIFFIO_B22P DIFFIO_B9N DIFFIO_B22N DIFFIO_B10P IOB4_28 DIFFIO_B10N IOB4_29 DIFFIO_B11P IOB4_30 DIFFIO_B11N IOB4_31 DIFFIO_B12P IOB4_32 DIFFIO_B12N IOB4_33 F7 G6 H7 H9 J10 J8 K11 L10 M10 R10 N10 T11 P10 R11 T12 N11 T13 R13 R12 P11 N12 R14 P12 T15 R16 P13 M11 M12 N9 R4 T10 T4 EXTRA_SIG1 SECURITY_MODE M570_CLOCK FACTORY_STATUS FACTORY_REQUEST EXTRA_SIG2 TRST RST 15 15 FLASH_OEn FLASH_RDYBSYn 15 15 FLASH_RESETn FLASH_CLK FLASH_ADVn 15 15 15 CLK125A_EN CLK50_EN Si570_EN SI571_EN 10,12 10 10,12 8 10 10 1V8 2.5V_REG_HPS 25 25 USB_CFG0 USB_CFG11 USB_CFG1 DIFFIO_B13N/DEV_CLRn DIFFIO_B13P/DEV_OE HSMA_PRSNTn MAX_FPGA_MOSI MAX_FPGA_MISO I2C_SCL_MAX 8,10 I2C_SDA_MAX 8,10 A1 A16 B15 B2 G10 G7 G8 G9 K10 K7 K8 K9 R15 R2 T1 T16 T6 GNDINT GNDINT GNDINT GNDINT GNDINT GNDINT GNDINT GNDINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO CPU_RESETn 1V8 MAX V Power VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 F10 G11 H10 H8 J7 J9 K6 L7 4,17,23 11 11 11,23 C ON-BOARD USB BLASTER II USB_CFG[11:0] EXTRA_SIG[2:0] 2.5V_REG_HPS USB_B2_CLK PCIE_JTAG_EN M570_PCIE_JTAG_EN M570_CLOCK FACTORY_STATUS FACTORY_REQUEST C1 H6 J6 P1 A14 A3 F8 F9 25 USB_CFG[11:0] 25 EXTRA_SIG[2:0] 4,25 25 25 25 25 MAXV DIPSWITCH CLK_SEL 1V8 C16 H11 J11 P16 FACTORY_LOAD SECURITY_MODE B 12 12 PUSH BUTTON INTERFACE 1.5V_REG_HPS PGM_SEL PGM_CONFIG MAX_RESETn L8 L9 T14 T3 23 23 23 PGM_SEL PGM_CONFIG MAX_RESETn 23 PGM_LED[2:0] 23 23 23 MAX_ERROR MAX_LOAD MAX_CONF_DONE LED INTERFACE PGM_LED[2:0] 5M2210ZF256 1.5V_REG_HPS MAX_FPGA_MOSI MAX_FPGA_MISO MAX_AS_CONF 15,16 MAX_ERROR MAX_LOAD MAX_CONF_DONE 1V8 2.5V VCCIO D 7,20,26 5M2210ZF256 VCCINT 11 11 11 11 11 7,20,26 5M2210ZF256 A E MSEL0 MSEL1 MSEL2 MSEL3 MSEL4 U19E DIFFIO_B14P DIFFIO_B14N DIFFIO_B15P DIFFIO_B15N DIFFIO_B16P DIFFIO_B16N DIFFIO_B17P DIFFIO_B17N FLASH_WEn FLASH_CEn0 MAX_AS_CONF 15,16 PCIE_JTAG_EN CPU_RESETn SDI_TX_EN SDI_RX_BYPASS SDI_RX_EN 2.5V_REG_HPS R419 R418 DIFFIO_B1P DIFFIO_B1N DIFFIO_B2P DIFFIO_B2N DIFFIO_B3P DIFFIO_B3N DIFFIO_B4P DIFFIO_B4N 15 SDI_TX_EN 5,20 SDI_RX_BYPASS 5,20 SDI_RX_EN 5,20 MAX V BANK4 J14 J15 K16 K13 K15 K14 L16 L11 15 FM_A[26:0] 11 11 11,15 11 PGM_SEL A2 FACTORY_LOAD A4 MAX_ERROR A6 MAX_LOAD B10 MSEL0 B3 MSEL1 C10 MSEL2 C12 MSEL3 C6 MSEL4 C7 D10 D11 D5 E8 11,15 FPGA_PR_DONE 11 FPGA_PR_REQUEST 11 FPGA_PR_READY 11 FPGA_PR_ERROR 11 FPGA_CvP_CONFDONE11 U19D MAX V BANK3 E14 C14 C15 E13 E12 D15 F14 D16 HPS_RESETn A13 CLK_SEL A15 5M2210ZF256 FM_A0 FM_A1 FM_A2 FM_A3 FM_A4 FM_A5 FM_A6 FM_A7 FPGA_nSTATUS FPGA_CONF_DONE FPGA_DCLK FPGA_nCONFIG MAX_CONF_DONE D12 B14 C13 B16 5M2210ZF256 U19C OVERTEMP 26 USB_RESET 22 HPS_RESETn 6,21 1 FM_D[15:0] FPGA_CONFIG_D[15:0] U19B MAX V BANK1 C 2 1.5V VCCIO A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 C345 C322 C320 C304 C319 C318 C321 C337 C346 C305 C281 C282 C306 C323 C291 C394 C317 C395 C336 C393 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 16 of 1 40 C 8 7 6 5 4 3 2 1 HSMC Port A J12 HSMA_SDA JTAG_MUX_TCK JTAG_HSMA_TDO HSMA_CLK_OUT0 HSMA_TX_P3 HSMA_TX_N3 HSMA_TX_P2 HSMA_TX_N2 HSMA_TX_P1 HSMA_TX_N1 HSMA_TX_P0 HSMA_TX_N0 HSMA_D0 HSMA_D2 D HSMA_TX_D_P0 HSMA_TX_D_N0 HSMA_TX_D_P1 HSMA_TX_D_N1 HSMA_TX_D_P2 HSMA_TX_D_N2 HSMA_TX_D_P3 HSMA_TX_D_N3 HSMA_TX_D_P4 HSMA_TX_D_N4 HSMA_TX_D_P5 HSMA_TX_D_N5 HSMA_TX_D_P6 HSMA_TX_D_N6 C HSMA_TX_D_P7 HSMA_TX_D_N7 HSMA_CLK_OUT_P1 HSMA_CLK_OUT_N1 HSMA_TX_D_P8 HSMA_TX_D_N8 HSMA_TX_D_P9 HSMA_TX_D_N9 HSMA_TX_D_P10 HSMA_TX_D_N10 HSMA_TX_D_P11 HSMA_TX_D_N11 B HSMA_TX_D_P12 HSMA_TX_D_N12 HSMA_TX_D_P13 HSMA_TX_D_N13 HSMA_TX_D_P14 HSMA_TX_D_N14 HSMA_TX_D_P15 HSMA_TX_D_N15 HSMA_TX_D_P16 HSMA_TX_D_N16 12V A HSMA_CLK_OUT_P2 HSMA_CLK_OUT_N2 3.3V C335 22uF 25V 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 3.3V C482 22uF 25V BANK 1 41 43 3.3V 47 49 3.3V 53 55 3.3V 59 61 3.3V 65 67 3.3V 71 73 3.3V 77 79 3.3V 83 85 3.3V 89 91 3.3V 95 97 3.3V 101 103 3.3V 107 109 3.3V 113 115 3.3V 119 121 3.3V 125 127 3.3V 131 133 3.3V 137 139 3.3V 143 145 3.3V 149 151 3.3V 155 157 3.3V ASP-122953-01 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 12V 48 50 12V 54 56 12V 60 62 12V 66 68 12V 72 74 12V 78 80 12V 84 86 12V 90 92 12V 96 98 12V BANK 2 A BANK 3 102 104 12V 108 110 12V 114 116 12V 120 122 12V 126 128 12V 132 134 12V 138 140 12V 144 146 12V 150 152 12V 156 158 PSNTn GND_1_1 GND_1_2 GND_1_3 GND_1_4 GND_2_1 GND_2_2 GND_2_3 GND_2_4 GND_3_1 GND_3_2 GND_3_3 GND_3_4 4 11,12,16 12 9 8 8 8 8 8 8 8 8 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 E HSMA_RX_P3 8 HSMA_RX_N3 8 HSMA_RX_P2 8 HSMA_RX_N2 8 HSMA_RX_P1 8 HSMA_RX_N1 8 HSMA_RX_P0 8 HSMA_RX_N0 8 HSMA_SCL 4 JTAG_HSMA_TMS 12 JTAG_HSMA_TDI 12 HSMA_CLK_IN0 9 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 HSMA_D1 HSMA_D3 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 HSMA_RX_D_P8 HSMA_RX_D_N8 HSMA_D[3:0] HSMA_TX_D_N[16:0] HSMA_RX_D_P[16:0] 6 5 7 7 D 7 HSMA_CLK_OUT_P[2:1] 4,7 HSMA_CLK_OUT_N[2:1] 4,7 HSMA_RX_D_P1 HSMA_RX_D_N1 HSMA_CLK_IN_P[2:1] HSMA_RX_D_P2 HSMA_RX_D_N2 4,9 HSMA_CLK_IN_N[2:1] 4,9 HSMA_RX_D_P3 HSMA_RX_D_N3 HSMA_PRSNTn 4,16,23 HSMA_RX_D_P4 HSMA_RX_D_N4 HSMA_RX_D_P5 HSMA_RX_D_N5 HSMA_RX_D_P6 HSMA_RX_D_N6 C HSMA_RX_D_P7 HSMA_RX_D_N7 HSMA_CLK_IN_P1 HSMA_CLK_IN_N1 HSMA_RX_D_P9 HSMA_RX_D_N9 HSMA_RX_D_P10 HSMA_RX_D_N10 HSMA_RX_D_P11 HSMA_RX_D_N11 B HSMA_RX_D_P12 HSMA_RX_D_N12 HSMA_RX_D_P13 HSMA_RX_D_N13 HSMA_RX_D_P14 HSMA_RX_D_N14 HSMA_RX_D_P15 HSMA_RX_D_N15 HSMA_RX_D_P16 HSMA_RX_D_N16 HSMA_CLK_IN_P2 HSMA_CLK_IN_N2 HSMA_PRSNTn 12V Title Size 4 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Date: 7 7 HSMA_RX_D_N[16:0] HSMA_RX_D_P0 HSMA_RX_D_N0 B 8 4 HSMA_TX_D_P[16:0] 161 162 163 164 165 166 167 168 169 170 171 172 E 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 17 of 1 40 C 8 7 6 5 4 3 2 10/100/1000 Ethernet - HPS ETHERNET INTERFACE U11A ENET_HPS_MDC 36 ENET_HPS_MDIO 37 E ENET_HPS_LED2_LINK ENET_HPS_RESETn 42 3.3V_REG_HPS J2 13 YK Yellow TD3_P CT3 TD3_N Orange D 15 17 OK GK Green 220 4 6 5 CT1 3 1 2 CT2 8 7 9 CT3 RX_DV_CLK125_EN 2 3 5 6 7 8 10 11 MDI_HPS_P0 MDI_HPS_N0 MDI_HPS_P1 MDI_HPS_N1 MDI_HPS_P2 MDI_HPS_N2 MDI_HPS_P3 MDI_HPS_N3 4.99K ENET_HPS_RSET 48 16 3.3V_REG_HPS TXRXP_A TXRXM_A TXRXP_B TXRXM_B TXRXP_C TXRXM_C TXRXP_D TXRXM_D 17 15 ENET_HPS_LED1_LINK ENET_HPS_LED2_LINK DNI 3 C49 ENET_HPS_LED1_LINK C48 C15 0.01uF CT1 DNI Y1 25.00MHz 2 35 ENET_HPS_RX_CLK 24 ENET_HPS_GTX_CLK 25 ENET_HPS_TX_EN 33 ENET_HPS_RX_DV 22 21 20 19 ENET_HPS_TXD3 ENET_HPS_TXD2 ENET_HPS_TXD1 ENET_HPS_TXD0 32 31 28 27 ENET_HPS_RXD0 ENET_HPS_RXD1 ENET_HPS_RXD2 ENET_HPS_RXD3 2.5V_REG_HPS U28 1 2 A0 3 A1 4 A2 GND ENET_HPS_TXD[3..0] 6 ENET_HPS_TXD[3..0] ENET_HPS_GTX_CLK6 ENET_HPS_TX_EN 6 ENET_HPS_MDC 6,18 ENET_HPS_RESETn 18,21 ENET_HPS_GTX_CLK ENET_HPS_TX_EN ENET_HPS_MDC ENET_HPS_RESETn ENET_HPS_RXD[3..0] 6 ENET_HPS_RXD[3..0] ENET_HPS_RX_CLK 6 ENET_HPS_RX_DV 6 ENET_HPS_MDIO 6,18 ENET_HPS_INTn 6,18 ENET_HPS_RX_CLK ENET_HPS_RX_DV ENET_HPS_MDIO ENET_HPS_INTn 2.5V_REG_HPS VCC WP SCL SDA 8 7 6 5 I2C_SCL_HPS 6,23,27 I2C_SDA_HPS 6,23,27 24LC32A 41 E D CLK125_NDO_LED_MODE LED1_PHYAD0 LED2_PHYAD1 3.3V_REG_HPS 46 45 1 4 CT0 RXD0_MODE0 RXD1_MODE1 RXD2_MODE2 RXD3_MODE3 CLK125_NDO_LED_MODE 220 0.01uF TXD3 TXD2 TXD1 TXD0 ISET R2 C16 GTX_CLK TX_EN ENET_L829-1J1T-43 C INT_N CT0 R50 GOA RX_CLK_PHYAD2 MDI INTERFACE TD2_P CT2 TD2_N GND_TAB GND_TAB R1 11 12 10 TD0_P CT0 TD0_N TD1_P CT1 TD1_N 18 19 38 ENET_HPS_INTn 14 YA MDC MDIO RESET_N 1 XI XO 3.3V_REG_HPS L1 KSZ9021RN C21 C27 10uF 10uF 3.3V_AVDDH 3A, 30 Ohm FB 3.3V_REG_HPS C26 22uF L24 1.2V_AVDLL_PLL C28 C23 2.2uF 0.1uF C43 22uF C58 C44 2.2uF 0.1uF L4 3.3V_DVDDH 1.2V_AVDDL C 1.2V_AVDLL_PLL C13 0.01uF U11B CT2 3.3V_AVDDH C14 0.01uF 47 12 1 CT3 3.3V_DVDDH 40 16 34 1.2V AVDLL_PLL 2.5V_REG_HPS 5.0V 49 13 29 U18 C52 4 10uF 6 B 2.5V_REG_HPS R46 BST OUT2 OUT1 SW SHDN 3 11 10.0K IN1 IN2 GND GND 1 2 ADJ PG 5 C47 1uF 1.2V_AVDLL_PLL 10 9 AVDDL_PLL LDO_O AVDDH AVDDH AVDDH AVDDL AVDDL DVDDH DVDDH DVDDH DVDDL DVDDL DVDDL DVDDL DVDDL DVDDL P_GND VSS_PS VSS 44 43 1.2V_AVDDL 3A, 30 Ohm FB C262 22uF C270 C261 2.2uF 0.1uF 3A, 30 Ohm FB C59 22uF 9 4 C60 C61 2.2uF 0.1uF L3 1.2V_DVDDL 18 14 39 30 26 23 1.2V_DVDDL 3A, 30 Ohm FB C56 22uF C57 C55 2.2uF 0.1uF KSZ9021RN 8 7 R56 R55 1.00K LTC3026 Place near KSZ9021RN PHY 2.00K B 3.3V C45 22uF C46 2.2uF R340 R339 R347 R364 R365 R368 R369 R378 R406 DNI DNI 4.70K, 1% 4.70K, 1% 4.70K, 1% 4.70K, 1% DNI 4.70K, 1% 4.70K, 1% ENET_HPS_LED2_LINK ENET_HPS_LED1_LINK ENET_HPS_RXD3 ENET_HPS_RXD2 ENET_HPS_RXD1 ENET_HPS_RXD0 ENET_HPS_RX_DV ENET_HPS_RX_CLK CLK125_NDO_LED_MODE R342 R341 R348 R366 R367 R370 R371 R379 R407 1.00k 1.00k DNI DNI DNI DNI 4.70K, 1% DNI DNI 3.3V_REG_HPS R47 R42 R48 R49 4.70K, 1% 4.70K, 1% 4.70K, 1% 4.70K, 1% ENET_HPS_MDIO 6,18 ENET_HPS_MDC 6,18 ENET_HPS_INTn6,18 ENET_HPS_RESETn 18,21 BOOT-STRAPS A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 18 of 1 40 C 8 7 6 5 4 3 2 1 10/100M Ethernet - FPGA 5 5 5 5 ENET2_RX_ERROR ENET2_RX_DV ENET2_RX_CLK ENET2_TX_CLK_FB 10 CLK_DUAL_ENET_PHY 3.3V C R502 R523 R238 0 DNI REG_FB R479 R512 4.70K, 1% DNI DNI 4,21 ENET_DUAL_RESETn P0TXERR_PHY P1TXERR_PHY 80 1 ENET_DUAL_RESETn P1TXP P1TXN P1RXP P1RXN XCLK0 XCLK1 DNI P0100BTLED P0ACTLED P0LINKED REGOFF RESETB P1100BTLED P1ACTLED P1LINKED 3.3V R504 R503 R540 P1RXD0 P1RXD1 P1RXD2 P1RXD3 P1RXERR P1RXDV P1RXCLK P1CRS P1COL 33 34 R237 R213 35 36 37 38 40 39 41 42 22 ENET2_RX_D0 ENET2_RX_D1 ENET2_RX_D2 ENET2_RX_D3 ENET2_RX_ERROR ENET2_RX_DV ENET2_RX_CLK DNI 4.70K, 1% 63 62 4.70K, 1% 4.70K, 1% MDIO MDC EXTRES REGAGND REGBGND1 REGBGND2 P0AGND P1AGND GNDIO GND15 VSSAPLL ENET_FPGA_MDIO ENET_FPGA_MDC 7 7 R528 R533 R515 79 13 2 4.70K, 1% 4.70K, 1% DNI DR ATP TEST TCT 3 17 18 ENET1_MDI_RX_P ENET1_MDI_RX_N C224 0.01uF 12pF 12pF 12pF 12pF RD- 8 13 14 C226 0.01uF R236 10 GND GND_TAB GND_TAB C230 0.01uF 7 6 ENET2_MDI_TX_P ENET2_MDI_TX_N 5 4 ENET2_MDI_RX_P ENET2_MDI_RX_N 64 68 69 ENET1_ACT_LED ENET1_LINK_LED P0TXERR 4,19 R526 DNI R276 ENET1_LINK_LED ENET2_ACT_LED R273 3.3V 61 65 67 ENET2_ACT_LED ENET2_LINK_LED 12 R527 J33 12.4K R226 10 R228 49.9 R227 49.9 R224 49.9 R223 49.9 R225 10 76 74 75 14 8 31 51 9 1 TD+ 2 TCT 3 RD+ 5 4.70K, 1% ENET2_RX_D0 4.70K, 1% ENET2_RX_D1 DNI ENET2_RX_CLK 4.70K, 1% ENET1_RX_ERROR DNI ENET2_RX_ERROR 4.70K, 1% ENET1_RX_CLK 4.70K, 1% ENET1_RX_DV 4.70K, 1% ENET2_RX_DV DNI ENET1_RX_D0 DNI ENET1_RX_D1 R509 R501 R478 R488 R495 R490 R486 R500 R482 R484 DNI DNI 4.70K, 1% DNI 4.70K, 1% DNI DNI DNI 4.70K, 1% 4.70K, 1% C220 C222 C221 C218 C217 0.01uF 12pF 12pF 12pF 12pF RCT R229 10 4,19 C112 4.7uF C110 C109 C108 C633 C632 C631 C630 C629 C628 C627 C626 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C614 22uF 25V P1TXERR C645 C644 C643 C642 C641 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF Title PLACE NEAR LEVEL TRANSLATORS B Date: 7 6 5 R525 DNI ENET2_LINK_LED R274 220 4 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 C615 22uF 25V Size 8 C223 0.01uF Green Place near uPD60620 PHY A C111 GND GND_TAB GND_TAB B 3.3V BOOT-STRAPS 1V5_ECAT2 RD- 8 13 14 C219 0.01uF Yellow TD- 4 3.3V Place near uPD60620 PHY C 3.3V B 3.3V 220 220 6 1.5V_REG_HPS D 3.3V uPD60620 R508 R499 R477 R487 R494 R489 R485 R498 R481 R483 Green GA GK ENET1_MDI_TX_P ENET1_MDI_TX_N C225 11 12 15 16 C228 9 10 RCT 6 ENET-7499011121A 5 C229 YA YK RD+ 1V5_ECAT2 C227 Yellow TD- 4 REG_FB 30 52 11 19 3 15 TD+ 2 0_Ohms GND_TAB1 1 ENET-7499011121A ENET2_RX_D0 ENET2_RX_D1 ENET2_RX_D2 ENET2_RX_D3 R232 10 9 10 ENET2_RX_D[3..0] 5 P0RXP P0RXN 78 R230 49.9 1 10uH L22 72 73 R231 49.9 YA YK 0 P0TXP P0TXN 2 R233 10 R218 R234 49.9 GA GK 5 4,19 D32 J34 R235 49.9 11 12 R514 ENET2_TX_EN P1TXERR P1TXD0 P1TXD1 P1TXD2 P1TXD3 P1TXERR P1TXEN P1TXCLK 32 50 66 40V GND_TAB2 D 23 24 25 26 27 28 29 ENET2_TX_D0 ENET2_TX_D1 ENET2_TX_D2 ENET2_TX_D3 P1TXERR_PHY ENET2_TX_EN ENET2_TX_CLK_FB VDD15_1 VDD15_2 VDDAPLL P0VDDMEDIA P1VDDMEDIA 1V5_ECAT E R217 16 ENET2_TX_D0 ENET2_TX_D1 ENET2_TX_D2 ENET2_TX_D3 REGFB DNI 15 ENET2_TX_D[3..0] 5 REGLX1 REGLX2 1.5V_REG_HPS GND_TAB1 ENET1_RX_ERROR ENET1_RX_DV ENET1_RX_CLK ENET1_TX_CLK_FB 5 5 5 5 P0RXD0 P0RXD1 P0RXD2 P0RXD3 P0RXERR P0RXDV P0RXCLK P0CRS P0COL 3.3V 3.3V GND_TAB2 53 ENET1_RX_D0 54 ENET1_RX_D1 55 ENET1_RX_D2 56 ENET1_RX_D3 58 ENET1_RX_ERROR 57 ENET1_RX_DV 59 ENET1_RX_CLK 60 R496 DNI R524 4.70K, 1% 21 ENET1_RX_D0 ENET1_RX_D1 ENET1_RX_D2 ENET1_RX_D3 VDDIO1 VDDIO2 VDDIO3 70 71 77 20 10 16 0 ENET1_RX_D[3..0] 5 REGBVDD1 REGBVDD2 REGAVDD VCC33ESD VDDACB 7 5 4,19 P0TXD0 P0TXD1 P0TXD2 P0TXD3 P0TXERR P0TXEN P0TXCLK NC R480 ENET1_TX_EN P0TXERR 43 44 45 46 47 48 49 ENET1_TX_D0 ENET1_TX_D1 ENET1_TX_D2 ENET1_TX_D3 P0TXERR_PHY ENET1_TX_EN ENET1_TX_CLK_FB 220 3.3V 7 E ENET1_ACT_LED R275 U45 ENET1_TX_D0 ENET1_TX_D1 ENET1_TX_D2 ENET1_TX_D3 NC ENET1_TX_D[3..0] 5 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 19 of 1 40 C 8 7 6 5 4 3 2 1 SDI Cable Driver, Equalizer, SMA Option and SMB E 75 Ohm Impedance 3.3V_SDI R91 750 L6 1 E 5.6nH 2 SDI_TXDRV_FILTER_P 75 R80 J14 C81 4.7uF 1 SDI_TXBNC_P 3.3V_SDI Mini SMB 3.3V_SDI D SDI_TX_P C80 8 SDI_TX_N 5 SDI_TX_SD_HDn 5 5,16 SDI_RSTI SDI_TX_EN 4.7uF C90 U25 4.7uF 1 2 SDI_TX_RSET 10 4 0 R95 R96 R79 10K 10K SDI SDI SDI_SDA SDI_SCL VCC NC5 NC6 R76 12 11 SDO SDO SDI_FAULT5 D R85 75 R75 10K 3 17 75 R81 L9 SDI Cable Driver, LMH0303SQx SDI_SCL SDI_SDA C86 4.7uF SDI_TXBNC_N 5.6nH 1 0 I2C_SCL I2C_SDA R86 2 SDI_TXDRV_FILTER_N 3.3V_SDI C85 R442 Right Angle CAD Note: Route traces at secondary side V1 3.3V_SDI VEE CENTERPAD 75 SDI_TXDRV_P SDI_TXDRV_N 16 13 RSTO FAULT RSTI ENABLE SDA SCL 14 15 49.9 9 SD/HD RREF 5 6 7 8 R92 R78 3.3V_SDI 49.9 R443 7,16,26 7,16,26 SDI_TXCAP_P SDI_TXCAP_N Cable Driver 2 3 4 5 8 75 0 3.3V 3.3V_SDI L5 0.01uF 120 ohm FB C119 C75 C76 C104 0.1uF 0.1uF 220nF 220nF C96 C 22uF C 75 Ohm Impedance L11 5.6nH 1 J17 1 2 SDI_IN_P1 SDI_IN_FILTER_P1 Mini SMB 75 R128 3.3V_SDI 5 4 3 2 Right Angle 75 R127 CAD Note: Route traces at secondary side B 1.0UF C120 CAD Note: Overlap C188 & R286 U31 R97 1.0UF 37.4 C103 2 3 SDI_EQIN_P1 SDI_EQIN_N1 7 15 4 12 SDI_RX_CDn 3.3V_SDI R94 3.3V_SDI 10K From EPM2210 5 6 AEC 5,16 SDI_RX_BYPASS 5,16 SDI_RX_EN 1.0UF C97 14 8 R126 Read-Only (Auto-Mute) R93 SDI SDI BYPASS CD SPI_EN AUTO_SLEEP VCC1 VCC2 SDO SDO MUTE MUTEref 11 10 VEE1 VEE2 DAP C117 SDO_P SDO_N AEC+ AEC- B 13 16 1 9 17 C116 4.7UF 4.7UF SDI_RX_P 8 SDI_RX_N 8 CAD Note: Overlap C189 & R284 SDI Cable Equalizer, LMH0384SQ 3.3V_SDI R98 A 75 0 D17 0 A Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia Green_LED Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet C 20 of 1 40 8 7 6 5 4 3 2 1 QSPI Flash & Reset Circuit RESET CIRUIT QSPI FLASH E E D D 3.3V 3.3V 3.3V 0.1uF C241 U5 U56 6 6 6 6 QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 15 8 9 1 6 QSPI_CLK 16 6 QSPI_SS0 7 C VCC DQ0 DQ1 DQ2/VPP/W# DQ3/HOLD# C S# DNU1 DNU2 DNU3 DNU4 DNU5 DNU6 DNU7 DNU8 VSS 2 4 R316 20.0K 3 4 5 6 11 12 13 14 3 S7 1 2 PB Switch VCC MR PB_COLD_RESETn GND RESET 1 2 MAX811 COLD_RESETn R315 100K R314 0 USB_RESET IS ACTIVE HIGH AND IS INVERTED THROUGH THE MAX II SYSTEM CONTROLLER 10 0 R319 RESET_HPS_UART_N 24 0 R320 ENET_HPS_RESETn 18 C N25Q00AA13GSF40F TP1 DNI R534 ENET_DUAL_RESETn4,19 HPS_RESETn 6,16 HPS_RESETn Input only to CV device cold reset 3.3V 3.3V B 0.1uF B C240 U55 3.3V 4 PLACE NEAR QSPI FLASH R313 20.0K 3 C259 C258 4.7uF S8 1 0.1uF 2 PB Switch PB_WARM_RESETn VCC MR GND RESET MAX811 1 2 WARM_RESETn R312 100K R311 0 Input/output to CV device warm reset MICTOR_RSTn A 6,12,16 MICTOR_RSTn A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 21 of 1 40 C 8 7 6 5 4 3 2 1 DanP Update: SMSC schematic review reference number is 834654-B1081. SMSC placement review reference number is 375404-B1082. USB 2.0 OTG , Micro SD Card 5.0V E C1 C2 2.2uF USB 2.0 OTG 1 3 9 2.2uF IN1 IN2 IN3 7 USB_EXTVBUS R6 3.3V E U1 C3 2.2uF USB_5.0V USB_5.0V OUT1 OUT2 OUT3 OUT4 FAULT 5 DNI 2 4 8 10 ON USB_VDD C8 C9 C243 C242 0.1uF 0.1uF 0.1uF 0.1uF 6 GND MAX1693H USB_VDDA 24 23 22 21 20 19 18 17 USB_CLK USB_NXT USB_DIR USB_STP 14 11 12 13 USB_RBIAS 32 USB_RESET_PHY R11 12.0K 9 16 6 6 6 6 6 29 15 26 CPEN EXTVBUS VBUS DM DP ID CLKOUT NXT DIR STP XO XI RBIAS GND GND GND_FLAG RESET 31 3 10 USB_CPEN USB_EXTVBUS 4 8 7 5 USB_VBUS USB_DM_N USB_DP_P USB_ID 27 28 USB_XO USB_XI C4 D J1 USB MINI-AB R5 X2 2 4 1 2 3 4 5 820,1% C20 1 2 33 4.7uF 30pF R17 1M 24MHz C USB_RESET R8 USB_RESET USB_CLK USB_NXT USB_DIR USB_STP USB_DATA[7..0] REG_EN USB3300 R9 10.0K C DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 6 7 USB_DATA0 USB_DATA1 USB_DATA2 USB_DATA3 USB_DATA4 USB_DATA5 USB_DATA6 USB_DATA7 3 R16 DNI 10.0K 10.0K 10.0K 10.0K 10.0K 10.0K 10.0K 10.0K USB_5.0V R15 100K 1 3.3V R21 R36 R35 R34 R23 R22 R20 R19 DanP: Should ESD protection diodes to be added? 3.3V 3.3V VDDA1.8 D VDD1.8 VDD1.8 U2 VDD3.3 VDD3.3 VDD3.3 VDD3.3 30 25 16 6 R10 DNI USB_RESET USB_CLK USB_NXT USB_DIR USB_STP USB_DATA[7..0] 0 C12 USB_RESET_PHY 30pF 3.3V USB INTERFACE Micro SD Card J3 B SD_CLK 5 SD_CMD 3 SD_DAT0 SD_DAT1 SD_DAT2 SD_CD_DAT3 7 8 1 2 CLK VDD CMD CAGE CAGE CAGE CAGE VSS DAT0 DAT1 DAT2 CD/DAT3 C10 C5 C6 2.2uF 0.1uF 0.1uF 4 9 10 11 12 6 B 1 K1 2 K2 1 K1 2 K2 1 K1 K2 2 MicroSD_skt 3.3V USB_VDD A C249 C252 4.7uF 0.1uF C256 0.1uF C255 0.1uF C245 0.1uF A 3 A ESD5V3U2U 3 ESD5V3U2U D12 USB_VDDA C254 C260 4.7uF ESD5V3U2U D10 3 D11 PLACE NEAR USB3300 A Micro SD / USB INTERFACE 0.1uF C251 C250 C248 4.7uF 0.1uF 6 6 6 6 6 SD_DAT2 SD_CD_DAT3 SD_DAT0 SD_DAT1 SD_CMD SD_CLK 6 SD_CLK Title 0.1uF B Date: 7 6 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Size 8 TP8 SD_DAT2 SD_CD_DAT3 SD_DAT0 SD_DAT1 SD_CMD 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 22 of 1 40 C 8 7 6 5 4 3 2 1 User I/O, RTC 3.3V B2 MAX_ERROR D34 49.9 R549 49.9 B4 Green_LED 2x16 LCD I2C I2C ADDRESS: 0x50 HEADER 3X1 HEADER 6X1 Green_LED R563 49.9 10K 10K D41 Green_LED PGM_LED0 D40 J15 R567 49.9 R568 49.9 Green_LED PGM_LED1 I2C_SCL_DISP I2C_SDA_DISP D39 Green_LED R569 PGM_LED2 49.9 D 1 2 3 4 5 6 7 8 9 10 8 1 2 I2C_SCL_DISP I2C_SDA_DISP 3.3V R435 0 U24 7 5.0V E 2.5V_REG_HPS 5.0V MAX_LOAD D38 MAX_CONF_DONE R555 R429 E B1 Red_LED R430 D36 VCC VL TRI_STATE VCCIO1 VCCIO2 GND VL_IO1 VL_IO2 3 6 R434 5 4 DNI I2C_SCL_HPS 6,18,27 I2C_SDA_HPS 6,18,27 MAX3373 D LCD_HEADER I2C ADDRESS: 0x40 3.3V I2C_SDA_HPS R12 I2C_SCL_HPS R37 S12 1 2 PGM_CONFIG PB Switch R564 2 PGM_SEL PB Switch R565 4.70K, 1% 2 MAX_RESETn PB Switch R337 4.70K, 1% 2 CPU_RESETn PB Switch R566 0 0 15 13 12 11 10 S9 1 D9 Green_LED HSMA_PRSNTn R309 16 1 4.70K, 1% S11 1 3 0.1uF VCC VBACKUP SDA SCL SQW/INT NC5 NC6 NC7 NC8 NC9 NC10 GND NC1 NC2 NC3 NC4 14 2 VBAT R38 4 5 6 7 8 9 BT1 DS1339C 49.9 C USER_LED_HPS[3..0] 6 S10 1 R557 3.3V 49.9 C D37 Green_LED CVP_CONF_DONE 4.70K, 1% 1 2.5V_REG_FPGA U3 C29 2 2.5V_REG_HPS 4.70K, 1% USER_LED_HPS[3..0] LED INTERFACE PGM_LED[2:0] 16 PGM_LED[2:0] 2.5V_REG_HPS USER_LED_FPGA[3:0] 4,9 S4 1 2 USER_PB_HPS0 PB Switch R298 4.70K, 1% 2 USER_PB_HPS1 PB Switch R299 4.70K, 1% 2 USER_PB_HPS2 PB Switch R300 4.70K, 1% 2 USER_PB_HPS3 PB Switch R301 4.70K, 1% MAX_ERROR MAX_LOAD MAX_CONF_DONE S3 1 3.3V D4 S2 1 Green_LED USER_LED_HPS0 R282 49.9 HSMA_RX_LED HSMA_TX_LED HSMA_PRSNTn S1 1 B D3 Green_LED R283 USER_LED_HPS1 49.9 S6 D2 1 Green_LED USER_LED_HPS2 R284 49.9 2 USER_PB_FPGA0 PB Switch R296 2 USER_PB_FPGA1 PB Switch R297 4.70K, 1% USER_PB_HPS[3:0] S5 1 D1 Green_LED R285 USER_LED_HPS3 4,16,17 PCIE_LED_X1 PCIE_LED_X4 USER_DIPSW_HPS[3:0] 5 1.5V_REG_FPGA 16 16 16 B DIPSW INTERFACE 5 USER_DIPSW_FPGA[3:0] 4 4.70K, 1% 49.9 PUSH BUTTON INTERFACE 2.5V_REG_FPGA D8 PGM_SEL PGM_CONFIG MAX_RESETn Green_LED R278 USER_LED_FPGA0 49.9 3.3V 16 16 16 USER_PB_FPGA[1:0] D7 Green_LED SW1 R279 USER_LED_FPGA1 16 15 14 13 12 11 10 9 49.9 A D6 USER_LED_FPGA2 D5 Green_LED R280 49.9 Green_LED R281 USER_LED_FPGA3 1 2 3 4 5 6 7 8 USER_DIPSW_HPS0 USER_DIPSW_HPS1 USER_DIPSW_HPS2 USER_DIPSW_HPS3 USER_DIPSW_FPGA0 USER_DIPSW_FPGA1 USER_DIPSW_FPGA2 USER_DIPSW_FPGA3 R288 R289 R290 R291 R292 R293 R294 R295 4.70K, 1% 4.70K, 1% 4.70K, 1% 4.70K, 1% 4.70K, 1% 4.70K, 1% 4.70K, 1% 4.70K, 1% CPU_RESETn 2.5V_REG_FPGA Title Size 49.9 B Date: 7 6 5 4 4 11,16 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 TDA08H0SB1 8 PGM_SEL PGM_CONFIG MAX_RESETn 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 23 of 1 40 C 8 7 6 5 4 3 2 1 UART, CAN UART E E U17 3.3V D CON2 18 RESET_HPS_UART_N 21 Green_LED Green_LED D14 220 D15 R350 220 3.3V_USB_UART R41 22 21 10 11 9 UART_TX_LED UART_RX_LED R349 10.0K PWR_EN 5V_USB_UART RESET_HPS_UART_N R51 10.0K NC1 NC2 NC3 NC4 NC5 NC6 CBUS0 CBUS1 CBUS2 CBUS3 CBUS4 26 20 17 4 24 33 R45 RESET OSCI OSCO VIO_USB_UART 0 R53 15 14 DNI J8 USB MINI-B 5V_USB_UART L2 742792780 DM_N DP_P R39 25 23 5 12 13 29 C32 C33 39pF 39pF 0 1 2 3 4 5 6 7 881545-2 USBDM USBDP 3.3V_USB_UART R52 D 27 28 U12 3.3V_USB_UART VIO_USB_UART 5V_USB_UART TP2 C42 C36 C51 C54 C37 C34 0.1uF 2.2uF 0.1uF 2.2uF 0.1uF 4.7uF TPD4S012DRYR 4 1 2 16 1 6 3 1 2 5 J9 3V3OUT VCCIO 19 VBUS ID D+ DGND NC XJ2 VCC TXD RXD RTS CTS DTR DSR DCD RI TEST GND3 GND2 GND1 AGND EPAD_GND 30 2 32 8 31 6 7 3 UART_RX UART_TX 6 6 FT232R 4.70K, 1% C C 3.3V CAN BUS 0.1uF J35 2.2uF 1 4 6 6 CAN_RS 3.3V R539 DNI 8 VCC VREF D R CANH CANL RS 5 7 6 Place near SN65HVD230 R550 120 CANH_P CANL_N 2 GND B 5 9 4 8 3 7 2 6 1 U50 3 CAN_0_TX CAN_0_RX CAN_VREF C666 CAN_VREF 61800925023 SN65HVD230 10 11 C668 B C667 R538 0 RS = VCC -> Standby Mode RS = GND -> High-Speed Mode RS = Resistor to GND -> Slope Control R272 DNI 0.1uF A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 24 of 1 40 C 8 7 6 5 4 3 2 On-Board USB Blaster II R531 FX2_SDA 0 USB_B2_DATA[7:0] 4 VBUS_5V FX2_D_N FX2_D_P R265 C216 0.1uF 1 7 6 100K R216 GND 2 FX2_RESETn VCC RESET MR 4 U47B U53 R277 GND D+ D- 1 2 3.3V U51 TPD2EUSB30 D1 D2 4.7nF G1 A5 B5 C5 E7 E8 C239 D E1 E2 4 Y5 3 2 1 G2 C1 C2 USB_B2_CLK 24M_XTALIN 24M_XTALOUT 24.00MHz C233 C234 12pF 12pF G8 G6 F8 F7 F6 C8 C7 C6 FX2_PA1 FX2_PA2 FX2_PA3 FX2_PA4 FX2_PA5 FX2_PA6 FX2_PA7 C H2 F1 F2 H1 A4 B4 C4 D7 D8 3.3V AVCC AVCC RESET SCL SDA VCC VCC VCC VCC VCC VCC WAKEUP CTL0 CTL1 CTL2 DMINUS DPLUS RDY0 RDY1 IFCLK XTALIN XTALOUT CLKOUT PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 RESERVED PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 AGND AGND GND GND GND GND GND GND B8 F3 G3 FX2_RESETn FX2_SCL R553 FX2_SDA R551 B7 FX2_WAKEUP H7 G7 H8 FX2_FLAGA FX2_FLAGB FX2_FLAGC A1 B1 FX2_SLRDn FX2_SLWRn 2.00K 2.00K 10.0K H3 F4 H4 G4 H5 G5 F5 H6 FX2_PB0 FX2_PB1 FX2_PB2 FX2_PB3 FX2_PB4 FX2_PB5 FX2_PB6 FX2_PB7 A8 A7 B6 A6 B3 A3 C3 A2 FX2_PD0 FX2_PD1 FX2_PD2 FX2_PD3 FX2_PD4 FX2_PD5 FX2_PD6 FX2_PD7 MAX_SDA C_USB_MAX_TDI C_USB_MAX_TCK C_USB_MAX_TMS C_USB_MAX_TDO 20.0K 0.1uF FX2_PB1 FX2_PB3 FX2_SCL FX2_PD6 FX2_PD4 J7 H2 H3 J1 J2 IO1/DEV_OE FX2_SLWRn FX2_SLRDn FX2_PD7 FX2_PD5 FX2_PA5 C_JTAG_TDO C_JTAG_TMS C_JTAG_TDI C_JTAG_TCK TDI TCK TMS TDO IO1/GCLK0p IO1/GCLK1p IO2/GCLK2p IO2/GCLK3p K9 USB_FULL USB_EMPTY USB_SCL USB_SDA USB_B2_CLK USB_RESETn USB_OEn USB_RDn USB_WRn E M570_PCIE_JTAG_EN MAX V USB INTERFACE USB_CFG[11:0] EXTRA_SIG[2:0] 16 USB_CFG[11:0] 16 EXTRA_SIG[2:0] D USB_DISABLEn 12 M570_CLOCK 16 FACTORY_STATUS 16 FACTORY_REQUEST16 R560 R558 R537 R559 C_USB_MAX_TCK C_USB_MAX_TDI C_USB_MAX_TDO C_USB_MAX_TMS IO1/DEV_CLRn 4 4 4 4 4,16 4 4 4 4 M570_PCIE_JTAG_EN 16 0 0 0 0 USB_DISABLEn M570_CLOCK FACTORY_STATUS FACTORY_REQUEST FX2_PD0 FX2_PD2 FX2_PD3 FX2_PD1 FX2_RESETn JTAG INTERFACE E2 USB_B2_CLK E1 FX2_PB7 F8 USB_CFG7 E10 M570_CLOCK JTAG_TCK JTAG_TMS JTAG_BLASTER_TDI JTAG_BLASTER_TDO EPM570GF100 12 12 12 12 JTAG_TCK JTAG_TMS JTAG_BLASTER_TDI JTAG_BLASTER_TDO C U47C A1 JTAG_TX A2 JTAG_RX FACTORY_REQUEST A3 A4 USB_CFG5 A7 USB_RESETn B8 USB_OEn D10 USB_RDn D9 USB_WRn A9 FACTORY_STATUS A10 SC_RX B2 SC_TX B3 USB_CFG4 B4 EXTRA_SIG1 B5 USB_CFG6 B9 USB_B2_DATA0 C9 USB_B2_DATA1 C8 USB_B2_DATA2 B7 USB_B2_DATA3 C7 USB_B2_DATA4 PLACE NEAR CY7C68013A C681 H8 J3 J4 J5 J6 J8 J9 K1 K2 K3 K4 K5 K6 K7 K8 K10 MAX II CONFIGURATION FX2_WAKEUP R562 IO_B1_H8 IO_B1_J3 IO_B1_J4 IO_B1_J5 IO_B1_J6 IO_B1_J8 IO_B1_J9 IO_B1_K1 IO_B1_K2 IO_B1_K3 IO_B1_K4 IO_B1_K5 IO_B1_K6 IO_B1_K7 IO_B1_K8 IO_B1_K10 U47D B2 3.3V B IO_B1_B1 IO_B1_C1 IO_B1_C2 IO_B1_D1 IO_B1_D2 IO_B1_D3 IO_B1_E3 IO_B1_F1 IO_B1_F2 IO_B1_F3 IO_B1_G1 IO_B1_G2 IO_B1_G3 IO_B1_H1 IO_B1_H4 IO_B1_H7 EPM570GF100 CY7C68013A_VFBGA VBUS_5V R561 B1 C1 C2 D1 D2 D3 E3 F1 F2 F3 G1 G2 G3 H1 H4 H7 FX2_PA2 FX2_FLAGC FX2_PA7 FX2_FLAGA FX2_PA3 FX2_PA4 EXTRA_SIG0 FX2_PB4 FX2_PA6 FX2_PB2 FX2_FLAGB FX2_PB0 FX2_PA1 FX2_PB5 USB_DISABLEn FX2_PB6 MAX811 3 MAX II BANK 1 3 USB_ADDR[1:0] USB_FULL USB_EMPTY USB_SCL USB_SDA USB_B2_CLK USB_RESETn USB_OEn USB_RDn USB_WRn U48 DNI USB_B2_DATA[7:0] USB_ADDR[1:0] 3.3V E 1M FPGA USB INTERFACE MAX_SDA J37 USB MINI-B 1 2 3 4 5 1 C677 C675 C672 C682 C669 C671 C676 C680 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF MAX II BANK 2 IO_B2_A1 IO_B2_A2 IO_B2_A3 IO_B2_A4 IO_B2_A7 IO_B2_B8 IO_B2_D10 IO_B2_D9 IO_B2_A9 IO_B2_A10 IO_B2_B2 IO_B2_B3 IO_B2_B4 IO_B2_B5 IO_B2_B9 IO_B2_C9 IO_B2_C8 IO_B2_B7 IO_B2_C7 1V8 U47A IO_B2_C3 IO_B2_C4 IO_B2_A6 IO_B2_F10 IO_B2_F9 IO_B2_B10 IO_B2_E8 IO_B2_C10 IO_B2_D8 IO_B2_B6 IO_B2_E9 IO_B2_A8 IO_B2_A5 IO_B2_G8 IO_B2_G9 IO_B2_G10 IO_B2_H9 IO_B2_H10 IO_B2_J10 C3 USB_CFG3 C4 M570_PCIE_JTAG_EN A6 USB_B2_DATA7 F10 USB_B2_DATA5 F9 USB_B2_DATA6 B10 RST E8 USB_CFG8 C10 TRST D8 USB_FULL B6 USB_EMPTY E9 USB_CFG11 A8 USB_SCL A5 USB_SDA G8 EXTRA_SIG2 G9 USB_CFG10 G10 USB_CFG0 V39 H9 V43 USB_CFG1 H10 USB_CFG2 V42 J10 USB_CFG9 MAX II POWER C5 E6 F5 H5 D5 D7 E5 F6 G5 G7 GNDINT GNDINT GNDINT GNDINT VCCINT VCCINT VCCINT VCCINT GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 C6 E7 F4 H6 3.3V E4 G4 G6 1.5V_REG_HPS D4 D6 F7 EPM570GF100 B EPM570GF100 1V8 1.5V_REG_HPS D30 JTAG_RX RESn_JTAG_RX R518 56.2 Green_LED D31 JTAG_TX RESn_JTAG_TX R517 56.2 Green_LED D29 SC_RX RESn_SC_RX R519 TRST RST 56.2 R544 R542 R545 R543 1.00k 1.00k 1.00k 1.00k USB_SCL USB_SDA USB_FULL USB_EMPTY R541 1.00k FACTORY_REQUEST 3.3V J38 SC_TX RESn_SC_TX R520 56.2 R529 R530 R535 R536 JTAG_TCK JTAG_TMS JTAG_BLASTER_TDI JTAG_BLASTER_TDO DNI JTAG_BLASTER_TDI R321 Green_LED 1.00K C_USB_MAX_TCK 1 C_USB_MAX_TDO 3 1.00K C_USB_MAX_TMS 5 7 C_USB_MAX_TDI 9 1 3 5 7 9 2 4 6 8 10 R211 C648 C653 C655 C654 C661 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF Title Size Date: 6 5 4 3 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 B 7 C647 2.5V_REG_HPS 2 4 6 8 10 DNI 8 1V8 3.3V R286 Green_LED D28 A 0 0 0 0 C_JTAG_TCK C_JTAG_TMS C_JTAG_TDI C_JTAG_TDO PLACE NEAR MAX II (U14) 3.3V 1.5V_REG_HPS 16 16 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 25 of 1 40 C 5 4 V48 1 1.1V_VCC_N RSNS SNS 1.1V_VCC 1 RSNS SNS 1 D RSNS SNS 1.1V_REG_VCC 1 RSNS SNS 1 RSNS SNS 1 RSNS SNS TSENSE_FAN_CNTL 2 D 22_23_2021 Q1 1.5V_REG_FPGA 2 B3 OVERTEMP 16 FDV305N 2.5V_FPGA 2 SENSE_PAD V40 2.5V_FPGA_P 1 2 1.5V_FPGA SENSE_PAD V41 2.5V_FPGA_N 12V J21 SENSE_PAD V44 1.5V_FPGA_P 1 2 SENSE_PAD V45 1.5V_FPGA_N 2 FPGA Power Monitor 2 SENSE_PAD V49 1.1V_VCC_P 3 FAN_2pin_Conn 2.5V_REG_FPGA 2 SENSE_PAD 3.3V_PM_FPGA R417 R416 10K 10K SCL_PM SDA_PM SCL_PM SDA_PM 0 0 12V C R88 R87 1K 1K C92 0.1uF C93 0.1uF R83 R82 1K 1K C87 0.1uF C88 0.1uF I2C_SCL 7,16,20 I2C_SDA 7,16,20 R422 R421 C U26 14 R77 R73 1K 1K C77 0.1uF C82 0.1uF R70 R69 1K 1K C72 0.1uF C73 0.1uF R68 R67 1K 1K C70 R66 R65 1K 1K C68 0.1uF C71 0.1uF 0.1uF C69 0.1uF 36 37 42 43 46 47 48 49 52 53 62 63 64 1 2 3 2.5V_FPGA_V_P 2.5V_FPGA_V_N 2.5V_FPGA_I_P 2.5V_FPGA_I_N 1.5V_FPGA_V_P 1.5V_FPGA_V_N 1.5V_FPGA_I_P 1.5V_FPGA_I_N 1.1V_VCC_V_P 1.1V_VCC_V_N 1.1V_VCC_I_P 1.1V_VCC_I_N B SCL_PM SDA_PM PM2_ASEL0 PM2_ASEL1 PM_CNTL0 PM_CNTL1 PM_RSTn 28 27 32 33 30 31 22 PM2_FAULTB00 PM2_FAULTB01 PM2_FAULTB10 PM2_FAULTB11 23 24 25 26 PM_SHARE_CLK 21 19 65 3.3V_PM_FPGA VIN_SNS VSENSEP0 VSENSEM0 VSENSEP1 VSENSEM1 VSENSEP2 VSENSEM2 VSENSEP3 VSENSEM3 VSENSEP4 VSENSEM4 VSENSEP5 VSENSEM5 VSENSEP6 VSENSEM6 VSENSEP7 VSENSEM7 R104 10K R108 10K VDACP0 VDACM0 VDACP1 VDACM1 VDACP2 VDACM2 VDACP3 VDACM3 VDACP4 VDACM4 VDACP5 VDACM5 VDACP6 VDACM6 VDACP7 VDACM7 VOUT_EN0 VOUT_EN1 VOUT_EN2 VOUT_EN3 VOUT_EN4 VOUT_EN5 VOUT_EN6 VOUT_EN7 FAULTB00 FAULTB01 FAULTB10 FAULTB11 SHARE_CLK ALERTB PWRGD VPWR VDD25 WP E-PAD VDD33_OUT VDD33_IN LTC2978 Address Select PWRMON2 = 7'h5D A PM2_ASEL0 PM2_FAULTB00 PM2_FAULTB01 PM2_FAULTB10 PM2_FAULTB11 5 REFP REFM NC SCL SDA ASEL0 ASEL1 CONTROL0 CONTROL1 WDI/RESET GND pad R107 R106 R105 10K 10K 10K VIN_EN LTC2978 12 2.5V_FPGA_VDACP0 31 1.5V_FPGA_VDACP2 30 1.1V_FPGA_VDACP4 29 C481 0.1uf 34 35 13 2.5V_FPGA_VDACP0 1.5V_FPGA_VDACP2 1.1V_FPGA_VDACP4 39 38 40 41 44 45 50 51 55 54 56 57 59 58 60 61 2.5V_FPGA_VDACP0 SCL_PM SDA_PM 27 27 1.5V_FPGA_VDACP2 PM_SHARE_CLK PM_CNTL0 PM_CNTL1 PM_RSTn 27 27 27 PM_CNTL0 PM_CNTL1 PM_RSTn PM_ALERTB PM_PWRGD 27 27 PM_ALERTB PM_PWRGD 4 5 6 7 8 9 10 11 2.5V_FPGA_RUN 31 1.5V_FPGA_RUN 30 1.5V_FPGA_RUN 1.1V_FPGA_RUN 29 1.1V_FPGA_RUN 29 20 15 18 1.1V_FPGA_VDACP4 SCL_PM SDA_PM PM_SHARE_CLK 27 B PM2_FAULTB00 PM2_FAULTB01 PM2_FAULTB10 PM2_FAULTB11 PM2_FAULTB00 PM2_FAULTB01 PM2_FAULTB10 PM2_FAULTB11 2.5V_FPGA_RUN PM_ALERTB PM_PWRGD 3.3V_PM_FPGA 16 17 C91 C98 C99 0.1uf 0.1uf 0.1uf A Altera Corporation, 101 Innovation Drive, San Jose, CA PM2_ASEL0 PM2_ASEL1 Title Cyclone V SoC FPGA Development Kit Board 4 3 2 Size B Document Number 150-0321003-C1 Date: Wednesday, March 20, 2013 Rev C (6XX-44184R) Sheet 1 26 of 40 5 4 V3 1 3.3V_HPS_N RSNS SNS 1 RSNS SNS 1 2.5V_HPS_N RSNS SNS 3.3V_REG_HPS 2.5V_HPS 1 RSNS SNS 2.5V_REG_HPS 1 RSNS SNS 1 RSNS SNS 1 RSNS SNS 1 RSNS SNS 2 4 6 8 10 12 2 4 6 8 10 12 D SDA_PM SCL_PM PM_ALERTB 1.5V_REG_HPS 2 3.3V_PM_HPS 1.1V_HPS 2 SENSE_PAD V14 1.1V_HPS_P 1 3 5 7 9 11 2x6HDR 1.5V_HPS SENSE_PAD V13 1.1V_HPS_N J24 1 3 5 7 9 11 2 SENSE_PAD V6 1.5V_HPS_P PM_CNTL1 2 SENSE_PAD V7 1.5V_HPS_N I2C Interface 2 SENSE_PAD V22 2.5V_HPS_P 1 2 SENSE_PAD V21 D 2 HPS Power Monitor 3.3V_HPS 2 SENSE_PAD V2 3.3V_HPS_P 3 1.1V_REG_HPS R170 R171 R165 R162 10K 10K 10K 10K 2 R163 R164 R166 R167 R168 R169 R172 R173 10K 10K 10K 10K 10K 10K 10K 10K SENSE_PAD C C 12V B R155 R154 1K 1K C158 0.1uF C159 0.1uF R150 R149 1K 1K C143 0.1uF C144 0.1uF 1K 1K C132 0.1uF C138 0.1uF R119 R118 1K 1K C127 0.1uF C128 0.1uF R117 R116 1K 1K C125 0.1uF C126 0.1uF R115 R114 1K 1K C123 0.1uF C124 0.1uF R113 R112 R139 R140 1K 1K 1K 1K U34 14 R141 R131 SDA_PM SCL_PM PM_RSTn PM_PWRGD 1.1V_HPS_V_P 1.1V_HPS_V_N 1.1V_HPS_I_P 1.1V_HPS_I_N 3.3V_HPS_V_P 3.3V_HPS_V_N 3.3V_HPS_I_P 3.3V_HPS_I_N 1.5V_HPS_V_P 1.5V_HPS_V_N 1.5V_HPS_I_P 1.5V_HPS_I_N 2.5V_HPS_V_P 2.5V_HPS_V_N 2.5V_HPS_I_P 2.5V_HPS_I_N C121 0.1uF C122 0.1uF SCL_PM SDA_PM PM1_ASEL0 PM1_ASEL1 PM_CNTL0 PM_CNTL1 PM_RSTn C137 0.1uF C136 0.1uF these GND connections to each VSENSEMx pin needs to be placed close to a GND pin of the BGA! 36 37 42 43 46 47 48 49 52 53 62 63 64 1 2 3 28 27 32 33 30 31 22 PM1_FAULTB00 PM1_FAULTB01 PM1_FAULTB10 PM1_FAULTB11 23 24 25 26 PM_SHARE_CLK 21 19 65 VIN_SNS VIN_EN LTC2978 VSENSEP0 VSENSEM0 VSENSEP1 VSENSEM1 VSENSEP2 VSENSEM2 VSENSEP3 VSENSEM3 VSENSEP4 VSENSEM4 VSENSEP5 VSENSEM5 VSENSEP6 VSENSEM6 VSENSEP7 VSENSEM7 REFP REFM NC VDACP0 VDACM0 VDACP1 VDACM1 VDACP2 VDACM2 VDACP3 VDACM3 VDACP4 VDACM4 VDACP5 VDACM5 VDACP6 VDACM6 VDACP7 VDACM7 SCL SDA ASEL0 ASEL1 CONTROL0 CONTROL1 WDI/RESET VOUT_EN0 VOUT_EN1 VOUT_EN2 VOUT_EN3 VOUT_EN4 VOUT_EN5 VOUT_EN6 VOUT_EN7 FAULTB00 FAULTB01 FAULTB10 FAULTB11 SHARE_CLK ALERTB PWRGD VPWR VDD25 WP E-PAD GND pad VDD33_OUT VDD33_IN A 12 C580 0.1uf 34 35 13 39 38 40 41 44 45 50 51 55 54 56 57 59 58 60 61 1.1V_HPS_VDACP0 4 5 6 7 8 9 10 11 EN_1.1V_HPS 29 20 15 18 PM_ALERTB PM_PWRGD PM_SHARE_CLK PM_ALERTB PM1_FAULTB00 PM1_FAULTB01 PM1_FAULTB10 PM1_FAULTB11 PM_CNTL0 PM_CNTL1 1.5V_HPS_VDACP2 2.5_HPS_VDACP4 3.3_HPS_VDACP6 PM_SHARE_CLK PM_CNTL0 PM_CNTL1 PM_RSTn 26 26 26 26 PM_SHARE_CLK PM_CNTL0 PM_CNTL1 PM_RSTn PM_ALERTB PM_PWRGD 26 26 PM_ALERTB PM_PWRGD PM1_FAULTB00 PM1_FAULTB01 PM1_FAULTB10 PM1_FAULTB11 PM1_FAULTB00 PM1_FAULTB01 PM1_FAULTB10 PM1_FAULTB11 EN_1.5V_HPS B EN_2.5V_HPS EN_3.3V_HPS 3.3V_PM_HPS 16 17 EN_1.1V_HPS EN_1.5V_HPS EN_2.5V_HPS EN_3.3V_HPS 35 33 32 34 EN_1.1V_HPS EN_1.5V_HPS EN_2.5V_HPS EN_3.3V_HPS 1.1V_HPS_VDACP0 1.5V_HPS_VDACP2 2.5_HPS_VDACP4 3.3_HPS_VDACP6 35 33 32 34 1.1V_HPS_VDACP0 1.5V_HPS_VDACP2 2.5_HPS_VDACP4 3.3_HPS_VDACP6 A C156 C157 C167 SCL_PM 26 SCL_PM R474 0 SDA_PM 26 SDA_PM R475 0 I2C_SCL_HPS 6,18,23 LTC2978 Address Select PWRMON1 = 7'h5C 0.1uf 0.1uf 0.1uf Altera Corporation, 101 Innovation Drive, San Jose, CA Title Cyclone V SoC FPGA Development Kit Board PM1_ASEL0 PM1_ASEL1 I2C_SDA_HPS 6,18,23 5 4 3 2 Size B Document Number 150-0321003-C1 Date: Wednesday, March 20, 2013 Rev C (6XX-44184R) Sheet 1 27 of 40 8 7 6 5 4 3 2 1 Power 1 - DC Input & 12V, 3.3V Output DC_INPUT U44 FDMC8878 J22 CONN JACK PWR 2 1 3 E 1 2 3 5 19V DC Input E 4 DC_IN U60 5 GATE IN 1 6 4 7 OUT VDD GND EP_GND NC LTC4357 D27 C175 C196 47uF 35V 47uF 35V C176 22uF 25V C197 22uF 25V DC_IN INTVCC_1 U41 FDMC8878 D24 CMDSH-3 U43 RJK0305DPB 5 3 2 C166 22uF 25V Q3 drain-tab C187 BOOST1 4.7uF 38 37 14 2 1 3.3V_SHDNn 4 J20 1 2 COM COM +12V +12V 3 U59 3 2 4 5 ATX-POWER_4P GATE IN NC OUT VDD GND EP_GND 1 6 4 7 R178 20.0K 13 36 15 6 7 12V_SHDNn LTC4357 SW1 RUN1 ITEMP1 ILIM1 ITH1 TK/SS1 BG1 VFB1 RUN2 ITEMP2 ILIM2 ITH2 TK/SS2 SENSE1+ SENSE1PGOOD1 30 4 L14 C181 0.1uF 29 31 Q2 RJK0301DPB 4 27 2 3.3V 3 1.5uH V9 drain-tab 2 1 SNS RSNS SENSE_PAD 39 40 R177 3.09K R470 4.02K LTC3855_S1P LTC3855_S1N C174 16 V8 C540 C564 100uF 6.3v 0.1uF R205 DIFFOUT 11.5K TG2 BOOST2 SW2 gnd-pad 82pF 4 C180 22pF R198 57.6K BG2 VFB2 4 21 drain-tab C195 0.1uF 5 B GATE IN 1 6 4 7 OUT VDD GND EP_GND NC 22pF L23 2 19 RJK0301DPB 4 5 VFB2 1 V46 drain-tab 23 2 SNS RSNS SENSE_PAD R192 52.3K 3.3V DIFFOUT 12 10 11 SENSE2+ SENSE2- DIFFOUT DIFFP DIFFN PGOOD2 8 9 LTC3855_S2P LTC3855_S2N 12V_REG 0.68uH Q5 U62 3 2 RJK0305DPB 4 R199 C193 3.92K DNI R200 17 PG_12V 0.1uF 1 R256 V47 215.0K 2 C192 100pF SGND1 SGND2 PGND1 PGND2 NC 20 RSNS SNS C185 Q6 C R193 2.55K C210 22uF 25V 1 C186 Q4 drain-tab 4 41 28 22 18 5 RJK0305DPB 5 R180 169.0K R179 20.0K 5 1000pF DC_IN 1 2 3 1 2 3 12V_ATX 1000pF CMDSH-3 D26 1 2 3 Q7 FDMC8878 C194 5 12V C179 FREQ MODE/PLLIN PHSASMD CLKOUT 1 2 3 C 330uF 10V SENSE_PAD INTVCC_1 35 34 33 32 D 1 2 5 TG1 RSNS SNS INTVCC_1 VIN INTVCC EXTVCC 1 12V_ATX 26 25 24 1 2 3 1 2 3 5 D 1 2 3 MMBD1205 C664 C665 C663 68uF 25V 68uF 25V 68uF 25V VFB2 R257 11.3K SENSE_PAD B LTC4357 Q8 FDMC8878 1 2 3 12V_REG LTC3855EUJ R206 100K 5 3.3V 5.0V 4 U63 3 2 5 A GATE IN NC OUT VDD GND EP_GND R548 1.00k 1 6 4 7 POWER LED LTC4357 D35 BLUE LED SW5 SW SLIDE-4P2T DC_IN DC_IN 100K R268 12V_SHDNn R267 20.0K 12V_ATX R261 100K 7 1 8 9 2 3 3.3V_SHDNn 10 4 12V_ATX 11 12 5 6 R270 100K R269 20.0K R264 Title 100K Size B Date: 8 7 6 5 4 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 28 of 1 40 C 8 7 6 5 4 3 2 1 Power 2 E E 12V SNS_P 1.1V_VCC L10 14 C182 SNS_M R195 10 1.0nF15 12V C 59 16 17 19 28 29 PVIN7 PVIN8 PVIN9 PVIN10 PVIN11 PVIN12 PVIN13 PVIN14 SGND2 SGND3 SGND4 SGND5 SGND6 SGND7 SW1 SW2 SNSPGND1 1.1V_REG_VCC SW2 58 18 20 SW3 SW4 SW5 SW6 SW7 SW8 SW9 NC PGND2 PGND3 PGND4 PGND5 PGND6 PGND7 PGND8 PGND9 51 50 49 48 47 46 45 52 R182 13.7K 1% SW 1.1V_FPGA_VDACP4 26 215.0K R181 16.5K 1% REF R183 21 22 44 43 42 41 40 39 38 37 47pF 0.01uF INTVCC 10 35 0.1uF L12 CMDSH-3 0.47uH 1 SW 2 23 21K (1%) 24 25 R160 R159 0 36 R142 0 3A, 30 Ohm FB RSNS SNS SENSE_PAD 1.1V_VCC SENSE_PAD 1.1V_REG_VCC R132 R461 0.0015 VOUT Isat = 20A INTVCC1 INTVCC2 VOSNS+ TRACK/SS SVIN1 34 744314047 Wurth Elektronik C139 100UF 6.3V C133 100UF 6.3V 0.001 D C118 330uF 6.3V C145 4.7uF 33 INTVCC 12V 1 C198 22uF 25V 1210 C146 32 0.1uF C171 R174 270pF C172 DNI VOSNS- PVIN1 TRACK C170 INTVCC V5 VOUT ITH MODE/PLLIN VRNG RT R158 115K (1%) EXTVCC NC SGND 2 3 4 5 6 7 8 9 SNS+ 12 U39B BOOST BOOST 1 SNS_P R194 PGOOD 11 C183 10 D PVIN2 PVIN3 PVIN4 PVIN5 PVIN6 D25 U39A 13 V4 RSNS SNS R187 100K CAD Note: Regulator input caps Place near regulator controller 57 56 55 54 53 2 INTVCC 1 C199 22uF 25V 1210 2 SNS_M C189 22uF 25V 1210 1.1V_VCCEL RUN 31 MODE 30 27 10.0K C160 DNI R151 DNI INTVCC C188 22uF 25V 1210 C35 C213 47uF 35V 47uF 35V C R152 26 1.1V_FPGA_RUN 26 LTC3613EWKH_6 FSW = 350kHz LTC3613EWKH_6 B B A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 29 of 1 40 C 8 7 6 5 4 3 2 1 Power 3 - 1.5V FPGA D22 E E LTC3605_INTVCC C595 1.0UF C610 2.2uF CMDSH-3 LTC3605_BOOST Design Note: Added extra 1uF at INTVCC due to sourcing Vbias pin of LTC3025-1 12V 5 LTC3605_INTVCC R196 DNI 1200pF R197 24.0K 1% C200 C612 LTC3605_ITH 6 19 SVIN 20 BOOST 21 INTVCC 22 SGND 23 TRACK/SS SW EXPOSED PAD ITH SW 33pF C609 0.1UF 50V 18 16 C173 22uF 25V 1210 CAD Note: Regulator input caps Place near regulator controller D 17 Design Note: Prefer 0603 size cap 25V rated voltage is sufficient LTC3605_SW 15 R214 1.2uH Isat = 11A 14 13 C201 R204 39pF 15K 1% LTC3605_FB C205 C623 C622 C624 22uF 22uF 22uF 22uF R506 1.5V_FPGA 0.003 Cad Note: Place output caps near inductor 1.5V_FPGA_VDACP2 26 215.0K 25 12 11 10 9 C U42 LTC3605EUF R203 10.0K LTC3605_RUN 1.5V_FPGA_RUN 26 1.5V_REG_FPGA L19 PGND LTC3605_SS 3300pF SW SW C611 FB SW 4 SW 8 C LTC3605_FB MODE RUN CAD Note: Overlap R289 & R290 pads at 1 of the pins Place resistor & cap near pin 6 Design Note: tss = Css x 0.6V/2uA Ramp rate ~990us PVIN 7 Design Note: Ith is tied to INTVCC for internal compensation 3 PHMODE PGND 169.0K R184 PVIN VON 2 C190 22uF 25V 1210 C593 0.1uF 25V RT PGOOD D CLKOUT 24 CLKIN 1 LTC3605_RT 10 R185 LTC3605_SVIN 1.5V_FPGA_RUN 3.3V logic signal R507 0 3.3V Design Note: DNI for ES device R505 100K PGOOD_1.5V Cad Note: 1 overlapping pad B B A A Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet C 30 of 1 40 8 7 6 5 4 3 2 1 Power 3 - 2.5V FPGA E E Cad Note: Place near INTVCC pin D33 LTC3605_INTVCC C660 D 1.0UF CMDSH-3 D LTC3605_BOOST Design Note: Added extra 1uF at INTVCC due to sourcing Vbias pin of LTC3025-1 C659 12V 2.2uF R207 LTC3605_SVIN 10 2.5V_FPGA_FILT R221 47.5K 1% C212 560pF C657 LTC3605_ITH 6 19 SVIN 20 BOOST 21 INTVCC 22 SGND 23 EXPOSED PAD ITH SW 10pF C652 0.1UF 50V 18 17 16 C203 22uF 25V 1210 LTC3605_SW 2.5V_FPGA_RUN 26 R532 0 3A, 30 Ohm FB Design Note: DCR = 40m ohms 2.5V_REG_FPGA Design Note: Prefer 0603 size cap 25V rated voltage is sufficient 2.5V_FPGA R208 C 0.001 L20 15 1.2uH Isat = 11A 14 13 C208 R215 39pF 15K 1% LTC3605_FB C639 C651 C209 C621 22uF 22uF 22uF 22uF R521 215.0K Cad Note: Place output caps near inductor 2.5V_FPGA_VDACP0 26 U46 LTC3605EUF B 2.5V_FPGA_RUN L21 CAD Note: Regulator input caps Place near regulator controller PGND DNI SW 25 LTC3605_INTVCC R220 TRACK/SS SW 5 12 LTC3605_SS 3300pF SW SW C658 FB 11 4 PGND LTC3605_FB SW RUN CAD Note: Overlap R289 & R290 pads at 1 of the pins Place resistor & cap near pin 6 Design Note: tss = Css x 0.6V/2uA Ramp rate ~990us MODE 7 Design Note: Ith is tied to INTVCC for internal compensation 3 10 1% PVIN VON C PHMODE 9 2 PVIN PGOOD R219 137K C640 0.1uF 25V RT 8 1 LTC3605_RT CLKOUT CLKIN 24 2.5V_FPGA C202 22uF 25V 1210 B R222 4.70K, 1% LTC3605_RUN 3.3V Design Note: DNI for ES device R522 100K PGOOD_2.5V Cad Note: 1 overlapping pad A A Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet C 31 of 1 40 8 7 6 5 4 3 2 1 Power 3 - 2.5V HPS E E Cad Note: Place near INTVCC pin D23 LTC3605_INTVCC C608 D 1.0UF CMDSH-3 D LTC3605_BOOST Design Note: Added extra 1uF at INTVCC due to sourcing Vbias pin of LTC3025-1 C607 12V 2.2uF R175 LTC3605_SVIN 10 2.5V_HPS_FILT R190 47.5K 1% C191 560pF C605 LTC3605_ITH 6 19 SVIN 20 BOOST 21 INTVCC 22 SGND 23 EXPOSED PAD ITH SW 10pF C594 0.1UF 50V 18 17 16 C163 22uF 25V 1210 CAD Note: Regulator input caps Place near regulator controller LTC3605_SW EN_2.5V_HPS 27 R493 10.0K 0 R492 Design Note: DCR = 40m ohms 2.5V_REG_HPS Design Note: Prefer 0603 size cap 25V rated voltage is sufficient 2.5V_HPS R176 C 0.001 L18 15 1.2uH Isat = 11A 14 13 C178 R186 39pF 15K 1% C581 C184 C604 C591 22uF 22uF 22uF 22uF Cad Note: Place output caps near inductor LTC3605_FB R491 U40 LTC3605EUF B EN_2.5V_HPS L17 3A, 30 Ohm FB PGND DNI SW 25 LTC3605_INTVCC R189 TRACK/SS SW 5 12 LTC3605_SS 3300pF SW SW C606 FB 11 4 PGND LTC3605_FB SW RUN CAD Note: Overlap R289 & R290 pads at 1 of the pins Place resistor & cap near pin 6 Design Note: tss = Css x 0.6V/2uA Ramp rate ~990us MODE 7 Design Note: Ith is tied to INTVCC for internal compensation 3 10 1% PVIN VON C PHMODE 9 2 PVIN PGOOD R188 137K C592 0.1uF 25V RT 8 1 LTC3605_RT CLKOUT CLKIN 24 2.5V_HPS C164 22uF 25V 1210 178K 1% 2.5_HPS_VDACP4 27 B R191 4.70K, 1% RUN_2.5V_HPS 3.3V 3.3V R476 100K PGOOD_2.5V A A Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet C 32 of 1 40 8 7 6 5 4 3 2 1 Power 3 - 1.5V & 1.5V FPGA D19 E E LTC3605_INTVCC C512 1.0UF C513 2.2uF CMDSH-3 LTC3605_BOOST Design Note: Added extra 1uF at INTVCC due to sourcing Vbias pin of LTC3025-1 12V C515 EN_1.5V_HPS 27 33pF EN_1.5V_HPS R454 0 19 SVIN 20 BOOST 21 INTVCC 22 SGND 23 ITH SW C541 0.1UF 50V 18 16 C152 22uF 25V 1210 CAD Note: Regulator input caps Place near regulator controller D 17 Design Note: Prefer 0603 size cap 25V rated voltage is sufficient LTC3605_SW 1.5V_REG_HPS L13 15 R134 1.2uH Isat = 11A 14 13 PGND 24.0K 1% 6 25 1200pF R122 C106 LTC3605_ITH EXPOSED PAD SW DNI SW 12 LTC3605_INTVCC R123 TRACK/SS SW 5 11 LTC3605_SS 3300pF SW PGND C514 FB VON 4 SW 10 C LTC3605_FB MODE RUN CAD Note: Overlap R289 & R290 pads at 1 of the pins Place resistor & cap near pin 6 Design Note: tss = Css x 0.6V/2uA Ramp rate ~990us PVIN 7 Design Note: Ith is tied to INTVCC for internal compensation 3 PHMODE 9 169.0K R124 PVIN PGOOD 2 C151 22uF 25V 1210 C555 0.1uF 25V RT 8 D CLKOUT 24 CLKIN 1 LTC3605_RT 10 R148 LTC3605_SVIN C131 R130 39pF 15K 1% C130 C556 C565 C542 22uF 22uF 22uF 22uF 1.5V_HPS 0.003 Cad Note: Place output caps near inductor LTC3605_FB R455 U33 LTC3605EUF C 1.5V_HPS_VDACP2 27 215.0K R121 10.0K RUN_1.5V_HPS 3.3V R460 100K PGOOD_1.5V B B A A Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet C 33 of 1 40 8 7 6 5 4 3 2 1 Power 3 - 3.3V HPS E E Cad Note: Place near INTVCC pin D16 LTC3605_INTVCC C489 D 1.0UF CMDSH-3 C488 12V 2.2uF 69.8K 1% 220pF C486 19 SVIN 20 BOOST 21 INTVCC 22 SGND 23 ITH SW 5pF C474 0.1UF 50V 18 17 16 C78 22uF 25V 1210 CAD Note: Regulator input caps Place near regulator controller LTC3605_SW EN_3.3V_HPS 27 R445 0 3.3V_HPS R90 C 0.001 L8 15 1.2uH Isat = 11A 14 C94 39pF 13 R89 11.5K C485 C100 C441 C466 22uF 22uF 22uF 22uF Cad Note: Place output caps near inductor 1% LTC3605_FB R444 U27 LTC3605EUF B EN_3.3V_HPS 3.3V_REG_HPS Design Note: Prefer 0603 size cap 25V rated voltage is sufficient PGND R101 C107 EXPOSED PAD 25 6 LTC3605_ITH SW DNI SW 12 LTC3605_INTVCC R100 TRACK/SS SW 5 11 LTC3605_SS 3300pF SW PGND C487 FB 10 4 SW VON LTC3605_FB MODE RUN CAD Note: Overlap R289 & R290 pads at 1 of the pins Place resistor & cap near pin 6 Design Note: tss = Css x 0.6V/2uA Ramp rate ~990us PVIN 7 Design Note: Ith is tied to INTVCC for internal compensation 3 PHMODE 9 1% PVIN PGOOD 2 C79 22uF 25V 1210 C467 0.1uF 25V RT 8 R99 90.9K CLKOUT 24 CLKIN 1 LTC3605_RT 10 R84 LTC3605_SVIN C D LTC3605_BOOST Design Note: Added extra 1uF at INTVCC due to sourcing Vbias pin of LTC3025-1 66.5K 3.3_HPS_VDACP6 27 B R102 2.55K 1% RUN_3.3V_HPS 3.3V R446 10.0K 3.3V logic signal 3.3V R437 100K PGOOD_3.3V A A Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet C 34 of 1 40 8 7 6 5 4 3 2 1 Power - 1.1V_HPS, 5.0V, 1.8V CAD Note: Regulator input caps Place near regulator controller D18 12V 1.1V_HPS_INTVCC C516 E 1.0UF CMDSH-3 C204 22uF 25V 1210 1.1V_HPS_BOOST Design Note: Added extra 1uF at INTVCC due to sourcing Vbias pin of LTC3025-1 C544 12V 2.2uF 19 C129 22uF 25V 1210 C505 0.1uF 25V SVIN 20 BOOST 21 INTVCC 22 SGND 23 CLKOUT 24 CLKIN 1 1.1V_HPS_RT 10 R120 LTC3605_SVIN RT PVIN PHMODE PVIN C543 0.1UF 50V 18 C625 22uF 25V 1210 C573 22uF 25V 1210 E C582 22uF 25V 1210 PGOOD_1.1V_HPS C105 22uF 25V 1210 CAD Note: Regulator input caps Place near regulator controller Design Note: 0.001 ohm sense resistor minimized IR drop @ 3A R129 17 16 1.1V_HPS_SW EN_1.1V_HPS 27 0 R467 1.1V_HPS R161 D 0.001 L15 15 1.2uH Isat = 11A 14 C141 39pF 13 R147 12.4K C566 C567 22uF 22uF Cad Note: C150 Place output caps 47UF near inductor 6.3V 1.1V_HPS_FB R468 U32 LTC3605EUF C EN_1.1V_HPS 1.1V_REG_HPS Design Note: Prefer 0603 size cap 25V rated voltage is sufficient PGND C558 25 68pF R146 SW SW 10.0K C140 ITH 12 1.0nF 1.1V_HPS_ITH 6 EXPOSED PAD SW DNI SW 11 1.1V_HPS_INTVCC R133 TRACK/SS PGND 5 SW RUN CAD Note: Overlap R289 & R290 pads at 1 of the pins Place resistor & cap near pin 6 1.1V_HPS_SS FB 7 Design Note: Ith is tied to INTVCC for internal compensation 1000pF 4 10 C557 1.1V_HPS_FB SW 8 Design Note: tss = Css x 0.6V/2uA Ramp rate ~990us MODE VON 3 9 D PGOOD 2 316k 1% 215.0K 1.1V_HPS_VDACP027 C R145 RUN_1.1V_HPS 15K 1% 3.3V CAD Note: Regulator input caps Place near regulator controller 100K PGOOD_1.1V_HPS R466 12V B C177 25V 4 22uF 2 5.0V L28 1 C168 22uF 25V C162 0.1uF 2 6.5uH R157 Isat = 6A 52.3K D21 1 DFLS230 2 C161 R156 10K R153 3 VIN BD BOOST1 BOOST2 Fsw=1.7MHz SW1 SW2 B 12 6 5 C148 0.1uF L16 1 DNI 16.2K 11 10 DA1 DA2 FB1 FB2 RUN/SS1 RUN/SS2 SYNC RT GND DFLS230 D20 7 2 1 8 9 DNI C147 15 1V8 2 6.5uH Isat = 6A 1 14 13 FB_5.0V 5.0V U36 R144 12.4K C149 22uF 4V R143 10K LT3509EDE A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 35 of 1 40 C 8 7 6 5 4 3 2 1 Power 4 - Linear Regulators E E 2.5V_REG_FPGA 1.5V_REG_FPGA R510 10.0K C636 3.3V VIN EN PGOOD VREF_FPGA_DDR3 6 1uF REFOUT C613 TPS51200 0.1uF VLDOIN REFIN 2 1 10.0K R513 VTT_FPGA_DDR3 GND_PAD PGND GND C634 10.0K 10 7 9 C635 VO VOSNS 3 5 11 4 8 R511 D 10uF DDR3 FPGA VTT, VREF U61 10uF C619 C618 C617 C616 C620 10uF 10uF 10uF 10uF 10uF R516 10.0K C646 R408 10.0K C307 D 1.0nF 1.5V_REG_HPS C338 3.3V VIN EN PGOOD VREF_HPS_DDR3 6 1uF REFOUT C293 TPS51200 0.1uF VLDOIN REFIN 2 1 10.0K R409 C VTT_HPS_DDR3 GND_PAD PGND GND C292 10.0K 10 7 9 C308 VO VOSNS 11 4 8 R388 C 10uF DDR3 HPS VTT, VREF U58 3 5 10uF C475 C442 C363 C339 C490 10uF 10uF 10uF 10uF 10uF 1.0nF B B A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 36 of 1 40 C 8 7 6 5 4 3 2 1 Power 6 - Power & Temperature Monitor E E D D C C B B A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 37 of 1 40 C 8 7 6 5 4 3 2 1 Power 7 - Cyclone V GX SoC Power U21J 2.5V_FPGA Cyclone V GX SoC Power 1.1V_VCC E M11 M13 M9 N10 N12 N14 P11 P13 R10 R12 R14 T11 T13 U10 U12 U14 V11 V13 V15 W10 W12 W14 Y11 Y13 Y9 U21 D VCCPD3A VCCPD3A VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD3B4A VCCPD5A VCCPD5A VCCPD5B VCCPD8A VCCPD8A VCCPD8A VCCPD8A VCCPD8A VCCPGM VCCPGM VCCPGM VCCBAT VCC_AUX VCC_AUX VCC_AUX VCC_AUX VCC_AUX F1 G2 AA7 AD15 E26 J15 C DNU DNU DNU DNU DNU DNU VCC_AUX_SHARED VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL AA10 AC10 E AB18 AB20 AC13 AC15 AC17 AC19 AD16 AE21 U21K 2.5V_FPGA VREF_FPGA_DDR3 V22 V24 1.5V_FPGA (2.5V) U23 K11 K13 L10 L12 L14 1.5V_FPGA J11 AA23 AB10 AC11 AD8 AF7 AG4 AD6 AB14 AD13 AE15 AJ13 AJ8 AK10 AJ15 AA17 AC21 AD18 AE25 AF22 AG19 AH16 AH26 AJ23 AK20 AK17 2.5V_FPGA_FILT H9 AB11 AB16 AD22 H10 J16 Cyclone V GX SoC Power 2.5V_FPGA 2.5V_HPS_FILT VCCIO3A VCCIO3A VCCIO3A VCCIO3A VREFB3AN0 VCCIO3B VCCIO3B VCCIO3B VCCIO3B VCCIO3B VCCIO3B VREFB3BN0 VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VREFB4AN0 VCCIO5A VCCIO5A VCCIO5A VCCIO5A VREFB5AN0 VCCIO5B VCCIO5B VREFB5BN0 VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VREFB8AN0 W23 AG29 AD28 AB24 AC24 AE30 AA27 AA29 J13 H6 G9 G14 F12 E5 D8 C11 B4 A7 B10 D U21L AA5 M6 N5 T6 U5 Y6 2.5V_VCCAUX_SHARED J21 N7 R7 V8 AA8 K9 Y22 VCCE_GXBL VCCE_GXBL VCCE_GXBL VCCE_GXBL 1.1V_VCCL VCCL_GXBL VCCL_GXBL VCCL_GXBL VCCH_GXBL VCCH_GXBL VCCH_GXBL VCCE_GXBL VCCE_GXBL W5 R5 L5 3A, 30 Ohm FB 3.3V_HPS U16 T17 L18 R16 P19 P17 P15 L20 L16 T19 N20 M15 U18 2.5V_FPGA_FILT 2.5V_VCCAUX_SHARED L25 1.5V_HPS VREF_HPS_DDR3 B 2.5V_FPGA_FILT V6 P6 AB6 1.1V_HPS 5CSXFC6D_F896 5CSXFC6D_F896 2.5V_HPS Cyclone V GX SoC Transceiver & HPS Power 1.1V_VCCEL D28 G29 H26 K24 K30 L27 M24 N21 G27 P23 P28 R25 T22 U19 V26 U30 VCC_HPS VCC_HPS VCC_HPS VCC_HPS VCC_HPS VCC_HPS VCC_HPS VCC_HPS VCC_HPS VCC_HPS VCC_HPS VCC_HPS VCC_HPS VCCIO7A_HPS VCCIO7A_HPS VCCIO7B_HPS VCCIO7B_HPS VCCIO7C_HPS VCCIO7D_HPS VCCIO7D_HPS VREFB7N0_HPS F22 H21 C G19 E20 D18 3.3V_HPS E15 H16 E22 2.5V_HPS VCCIO6A_HPS VCCIO6A_HPS VCCIO6A_HPS VCCIO6A_HPS VCCIO6A_HPS VCCIO6A_HPS VCCIO6A_HPS VCCIO6A_HPS VREFB6AN0_HPS VCCPD6A6B_HPS VCCPD6A6B_HPS VCCPD6A6B_HPs VCCPD6A6B_HPS VCCPD6A6B_HPS VCCIO6B_HPS VCCIO6B_HPS VCCIO6B_HPS VCCIO6B_HPS VCCIO6B_HPS VCCIO6B_HPS VREFB6BN0_HPS VCCPD7B_HPS VCCPD7D_HPS VCCPD7C_HPS VCCPD7A_HPS VCCPLL_HPS VCCRSTCLK_HPS R23 R20 P21 N22 M21 K16 3.3V_HPS B J17 K18 K19 2.5V_HPS_FILT L21 2.5V_HPS J20 5CSXFC6D_F896 A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 38 of 1 40 C 8 7 6 5 4 3 2 1 Power 8 - Cyclone V GX SoC Ground E E U21I U21H Cyclone V GX SoC GND J6 J22 D26 A26 A12 A17 A2 A22 A27 AA11 AA22 AA3 AA4 AA6 AA9 AB1 AB19 AB2 AB29 AB5 AB7 AC16 AC26 AC3 AC4 AC6 AC8 AD1 AD2 AD23 AD5 AE10 AE20 AE3 AE4 AF1 AF12 AF17 AF2 AF27 AF3 AG14 AG24 AG9 AH1 AH11 AH21 AH6 AJ18 AJ28 AJ3 AJ30 AK15 AK25 AK5 B14 B19 D C B GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Cyclone V GX SoC GND B24 B29 B9 C1 C16 C21 C26 C6 D13 D23 D3 E10 E25 E30 F17 F2 F27 F5 F7 G24 G3 G4 H1 H11 K5 L11 L13 L15 L17 L19 L22 L3 L4 L6 M1 M10 M12 M14 M16 M18 M2 M20 M29 M5 M7 M8 N11 N13 N15 N17 N19 N26 N3 N4 N6 N8 N9 P1 P10 P12 P14 P16 P18 P2 P20 P5 P7 R11 R13 R15 R17 T20 R3 R30 R4 R8 H2 H5 J18 J28 J3 J4 J8 K1 K10 K15 K2 K20 K25 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND T7 U11 U13 U15 U17 U24 U29 U3 U4 U6 U9 V1 V10 V12 V14 V19 V2 V21 V5 V7 W11 W13 W18 W28 W3 W4 W6 W9 Y1 Y10 Y12 Y14 R6 Y15 Y2 Y20 Y25 Y30 Y5 Y7 Y8 U22 T18 T5 T27 T2 T16 T15 T14 T12 T10 T1 R9 D C B 5CSXFC6D_F896 5CSXFC6D_F896 A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 39 of 1 40 C 8 7 6 5 4 3 2 1 Decoupling 1.1V_vcc 1.1V_VCC 1.1V_VCCEL C344 E C314 330uF 2.5V C334 C559 330uF 2.5V C553 C560 330uF 2.5V 330uF 2.5V C290 C552 C561 C562 330uF 2.5V C554 C563 330uF 2.5V C531 330uF 2.5V C534 4.7uF 4.7uF 2.2uF C535 C502 C439 C539 C501 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF C533 C530 C532 C536 C537 C538 C510 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C438 C526 C386 C424 C384 C383 C410 1uF 0.47uF 1uF 0.47uF C280 330uF 2.5V C269 330uF 2.5V C303 C511 330uF 2.5V 100uF 6.3V C417 22uF 4V C390 4.7uF C480 C358 0.47uF C359 0.22uF 0.1uF 1.1V_VCCL C416 C440 47nF C360 C479 C63 C435 C74 C389 C388 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF C279 220 Ohm FB 0.47uF C67 C473 C462 4.7nF 22nF 22nF 22nF C382 100uF 6.3V 1uF C528 C437 2.5V_fpga 2.5V_FPGA L26 1.1V_vccel 0.47uF C385 C500 C357 0.22uF 0.1uF 47nF C469 C471 C478 C423 C343 0.01uF 0.01uF 22nF 4.7nF 4.7nF E 2.5V_fpga_filt 2.5V_FPGA_FILT 1.5V_vccio 1.5V_FPGA C468 C550 D 47nF 47nF 47nF 47nF 47nF 47nF 330uF 2.5V 47nF C551 4.7uF C521 0.47uF C522 C523 C524 0.22uF 0.1uF 47nF C406 C428 C430 C432 C458 C460 C525 C527 C470 C477 C529 47nF 47nF 47nF 47nF 47nF 47nF 0.01uF 0.01uF 0.01uF 22nF 22nF C455 C457 C456 C431 C429 C433 C459 C405 22nF 22nF 22nF 22nF 22nF 22nF 22nF 22nF C409 C413 C404 C408 C412 C411 C407 22nF 22nF 22nF 22nF 22nF 22nF 22nF C508 C454 C507 C499 C509 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF C476 100uF 6.3V C356 0.47uF 1uF C387 C355 0.1uF 47nF C436 C414 C453 C472 C498 0.01uF 0.01uF 0.01uF 0.01uF 22nF C434 C415 C461 4.7nF 4.7nF 4.7nF D 1.5V_hps C 2.5V_HPS C 1.5V_HPS 2.5V_hps C347 C449 1.1V_HPS 100uF 6.3V C277 C278 100uF 6.3V C380 C276 100uF 6.3V 0.47uF 2.2uF C379 C381 0.22uF 0.1uF C427 C425 C402 C401 C426 C403 47nF 47nF 22nF 22nF 22nF 22nF B C397 4.7uF C452 0.47uF C373 C421 C398 0.1uF 47nF 47nF 330uF 2.5V C450 C374 C451 C352 C377 C375 C422 0.01uF 0.01uF 0.01uF 0.01uF 22nF 22nF 22nF C399 C400 4.7nF 4.7nF C329 4.7uF C295 0.47uF C296 C372 C312 0.22uF 0.1uF 47nF C313 C330 C331 C350 C340 0.01uF 0.01uF 0.01uF 22nF 22nF C348 C332 C333 C341 C349 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF B 2.5V_HPS_FILT 2.5V_VCCAUX_SHARED SCREW2 STANDOFF1 SPACER1 SCREW4 STANDOFF2 SPACER2 SCREW1 SCREW5 STANDOFF3 2.5V_HPS_FILT 3.3V_HPS C272 1uF 3.3v_HPS C271 4.7uF C274 C273 C300 C299 C298 A 1uF 0.22uF 0.1uF 47nF C297 C353 C378 C351 C354 0.01uF 0.01uF 0.01uF 4.7nF 4.7nF Title B Date: 5 10uF 47nF 0.01uF 22nF A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Size 6 C376 PCB1 22nF 7 C301 STANDOFF4 C342 8 C302 SCREW3 SCREW6 100uF 6.3V C275 4 3 Cyclone V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0321003-C1 Wednesday, March 20, 2013 2 Rev (6XX-44184R) Sheet 40 of 1 40 C

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