International Journal of Engineering & Technology IJET-IJENS Vol: 11 No: 02
130
Performance of A Laboratory Static Var Compensator
Maamar Taleb
Mustafa Ibrahim Hasan
Mahmood Marzooq Mansoor
Department of Electrical and Electronics Engineering University of Bahrain
Isa Town, Bahrain
e-mail: maamar@eng.uob.bh
Abstract— This paper presents a laboratory model for a shunt
I
Zs=jXs
V
t
P+jQ
V
s
LOAD
static var compensator (SVC). Such shunt static var
compensator (SVC)
is useful in the control of power
distribution feeders. The type of the SVC considered in this
investigation is the famous thyristor-controlled reactor (TCR)
configuration. LABVIEW software has been used as a
practical platform to control the operation of the SVC
thyristors. For a labratory load voltage fluctuating originally
between 265 V at light loading and 240 V at heavy loading, a
near 240 V as an rms value was kept constant at the feeder
terminals. That was observed when installing the SVC and
changing randomly the level of the feeder loading. The
introduction of the SVC resulted in some distortion in the load
voltage waveform but luckly the measured total harmonic
distortion factor (THD) was found to be below the allowed levels
reported in relevant IEEE power quality standards.
(a)
jXsI'
Vs
Vs
Index Term-- Static Voltage Compensators, Power System
Harmonics,
Education.
jXsI
LABVIEW Applications, Electrical Engineering
Ip=I'p
I.
INTRODUCTION
Static var compensators (SVC) have been applied to utility
and industrial power for many years. Therefore, SVCs are not
new to the industry, and by themselves, are not an overly
complex device. To understand the need of installing an SVC
when needed, consider the simple per-phase system
equivalent circuit shown in figure1.(a) [1] by means of the ac
system Thevenin equivalent, where the internal impedance of
the ac system is assumed to be purely inductive. Figure1.(b)
shows the phasor diagram for a lagging power factor load
P+jQ with a current I=Ip+jIq, which lags the terminal voltage
Vt. An increase Q in the lagging vars drawn by the load
causes the reactive current component to increase to Iq+ Iq,
while Ip is assumed to be unchanged. The phasor diagram for
the increased Q is indicated by ``primed'' quantities in
figure1.(b) where the magnitude of the internal system
voltage Vs remains the same as before the change. The
phasor diagram of figure1(b) shows a drop in the terminal
voltage by  Vt caused by an increase in the lagging reactive
power drawn by the load. In this case, even if Ip remains
constant, the real power P will decrease because of the
Vt
V't
Vt
Iq
Iq
I
I'
I'q
(b)
Vs
Vs
Ip
I'p
Ip
Iq=I'q
I
V't
Vt
Vt
I'
(c)
Fig. 1. Effect of Load on the terminal Voltage
a) Equivalent circuit b) Change in real load current
c) Change in reactive load current
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International Journal of Engineering & Technology IJET-IJENS Vol: 11 No: 02
Voltage Source (Vs)
Feeder
240 V rms, 50 Hz
Inductance (Lt)
132.2 mH
Load
Variable Resistance (R)
120 to 400 ()
Static Var Compensator
SVC
Fixed Capacitor
(C)
7.98 F
Reference Voltage (Vref)
Vref
Inductor (L)
132.2 mH
239 Volts
+
Firing Angle
Vmea
Comparator
Vt
Synchronized
Sawtooth
Waveform
Generation
Firing pulses
II.
STUDY SYSTEM
Figure 2 shows the general circuit diagram of the SVC as
well as its main control blocks. The figure shows a
distribution bus voltage ( i.e source voltage) in series with a
series impedance. The impedance represents the feeder
impedance. The SVC configuration is shunted with a power
load. The SVC contains a fixed capacitor (C) in parallel with
the thyristor controlled reactor . The values of the parameters
of figure 2 are shown in table I.
The control blocks represent actually the firing angle control
circuit needed by the thyristors of the TCR branch. The
control blocks consist of:
1- an rms detector which measures simply the effective (rms)
value of the load voltage or the SVC branch voltage,
2- a gate pulse generator (GPG) whose purpose is to compare
first the SVC branch rms voltage with a reference voltage and
based on this comparison, it initiates desired accurate instants
of firing angle. Content of the gate pulse generator is shown
in figure 3.
TABLE I
PARAMETERS VALUES OF FIGURE 2
(a)
sign
Integrator
and Limiter
Vref
1
1
+
X
U
Vmea
100
s
0
abs
Firing angle
reduction in Vt. For comparison purposes, Figure 1.(c) shows
the phasor diagram where the percentage change in Ip is the
same as the percentage change in Iq in figure 1.(b), while Iq
is assumed to be unchanged. Figure 1.(c) shows that the
voltage change Vt is small due to a change in Ip. The last
observation suggests that for the sake of controlling the
terminal voltage Vt, a reactive power source rather than a real
power source should be installed in shunt with the load to
compensate for any temporarily need of power by the load.
This required source can be simply thought as a variable
capacitor bank. Varying this capacitor should be fast and
therefore it can not be done mechanically. To perform such a
requirement, a fixed capacitor is installed in shunt with a
controlled power semi-conductor switches in series with a
fixed power inductor element. Controlling the on/off
switching times
of the semi-conductor switches will
ultimately vary the reactive power needed by the system.
131
Gain
Selector
(b)
Sawtooth
Signal
Feeder
RMS
Dectector
(c)
L
LOAD
Firing
Pulses

SCR1
SCR2
(U+5)/180
Firing
angle
+
+
-
(U)/180
0
+
X
0
Firing pulses
C
Gate Pulse
Generator
Sawtooth
Signal
Vs
Load Voltage (V)
Vref
Source
Voltage
(d)
Fig. 2. Study System
Fig. 3. SVC Firing Angle Controller a) General Block b) Content of
Firing Angle Block C) Content of Synchronized Sawtooth Waveform
Generation Block D) Content of Comparotor Block
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International Journal of Engineering & Technology IJET-IJENS Vol: 11 No: 02
When analyzing the steady state operation of the SVC circuit
of figure 2, two modes of operation can be noted. The time
location of the two modes of operation is shown in figure 4.
iL
p-α
2p-α
α
p+α
The numerical solution of such state space model will predict
the load voltage waveform behavior.
III.
STUDY SYSTEM PERFORMNACE
To predict the performance of the power system under study,
LABVIEW software [2] has been used as a real time practical
control platform. In LABVIEW, the firing angle controller
of figure 3 has been programmed.
The input to such
programmed controller is simply the stepped-down load
volatge and the output is the synchoronized pulses. The
synchronized pulses are interfaced with the thryristors gates
of figure 2 through the simple circuit shown in figure 5.
v
0
132
2p
time
Mode I
Mode II
Mode I
Mode II
Mode II
Fig. 4. Operation Modes Location
Mode I: is characterized by the time durations
in one
cycle where  represents the firing angle and  is the
angular velocity of the supply voltage (Vs). In such a mode,
the two thyristors are not conducting and thus the SVC
inductor can be omitted. The resulted circuit can be found
to be described by the following second order differential
equation:
Vs  Lt C
d 2 v Lt dv
+
+v
dt 2 R dt
Fig. 5. Interface Circuitry Between LABVIEW and Study System
(1)
The load resistance (R) was varied between its two limits
and measurements of the load voltage, and the firing angle
were recorded. Table II reports such measrements.
V: represents the load voltage.
Mode
II:
is
characterized
by
the
time
duration
TABLE II
STUDY SYSTEM PERFOMANCE
in one cycle. In such mode, one of the two thyristors is
conducting and the resulted circuit can be described by the
following second order differential equation:
Vs 
Lt
d 2 v L dv
v + Lt C 2 + t
+v
L
R dt
dt
(2)
iL represents the SVC inductor current or TCR current
Equations 1 and 2 can be transformed into a state space
model of the form:
 dv 
Lt C   v 
0

 dt 
0 

 
1
1  
 
  +
  LC
 V s
- (1 + m * Lt ) - Lt    Lt C 1
t
 dx 
 

L
R   x 
 dt 
(3)
Load Resistance
R ( )
Load
Voltage (V)
Firing Angle
(0)
120
150
180
200
220
250
300
400
239
238.5
238.5
238
238.5
239
239
238
162
144
129.6
126
118.8
115.2
100.8
97.2
Load Voltage (V)
In the absence of
Control
239
247
252
254
256
258
260
261
As it seen from the second column, the load voltage is kept
self-controlled (near 239 V). The fourth column of Table II
represents actually the measured load voltage values in the
absence of SVC inductor branch (i.e The values of such
column were obtained by not generating pulses to the gates
of the thyristors while varying the load resistance). Besides
controlling the rms value of the the voltage at the feeder
terminals, the ohmic losses in the feeder are also reduced.
This is possible through the reduction of the current levels in
m takes 0 value for mode I and 1 for mode II.
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International Journal of Engineering & Technology IJET-IJENS Vol: 11 No: 02
the feeder. Table III reports the measured current in the
feeder with and without installing the SVC module.
Load
Resista
-nce R
( )
120
150
180
200
TABLE III.
FEEDER CURRENT (RMS) VALUES.
I (A)
I(A)
Load
I (A)
With the
In the
ResistaWith the
Presence
absence
nce R
Presence
of the
of the
of the
( )
SVC
SVC
SVC
220
2.07
2.08
1.13
250
1.66
1.78
1.01
300
1.37
1.54
0.84
400
1.24
1.43
0.65
I(A)
In the
absence
of the
SVC
1.34
1.23
1.10
0.93
As to the quality of load voltage, voltage waveforms at the
feeder terminals were captured and analyzed. That was done
through through the computation of the total harmonic
distortion factor (THD). Figure 6 depicts the load voltage
waveforms for two loads. The pulses shown in such figure
are actually the pulses generated to the TCR SCRs gates.
Table IV represents the measured total harmonic distortion
factor.
133
TABLE IV
TOTAL HARMONC DISTORTION FACTOR
Load Resistance
THD (%)
Load Resistance
THD (%)
R ( )
R ( )
120
220
2.63
6.95
150
250
5.14
6.73
180
300
6.52
6.05
200
400
6.70
5.68
As it is observed, all measured values of the THD fall-in
within the allowable IEEE Standard 519 limits [3].
IV. CONCLUSION
A laboratory module representing a static var compensator
using the thyristor controlled reactor (TCR)
has been
invesitaged in this paper. LABVIEW has been used as a
practical controller to generate the online required firing
angles required by the TCR for different feeder loadings.
Quite satisfactory practical results concerning the control of
the feeder terminal voltage were reached. The introduction of
the SVC configuartion resulted in certain load voltage
waveform distortion, but luckly the measured total harmonic
distortion factor values were within the allowable standard
limits.
REFERENCES
[1] N. Mohan, T. M. Undland, and W. P. Robbins, Power Electronics:
Converters, applications, and Design, John Wiley and Sons Inc., 2nd Edition,
New York, 1995, pp. 471-472.
[2] LABVIEW Software. Version 8.6, National Instruments Inc., Texas,
2007.
[3] IEEE Standard 519, Recommended Practice on Monitoring Electric
Power Quality , 1992.
BIOGRAPHY
Maamar Taleb received the B.Sc. degree in Electrotechnics from University
of Sciences and Technology of Wahran, Algeria in 1983, the M.Sc. in
Electric Power Engineering from Renssealaer Polytechnic – New York, USA
in 1986, and the Phd degree in Electrical Engineering from Clarkson
University – New York, USA in 1990.
(a)
Maamar Taleb had held a research associate position in Electrical
Engineering at Clarkson University in the period of 1990-1992.
In 1992, Maamar Taleb joined University of Bahrain. He is currently an
associate professor in electrical engineering at University of Bahrain.
Dr. Taleb research interests are: Power Quality issues, Power system
modelling, and Renwable Energy Applications.
(b)
Fig. 6. Load Voltage Waveform a) Load Resistance = 150 , b) Load
Resistance = 400 ,
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