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Correlation Receivers for Detecting Cosmological Signals by Girish B. S. Srivani K. S., Saurabh Singh, Mayuri S. Udaya Shankar N., Ravi Subrahmanyan Raman Research Institute Bengaluru A National Workshop Cosmology With the 21-cm HI Line June 23 – 26, 2015 Introduction RRI is working towards the goal of building precision receivers for detecting signals from the Epoch of Recombination & the Epoch of Reionization Array of Precision Spectrometers for the Epoch of Recombination APSERa - a project to detect recombination lines from the Epoch of Cosmological Recombination. Detecting Epoch of Recombination signatures in the CMB spectrum is extremely challenging, since the estimated magnitude of fluctuations is 8 to 9 orders of magnitude weaker than the CMB radiation temperature A National Workshop – Cosmology With The 21-cm H1 Line, June 23 – 26, 2015 About APSERa Feasibility study has shown that optimal frequency range for operating APSERa to be around 2 - 6 GHz APSERa is likely to consist of an array of 128+ purpose-built small telescopes, operating in the above frequency range Rapid advances in technology allows development of broadband precision receivers to attempt such challenging tasks Currently, a prototype system consisting of antennas, precision analog front-end & digital receivers, is being designed & developed at RRI. A National Workshop – Cosmology With The 21-cm H1 Line, June 23 – 26, 2015 In this talk…. This talk highlights the design challenges in the development of a broadband correlation spectrometer based on pSPEC (RRI’s high speed signal processing platform) and preliminary results obtained from pSPEC prototype A National Workshop – Cosmology With The 21-cm H1 Line, June 23 – 26, 2015 Correlation Spectrometer - Requirements Capability to digitize and process broadband signals having a bandwidth of about 2 to 3 GHz Channelize the sampled signal into narrow sub-bands (8192) by implementing efficient polyphase filter banks which provides a handle on shape of pass band and adjacent channel rejection A high dynamic-range, RFI-tolerant receiver Channel-wise cross-correlation to obtain cross-power spectra of the sampled signal A common DSP platform that can cater to requirements of both EoR and Recombination experiments is being developed A National Workshop – Cosmology With The 21-cm H1 Line, June 23 – 26, 2015 Time-interleaved ADCs to enhance sampling rate High bit precision, 5 to 6 GSps commercial ADCs not easily available. Large BW requirements are met by time interleaving multiple, highspeed ADC modules Sampling rate increased by a factor of M, by time interleaving M ADCs with sampling CLKs phase offset by A National Workshop – Cosmology With The 21-cm H1 Line, June 23 – 26, 2015 Challenges in time interleaving ADCs Offset mismatch Gain mismatch Phase mismatch Sampling Fin= 1 GHz (1000 ps), a 10 ps (3.6°) skew in sampling clock between TI-ADCs degrades SNR to ~25 dB Offset mismatch is independent of Fin and its amplitude Gain mismatch: Largest error in channel outputs occurs at peak amplitude Phase mismatch: Largest error in channel outputs occur during largest slew rate A National Workshop – Cosmology With The 21-cm H1 Line, June 23 – 26, 2015 Gain and Phase mismatch errors If two 10-bit ADCs are time-interleaved, to obtain a system performance of ˜62 dBc, gain matching and phase matching (clock skew) between time-interleaved ADCs should be better than 0.1% and 0.04 degrees (~120 femtoseconds at 1000 MHz) Offset, Gain and Phase matching between channels/cores of modern ADCs can be realized by: • Using ADC’s on-chip compensation features • Matching flight-times of signals routed between ADCs and FPGA to within timing-budget • Finer path delay adjustment features inside the FPGA A National Workshop – Cosmology With The 21-cm H1 Line, June 23 – 26, 2015 Sampling Clock Jitter Flatness of pass band Each sample of autocorrelation function is perturbed using a normally distributed jitter Nulls in the autocorrelation function do not average to zero due to asymmetric nature of the autocorrelation function around each null Resulting bias due to averaging, alternates between positive and negative values for odd and even nulls Sampling clock jitter (rms) of about 100 fs Results in a peak-peak pass band ripple of about 0.0004 dB A National Workshop – Cosmology With The 21-cm H1 Line, June 23 – 26, 2015 Overview of RRI’s high-speed DSP platform Digital Signal Processing platform (pSPEC) built around multi-GSps ADCs and Virtex 6 FPGA Processing of 4 analog signals at Fs = 2 GSps (2 ADCs in time- interleaved mode) MWA Technical Meeting, The University of Melbourne, June 9 – 10, 2013 Choice of ADC for pSPEC Quad, 10 –bit ADC Block Diagram of EV10AQ190CTPY Analog BW = 3 GHz Fclk (max) = 1.25 GHz LVDS output format A B C D DDR output protocol 500 mV p-p analog input (-2 dBm) +3.3 V, +1.8 V supplies 1.4 W per channel Modes of operation: a. 4 independent channel mode (BW = 625 MHz, each) b. 2, 2-channel time-interleaved mode (BW = 1.25 GHz) c. 1-channel time-interleaved mode (BW = 2.5 GHz) In-built analog cross-point switch (multiplexed) SPI interface for Gain matching (steps of 0.02%, ±10 %), Offset matching (steps of 40 µV, ±40 LSBs), Phase matching (steps of ~30 femtoseconds, ±15 ps) A National Workshop – Cosmology With The 21-cm H1 Line, June 23 – 26, 2015 pSPEC: Evaluation of ADC module Effective Number Of Bits of 7 bits and Signal-to-Noise Ratio (SNR) of 44dB for an input tone at 1GHz (-3dBm), compares favourably with datasheet specification. Advantageous to use Quadrature Sampling Instead of time interleaving multiple ADC cores to enhance sampling rate, Quadrature Sampling is used In Quadrature Sampling, Fs at each ADC needs to be ≥ signal bandwidth, as opposed to twice the bandwidth in real sampling When we need to digitize wide bandwidths, Quadrature Sampling is very attractive, especially, when the aim is to used FFT-like processing for spectral analysis. FFT engine can be used efficiently by feeding complex numbers as input, rather than real numbers. A National Workshop – Cosmology With The 21-cm H1 Line, June 23 – 26, 2015 Channelization – Divide & Conquer approach De-multiplexed ADC data:1 GSps/4 @ 250 MSps feed 8 smaller pipelined FFTs Modern, high-performance FPGAs allow parallelization of FFT algorithm (M=8, N=1024) A combination of optimized, pipelined FFT core and custom-designed parallel FFT. Implementation of large BW, high- resolution spectrometer possible. A National Workshop – Cosmology With The 21-cm H1 Line, June 23 – 26, 2015 Preliminary results from pSPEC Tone i/p (Fin) Fs/2 Fs/2 - Fin Input to pSPEC: Tone at 78.125 MHz, -22 dBm Two ADCs each in TI mode-of-operation -I, Q(set to 0) Effective Sampling rate = 1 GSps x2 = 2GSps FFT length = 8192 On-chip averaging for 16.77ms For a tone i/p at 78.125 MHz (-22 dBm), achieved SNR value matches with the ADC datasheet specifications. A National Workshop – Cosmology With The 21-cm H1 Line, June 23 – 26, 2015 Preliminary results from pSPEC Broadband noise input (LPF, with fc = 450 MHz) Two ADCs each in TI modeof-operation -I, Q(set to 0) Eff. Sampling rate = 2 GSps FFT length = 8192 On-chip averaging for 16.77ms Self-power spectra and cross-power spectrum For broadband noise i/p, we get the expected band shape and SNR A National Workshop – Cosmology With The 21-cm H1 Line, June 23 – 26, 2015 SARAS (for EoR experiment) Shaped Antenna measurement of the background RAdio Spectrum (40 – 200 MHz) FREQUENCY -Hz FREQUENCY -Hz Input: Tone at 78.125 MHz, -26 dBm Fs = 500 MSps, FFT length = 8192 (weighted by Blackman-Nuttal Window) On-chip averaging for ~67ms A National Workshop – Cosmology With The 21-cm H1 Line, June 23 – 26, 2015 SARAS Picture of integrated EoR spectrometer A National Workshop – Cosmology With The 21-cm H1 Line, June 23 – 26, 2015 S Thank you