TN-30: Digitization at the Antenna with DTA9500, Featuring Multi-GSPS ADC and DAC
and Multiple 10 GbE Networks
Introduction
Digitization at the antenna has been the ultimate objective for implementing a true
Software Radio transceiver. However, the obstacles of achieving high dynamic range and
handling a large instantaneous bandwidth have prevented users from having a deployable
solution. The DTA-9500 addresses these challenges by utilizing D-TA's 10 Gigabit
Sensor Processing Architecture. The DTA-9500 is available in two versions: <i>
conduction cooled module operating from a 24/28V DC power supply providing two
channel digitization at 1.8 GSPS each and up to four (4) 10GbE links for high-speed data
transfer and <ii> air-cooled module that provides up to four channels at 1.8 GSPS each
and up to eight (8) 10GbE links for data transfer. Unlike other board level limited
capability products available in the market place, the 10GbE links in the DTA-9500 allow
the ability to record and process in real time, the entire RF bandwidth for an extended
period of time. Thus, DTA-9500 is the only solution that allows recording of multiple 1.5
GHz bandwidth RF signals for hours and hours.
System Architecture
The simplified block diagram of the DTA-9500 is shown in Figure 1. The DTA-9500
includes a high speed dual ADC, with 12-bit precision that can handle 2-channels at 1.8
GSPS each or a single channel at 3.6 GSPS. A single channel 12-bit DAC capable of
running at 4 GSPS is also available as an option. An integrated optional GPS receiver is
also available for GPS time-stamping and providing a GPS locked 10MHz reference.
Major Features:
•
Dual 12-bit ADC providing 2-channel digitization at 1.8 GSPS each or 1-channel
at 3.6 GSPS. The Air cooled version doubles the channel count (4-channel at 1.8
GSPS each or 2-channel at 3.6 GSPS each)
•
12-bit DAC at 4 GSPS (single channel for the conduction cooled version, two
channels for the air-cooled version)
•
Flexible clocking and multi-unit synchronization for higher channel count
•
Built in RF front end with gain, programmable attenuator and band-pass filters.
TN-30 Rev: A Updated: November 2011
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•
•
PLL,
CLOCK
GEN ERATTION
& DISTRIBUTION
DDR3
RF
In
V6 FPGA
4
ports
DAC
(MAX19693 )
Filters, Amp
GPS IN
(fro m GPS
Antenna)
1-ch at 3.6 GSPS OR
2-ch at 1.8 GSPS
DDR3
10GbE
PHY
10GbE
PHY
10GbE Optical
Module
10GbE
PHY
DDR3
DDR3
10GbE Optical
Module
TRIG2 IN/
OUT
10GbE
PHY
10GbE Optical
Module
ADC
(ADC12D1800 )
TRIG2 IN/
OUT
NAND
PPS, LOC,
TIM E, ETC.
10GbE Optical
Module
CLK
IN/OUT
SYNC
IN/
OUT
DDR3
DDR3
V6 FPGA
2/4
ports
Front End
LNA, F ilter
REF IN/
OUT
DDR3
DDR3
1GbE Optical
•
GPS RECEIVER
•
1GbE Optical
•
The band-pass filters can be customized for specific application
Built in clock delay function in the ADC chip (36 fs steps) for calibration and
multi-unit synchronization
Large Virtex 6 (LX130T as standard, SX315T available as upgrade) FPGA
Up to four (4) 10GbE Networks (fiber) for full rate data transfer
Seamless operation with DTA-5000 record and playback unit for wideband RF
record and playback capability
1GbE link (fiber) for command and control
RF Out
1-ch at 3.6 GSPS
Figure 1: System Block Diagram of the conduction cooled DTA-9500 transceive system
ADC / DAC RF Front End
The ADC RF Front End is shown in Figure 2.
~
~
~
BPF
~
~
~
PROG
ATTN
AMP
BPF
~
~
~
AMP
XFRM R
BALUN
TO ADC
BPF
Figure 2: ADC RF Front End offers a maximum gain of 18 dB
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The DAC RF Front End is shown in Figure 3.
FROM
DAC
~
~
~
XFRM R
BALUN
BPF
~
~
~
PROG
ATTN
AMP
BPF
Figure 3: DAC RF Front End offers a maximum gain of 7 dB
The attenuators used in the RF Front End are software programmable in 0.25 dB steps
with a maximum settable value of 31.75 dB. These programmable attenuators can be used
to balance gain. When used in conjunction with the clock delay feature of the ADC, it
offers a powerful way of accurate synchronization of multiple channels.
Added Features that makes DTA-9500 ideal for a variety of applications
RF Front End: The DTA-9500 has a
sophisticated RF front end with customizable
filters, LNA and programmable attenuator
(0.25 dB steps). The max gain for the ADC
front end is 18dB, while for the DAC it is 7
dB.
applications. The received signal can be
suitably modified to be transmitted out via
the high speed DAC for lowest latency.
FPGAs available for user Processing: The
DTA-9500 has two Virtex 6 FPGAs that can
be used to implement custom DSP modules.
Full Data Rate: Four 10GbE network links, The standard FPGA is LX130T and can be
allow the DTA-9500 to handle the entire RF upgraded to SX315T.
bandwidth and enable continuous and
Conduction Cooling and Digitization at the
sustained recording of the RF spectrum.
Antenna: The DTA-9500 has four fiber links
GPS Receiver: The in-built GPS receiver for transfer of data. The conduction cooled
allow GPS time stamping on the data as well box enables the unit to be placed near the
antenna for maintaining performance while
as having a GPS locked sampling.
the fibers allow data transfer over a long
Clocking Options: The DTA-9500 sample
distance. The 1GbE control link is also over
clock can be internal or external. In case, it is
fiber.
internally generated, the internal synthesizer
can be locked the internal (100 MHz TCXO) 10GbE Networks: Like all D-TA products,
or external reference signal (10 to 100 MHz). the DTA-9500 implements four (4) 10 GbE
networks for high speed data transfer for
Ideal for ECM / EW applications: By
recording and processing. This allows real
integrating the DAC in the unit, the DTAtime processing and recording of the entire
9500 is ideal for EW, ECM, DRFM
bandwidth.
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Major Specification
FEATURES
VALUE
COMMENTS
ADC Section
Number of ADC Channels
1-ch at 3.6 GSPS Or
2-ch at 1.8 GSPS each
ADC Chip
ADC12D1800
Maximum Sample Rate
3.6 GSPS
Minimum Sample Rate
300 MHz
Contact Factory for extending range
Precision
12 bits nominal
Data is also available as 8-bit to reduce
data rate
Full Scale Input
0 dBm
With 0 dB gain in the RF Front End
Input Impedance
50 Ohm
Input Coupling
AC Coupled with transformer
On board RF Front End provided
Input 3-dB Bandwidth
450 to 1500 MHz
Limited by standard BPFs. BPFs can be
removed or changed
ADC Input Connector
50 ohm SMA Female
SFDR
< -65dBc
ADC data sheet performance achieved
Integrated SNR
58 dB
ADC data sheet performance achieved
ADC RF Front End Noise
Figure
7 dB
With Maximum Gain
ADC RF Front End Gain
18 dB
ADC RF Front End IP3
35 dBm
Output IP3
ADC RF Front End Gain
Control
31.75 dB in 0.25 dB steps
Software programmable attenuator.
From National Semiconductors
DAC Section
Number of DAC Channels 1
DAC Chip
MAX19693
From Maxim IC
Maximum Conversion Rate 4 GSPS
Precision
12 bits nominal
Output Impedance
50 Ohm
DAC Output Connector
50 Ohm SMA Female
SFDR
< -68 dBc
DAC RF Front End Gain
7 dB
DAC RF Front End IP3
35 dBm
Limited by the DAC performance. Non
including FDAC/4, FDAC/2, FDAC/2-FOUT
spurs
Output IP3
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FEATURES
VALUE
COMMENTS
DAC RF Front End Gain
Control
31.75 dB in 0.25 dB steps
Software programmable attenuator.
Maximum Output Level
5 dBm
DAC operating at full scale
Clock Section
Internal Reference Clock
100 MHz TCXO
TCXO Phase Noise
(typical)
< -100 dBc/Hz @ 100 Hz offset
< -150 dBc/Hz @10 kHz offset
TCXO Frequency Stability
+/- 5 ppm over all
+/-1 ppm (initial tolerance at
25C)
PLL Chip
ADF4350
VCO
Integrated with the PLL chip
External Clock and
reference Input
50 Ohm SMA Female
External Reference
10 to 100 MHz
External Reference Level
Sine +6 dBm (Maximum)
From Analog Devices with integrated
VCO
Data FPGA Section
Number of FPGAs
2
Standard FPGA
Virtex 6: XC6VLX130T
FFG1156 package used
Upgraded FPGA as option
Virtex 6: XC6VSX315T
Other options may be provided (contact
factory)
10GbE MAC
Implemented in the FPGA
10GbE Interface
XFP: 850 nm for Short Reach
Multi Mode Fiber
Up to four (4) interfaces
Memory per FPGA
4 x 128 Mbytes of DDR3
SDRAM
Total 1 Gbytes of DDR3 SDRAM
distributed over 2 FPGAs
Input Power
Input Voltage
Conduction Cooled: 24 /28V DC
Air Cooled: AC Power
Maximum Power
Consumption
150 W
Mechanical
Dimension – Conduction
Cooled
11.5” (W) x 11” (D) x 3.5” (H)
TN-30 Rev: A Updated: November 2011
Flanges provided for mounting. Contact
factory for exact mechanical drawing
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FEATURES
VALUE
COMMENTS
Dimension – Air Cooled
1U high, 20” deep, 19” rackmountable
Maximum Mass
8 kg (17.7 lbs)
Environmental
Operating Temperature
-20C to +70C ambient
(conduction cooled)
0 to +55C ambient (air cooled)
Ambient at cold plate. The environment
must be able to adequately dissipate the
thermal load of the DTA-9500. Provisions
of attaching an external fan to blow air on
the conduction cooled chassis available.
The air cooled chassis comes with fans
and the user has to ensure that airflow is
not blocked.
DTA-9500 Configurations
10GbE
PHY
10GbE
PHY
10GbE Optical
Module
10GbE Optica l
Module
CLK
IN/OUT
SYNC
IN/
OUT
ADC
(ADC12D1800)
TRIG2 IN/
OUT
TRIG2 IN/
OUT
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
NAND
V6 FPGA
V6 FPGA
2/4
ports
Front End
LNA, F ilte r
REF IN/
OUT
DDR3
1GbE Optical
PLL,
CLOCK
GEN ERATTION
& DIS TRIBUTION
DDR3
RF
In
1-ch at 3.6 GSPS OR
2-ch at 1.8 GSPS
Figure 4: System Block Diagram of DTA-9500S-1R-2F (ADC only with two 10GbE
links)
The DTA-9500 is a modular design and thus various configurations can be easily
supported. Customized packaging of these configurations are also possible. Figure 4
shows the ADC only configuration with 2 fiber links.
Figure 5 shows the ADC only configuration with 2 fiber links.
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DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
TRIG2 IN/
OUT
1GbE Optical
10GbE
PHY
10GbE
PHY
10GbE Optical
Module
TRIG2 IN/
OUT
10GbE
PHY
10GbE Optical
Module
CLK
IN/OUT
SYNC
IN/
OUT
10GbE
PHY
10GbE Optical
Module
ADC
(ADC12D1800)
Front End
LNA, Filter
REF IN/
OUT
V6 FPGA
V6 FPGA
2/4
ports
10GbE Optical
Module
PLL,
CLOCK
GEN ERATTION
& DISTRIBUTION
NAND
RF
In
1-ch at 3.6 GSPS OR
2-ch at 1.8 GSPS
Figure 5: System Block Diagram of DTA-9500S-1R-4F (ADC only with four 10GbE
links)
Similar configurations are also available with the DAC only version.
Figure 6: The same modules used for the air-cooled version to achieve up to four
channels sampling at 1.8 GSPS each with up to eight 10GbE links
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ADC 1
ADC 2
Clock &
Control
2 x Virtex 6 FPGA
10GbE
10GbE
ADC 3
Clock &
Contro l
ADC 4
2 x Virtex 6 FPGA
10GbE
10GbE
10GbE
10GbE
10GbE
10GbE
Figure 7: An air-cooled version of the DTA-9500 with 2 ADC channels at 3.6 GSPS
each or 4 channels at 1.8 GSPS each
The same modules can be packed in a air-cooled chassis to provide four channels at 1.8
GSPS each with eight 10GbE links as shown in Figure 6 and Figure 7 .
High Speed Continuous and Sustained Record / Playback
The four 10GbE interfaces in the DTA-9500 enable continuous and sustained recording
of wideband RF signals as shown in Figure 8. The configuration shown is capable of
recording a 3.2 Gbytes/sec on a continuous and sustained basis. Thus, a single channel at
3.2 GSPS sampling rate (with 8-bit data) or two channels at 1.6 GSPS each can be
recorded to disks.
10Gb E
10Gb E
10Gb E
User Laptop / Computer
(GUI / Control API)
10Gb E
Figure 8: Recording of RF signal with full 1.5 GHz bandwidth. The configuration
shown can record at 3.2 Gbytes/sec and offers up to 19.2 TB of storage.
Using the air-cooled chassis, up to four ADC channels at 1.6 GSPS each, or two channels
at 3.2 GSPS each can be recorded for an extended period of time as shown in Figure 9.
The total recording rate for the configuration is 6.4 Gbytes/sec.
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ADC 1
ADC 2
Clock &
Control
2 x Virtex 6 FPGA
10GbE
10GbE
ADC 3
Clock &
Contro l
ADC 4
2 x Virtex 6 FPGA
10GbE
10GbE
10GbE
10GbE
10GbE
10GbE
1 GbE S witch
User Laptop / Computer
(GUI / Cont rol API)
Figure 9: Recording at 6.4 GSPS each with the air-cooled DTA-9500. The total storage
is 38.4 TB
Clocking and Multi-Unit Synchronization
The DTA-9500 is designed to make multi-unit synchronization easy and allow immense
flexibility and scalability. It provides an extremely versatile clock generation mechanism
as well as re-timing feature for control signals to allow for synchronization for high speed
ADCs.
Clock Generation and Distribution
The clock generation and distribution circuit is shown in Figure 10. The DTA-9500
allows the following clocking options for the user:
•
Internally generated sampling clock locked to an internal 100 MHz TCXO serving
as the reference source
•
Internally generated sampling clock locked to an externally provided reference
•
Externally provided sampling clock
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The ADC and the DAC section have separate clock generation and distribution section
and thus may be run at different clock frequencies or locked to different reference
sources. By using the sampling clock in/out feature they can also be operated from the
same sampling clock. Note that the re-timing clock is also created from the same source
and can be at an integral multiple of the ADC sampling clock.
ADC
RC Out 1
RFoutA
REF IN
CLK
SCLK In
LC
Balun
Internal Ref
TCXO
(100 MHz)
RCOut1
RCLK In
RCLK
SCLK Out
Reference In
Fro m
Retiming
Section
SCLK_180deg_Out
The 10MHz Out from the
internal GPS (not shown in this
diagram) can be connected to
the Reference In for achieving a
GPS locked Reference signal.
PLL &
VCO
DCLK_ RST
DCLK (I, Q)
ADC_DCLK
RFoutB
RT_CLK In
LC
Balun
Refe rence Out
RC Out 2
RCOut1
To
FPGA, Ret iming
Retiming Clock
RT_CLK
ADF4350
RT_CLK Out
RT_CLK_ 180deg_Out
Figure 10: Clock Generation and Distribution
Re-timing of Control Signals
For seamless multi-unit synchronization, there is a re-timing circuit in the DTA-9500 that
retimes the control signals using the high speed sampling clock, as shown in Figure 11.
The ADC chip has a feature where the trigger signal can be embedded in the data. In this
mode, only the 11 MSBs are used for sampling the analog signal and the LSB is the
Trigger signal. This mode is also supported with the design as shown in Figure 11. Please
refer to the ADC data sheet (ADC12D1800 from National Semiconductor) for more
details regarding the other signals in the ADC.
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Internal
DCLK RST
DCLK RST
D
Q
D
>
DCLK RST
In
D
>
Q
D
>
FPGA_DC LK_RST In
(To FPGA)
Q
>
RT_C LK
Internal
Trig 1
Q
DCLK RST Out
ADC DC LK RST
(To ADC)
ADC DC LK (Fro m ADC)
TRIG 1
D
Q
D
>
Q
>
TRIG 1 In
D
Q
D
>
RT_C LK
FPGA_TRIG 1 In
(To FPGA)
Q
>
TRIG 1 O ut
ADC DC LK (Fro m ADC)
Figure 11: Retiming DCLK RST and TRIG 1 signals
FPGA_TRIG 2 In
(To FPGA)
Internal TRIG 2
Fro m
FPGA
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
Internal EV ENT 1
Internal EVEN T 2
Internal EVEN T 3
>
TRIG 2 In
EVENT 1 In
EVENT 2 In
RT_C LK
TRIG 2 O ut
EVENT 2 O ut
>
EVEN T 3 O ut
D
Q
D
Q
D
Q
D
Q
FPGA_EVENT 1 In
D
Q
D
Q
FPGA_EVEN T 2 In
D
Q
D
Q
FPGA_EVEN T 2 In
>
EVEN T 3 In
EVENT 1 O ut
To FPGA
>
ADC DC LK (Fro m ADC)
Figure 12: Retiming of other control signals
The clock generation and distribution design makes multi-unit synchronization extremely
easy. For multi-unit synchronization, the sample clock, trigger, etc. are generated in the
Master unit and distributed to all units (slave as well as the master unit) by using an
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external splitter (see Figure 13). The clock delay feature in the ADC can be used to
correct any imbalance. All control signals are re-timed using the same fast sampling clock
to ensure synchronization in all units.
DTA-9500: Master
Ref In
DTA-9500 : S lave
Ref Out
SCLK In
SCLK Out
RT_CLK
In
RT_CLK
Out
Ref In
1:2 RF
Splitter
Ref Out
SCLK In
SCLK Out
RT_CLK
In
RT_CLK
Out
RCLK In
RC Out1
DCLK_
RST In
TRIG 1
In
DCLK_
RST
Out
TRIG 1
Out
TRIG 1
In
DCLK_
RST
Out
TRIG 1
Out
TRIG 2
In
TRIG 2
Out
TRIG 2
In
TRIG 2
Out
1:2 RF
Splitter
RCLK In
DCLK_
RST In
RC Out1
Same S ignal
(Created Internally)
Figure 13: Multi-Unit Synchronization
DTA-9500 Configurations
Table 1: DTA-9500 Configurations
Number
Description
DTA-9500S-1RT-4FG
Tranceive system in a conduction cooled chassis with 1-ch ADC
at 3.6 GSPS (or 2-ch ADC at 1.8 GSPS each), 1-ch DAC at 4
GSPS, four 10 GbE interfaces and a GPS receive module.
DTA-9500S-1R-2F
Receive only system in a conduction cooled chassis with 1-ch
ADC at 3.6 GSPS (or 2-ch ADC at 1.8 GSPS each) and two (2)
10 GbE interfaces.
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Number
Description
DTA-9500S-1R-4F
Receive only system in a conduction cooled chassis with 1-ch
ADC at 3.6 GSPS (or 2-ch ADC at 1.8 GSPS each) and four (4)
10 GbE interfaces.
DTA-9500-AC-2R-8F
Receive only system in an air-cooled chassis with 2-ch ADC at
3.6 GSPS (or 4-ch ADC at 1.8 GSPS each) and eight (8) 10 GbE
interfaces.
DTA-9500-AC-1R-4F
Receive only system in an air-cooled chassis with 1-ch ADC at
3.6 GSPS (or 2-ch ADC at 1.8 GSPS each) and four (4) 10 GbE
interfaces.
Performance
ADC performance is shown in Figure 14, Figure 15, and Figure 16.
Figure 14: ADC Performance at Fs at 1.0 GSPS with input signal at 140 MHz
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Figure 15: ADC Performance at Fs at 640 MHz with input signal at 140 MHz
Figure 16: ADC Performance at Fs at 1.6 GSPS with input signal at 140 MHz
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FPGA Applications
D-TA has extensive FPGA design capability including having standard cores like FFT,
DDC etc. D-TA can also offer customized FPGA design services to implement user
specific application in the FPGAs. Please contact factory for details.
Customization
DTA-9500 can be easily customized to meet specific user requirements. Please contact
factory to discuss your specific requirement. Typical customization can include:
•
Custom FPGA application coding
•
Different packaging options
D-TA Systems also provides custom development capability to meet specific user
requirements. D-TA Systems offers technical leadership in all aspects of sensor
processing and sensor interfacing solutions – RF design, mixed signal and FPGA design,
10GbE design, real time multi-threaded and multi-core software design, etc.
Programming Interface and API support
The DTA-9500 can be programmed over a 1GbE interface (optical). The software
development kit contains extensive API functions that allow the user to control the unit.
The SDK also allows the user to very easily integrate the control functionality of the
DTA-9500 into user applications.
The SDK also includes the Data SDK that can be used for development of multithreaded, multi-core applications running on standard servers using the 10GbE interfaces
for data transfer. The SDK shields the users from mundane data management issues and
allows users to concentrate on developing their own applications. Please refer to TN-14
for more details.
Training
We also offer hand-on interactive training either in our fully equipped Training Center or
in your facility. The Training Center boasts of a fully equipped conference room and a
dedicated Training Laboratory with access to D-TA products as well as test equipment
like Oscilloscopes, Spectrum Analyzers, Network Analyzers, Signal Generators, etc. The
hand-on training cover a full discussion of the SDK structure, detailed product
discussions and actual demo application development with actual equipment. The user
would be able to create processing applications and determine optimal speed and
performance. The specific applications are tailored to meet the user's exact requirement.
We also offer custom application development to meet the users' exact requirement.
Please contact us for more information.
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Conclusion
The DTA-9500 is an ideal wideband SDR platform for a variety of applications. Together
with the high speed and sustained record / playback option the DTA-9500 provides
unprecedented wideband capability unmatched in the industry. DTA-9500 is the only
solution available that allows transfer of the entire bandwidth in a continuous and
sustained fashion. The 10GbE back-end allow the fastest data transfer capability and
enables real time recording and monitoring of the entire bandwidth on a continuous and
sustained basis.
Contact Information
US
INTERNATIONAL
Toll Free: 1-877 382-3222
+1 (613) 745-8713
www.d-ta.com
Sales: sales@d-ta.com
Support: support@d-ta.com
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