Project design steps
Strona 1 z 2
Project design steps
Draw the schematic diagram of your amplifier, write components' names, mark node numbers.
Select operating point.
Calculate plots requested in task 1. For IC=f(VBE) use selected VCE value. Make hardcopy of
them.
With PSPICE calculate small signal hybrid-PI model parameters for selected operating point
VCEQ, ICQ, VBEQ.
Perform manual calculations of the voltage gain Gv, effective voltage gain Gveff, current gain
Gi, input and output impedances Zin, Zout (rin, rout for midfrequencies).
Calculate C1, C2, CE for requested fL.
1. Select VEQ, VCEQ, ICQ for design
VEQ = .25*VCC, VCEQ = VRCQ = .5*(VCC - VEQ), ICQ
= (1mA ... 3mA)
It should assure reasonable compromise for the best
temperature behavior,
maximum voltage gain (largest RC) and maximum output
amplitude (adequate VCE). Example:
VCC = 26V, then VEQ = 6V, VCEQ = 10V, ICQ = 1.5mA
(See note above.)
2. Task 1. What to do.
AREA = as given in project data. AREA is declared in
PSPICE statement just after the transistor type declaration example: Q1 2 3 4 Q2N3904 .97
Find characteristics IC, IB = f(VBE) for large change of these currents.
'Large' means 'not far above Imax' for given transistor, in case of 2N3904 ICmax = 200mA, so Imax
= AREA*ICmax.
Reasonable VBE range (for the task 1)seems to be (0.5V ... .9V)
Temperatures according to project data, eg. Tmin = 14, Tnom = 27, Tmax = 88 (for this example).
3. Repeat calculation IC = f(VBE) for single TEMP = 27 (default). Find VBEQ for your selected
value of ICQ = 1.5mA (see above). It may need to narrow the scanned VBE range. Having found
VBEQ for selected ICQ fix it, then perform (using .OP)operating point calculations for ICQ, VCEQ,
watch VBEQ, IBQ. Check small signal hybrid-PI parameters (among them h21E ( BETADC), h21e
(BETAAC), gm (GM), rbe (RPI), Cbe (CJE), Cjc (CJC), h22e (1/RO)).
Print results of above calculations and corresponding PSPICE input files and include them in
your project report.
4. Calculate collector, emitter and base biasing resistors.
RC = VRCQ/ICQ,
RE = VEQ/ICQ,
RB1 = (VCC-(VEQ+VBEQ))/(11*IBQ),
RB2 = (VEQ+VBEQ)/(10*IBQ) -- assuming base divider current as 10*IBQ.
Select values from E12(10%) series nearest to calculated ones.
Now you may check the operation point for the transistor using PSPICE with selected (standard)
resistors.
Print results of above calculation(s) and corresponding PSPICE input file(s) and include them
in your project report.
Make a table and fill it with obtained values of RB1, RB2, RC, RE, VBEQ, ICQ, VCEQ, BETADC,
BETAAC, GM, RPI, RO. Write components' values to your schematic diagram.
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Project design steps
Strona 2 z 2
5. Begin manual calculations.
Calculate voltage gain Gv (ku), current
gain Gi (ki), and input and output
resistances using hybrid PI model
parameters generated by PSPICE.
Auxiliary calculations
rbe = 1/gbe = RPI,
RB = RB1||RB2,
rin = RPI||RB,
RLt = 1/h22||RC||RL = RO||RC||RL; note: 1/h22 = RO from generated hybrid PI model table.
Gi = I2/I1 = BETAAC*RB/(RB + RPI)*RLt/RL
Gv = Vout/Vb = gm*RLt = Gi*ZL/Zin = Gi*RL/rin (where ZL = RL, Zin=rin for midfrequency)
Gveff = Vout/Vin = Gv*rin1/(RS + rin1) = gm*RLt*rin1/(RS + rin1); gm = GM (from generated
hybrid-PI model table)
Input impedance: Zin = rin = RB||RPI,
Output impedance: ZO = RO||RC
6. Calculate CE, C1, C2
CE: approx. value from time constant re*CE, where re = (RS||RB +
RPI)/BETAAC,
CE = 1/(2*PI*fL*re), watch E12
C1 = 10*C1', watch E12, C1' = 1/(2*PI*fL*rsin), rsin = RS + rin,
C2 = 10*C2', watch E12, C2' = 1/(2*PI*fL*rso), rso = RC||RO + RL
Write CE, C1, C2 values to your schematic diagram.
7. Realisation of the upper cut-off frequency fH.
Check fH using PSPICE. If fH is greather than required, an additional
capactance CMO is needed between collector and base. Calculations:
CMO = (Cb' - Gv*CBC - CBE)/Gv, Cb' = 1/(2*PI*fH*rin'), Gv = gm*RLt, rin' = RS||RB|RPI
8. Calculate operating point change for TEMP=tj2
Find base bias equivalent circuit - VBeq, RBeq (see schematic diagram)):
VBeq = VCC*RB2/(RB1+RB2), RBeq = RB
dVBE(T) = -2.2mV/degree, dBETADC(T) = 1%/degree
calculate new VBE' and BETADC' for TEMP=tj2,
VBE' = VBE-(2.2mV*(tj2-tj1)) BETADC' = BETADC*(100+(tj2-tj1))/100, then find new ICQ' =
(VBeq - VBE')/(RE + RB/BETADC'),
Find new dynamic parameters at tj2:
new value of RPI' = VT/ICQ'*BETADC', new effective voltage gain of the amplifier
gm' = BETADC'/(BETADC'+1)* ICQ'/VT;
rin' = RPI'||RB
Gi' = I2/I1 = BETAAC'*RB/(RB + RPI')*RLt/RL; assume that change in BETAAC is same as in
BETADC
ZL = RL,
Zin'=rin' (for midfrequency)
Gv' = Vout/Vb = gm'*RLt = Gi'*ZL/Zin' = Gi'*RL/rin' (where ZL = RL, Zin'=rin' for midfrequency)
Gveff' = gm'*RLt*rin'/(RS + rin1')
9. Check operating point of the transistor and calculations in sec. 5 - 8 using PSPICE. Check the
maximum output amplitude using TRAN analysis (Fourier for THD, assume max. 2% THD)
Full documentation of simulation is needed - schematics with node numbers, input files' listings,
operational points data, etc. See PRONEEDS for more. This file in pdf format is here.
You may download Pspice8 (version used in Electronics Lab.) here
© Michal Ramotowski 2003
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