EE 536a
USC Viterbi School of Engineering
J. Choma
U niversity of S outhern C alifornia
USC Viterbi School of Engineering
Ming Hsieh Department of Electrical Engineering
EE 536a:
Double Homework Assignment #01-02
Due: 09/04/2013
Fall, 2013
Choma
Reading Assignment:
Chapter 1, assigned textbook.
Chapter 2, assigned textbook.
Lecture Supplement #3; www.jcatsc.com/EE 536a
Problem #01:
In the current amplifier of Figure (P1), the input signal is the signal component, Is, of
the net input current, IQ + Is, while the output response to the signal input is taken as the signal
component, ILs, of the indicated net current, ILQ + ILs. Of course, ILQ and IQ are quiescent biasing
currents. Transistors M1 and M2 are identical, save for the fact that the gate aspect ratio of transistor M1 is k-times smaller than the gate aspect ratios of transistors M2 and M3. All transistors
are biased in saturation, have infinitely large channel resistances, negligible carrier mobility degradation and negligibly small bulk-induced threshold modulation. In a word, the transistors are
presumed to abide by the simple, square law, Schichman-Hodges model.
Vdd
R
RL
C
Rin
ILQ + ILs
M3
I Q + Is
M1
M2
Figure (P1)
(a). Under quiescent operating conditions, express in terms of the aspect ratio parameter, k, the
relationship among the device transconductances, gm1, gm2, and gm3.
(b). Draw the low frequency, small signal equivalent circuit of the network. Make use of the
fact that transistor M2 is configured as a diode-connected device.
(c). Derive an expression for the small signal, low frequency input resistance, Rin. Express
your result in terms of appropriate circuit parameters and device transconductances.
(d). Derive an expression for the low frequency, small signal current gain, Ai = ILs /Is. Simplify
your result for the case of very large R and express the result in terms of parameter k.
Homework #01
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Fall Semester, 2013
EE 536a
USC Viterbi School of Engineering
J. Choma
(e). Derive an expression for the 3-dB bandwidth, B, of this current gain. Assume that all
capacitances implicit to the three transistors are negligibly small.
(f). If the resistances, R and RL, satisfy the constraint, R > kRL, briefly discuss any problems
encountered with respect to assuring the saturation domain operation of transistor M3.
Problem #02:
The circuit given in Figure (P2) is capable of realizing a negative resistance between
terminals (1) and (2). Derive an expression for this negative resistance, assuming ideal transconductors.
(1)
(2)
Gm



G
 m
Figure (P2)
Problem #03:
In the amplifier of Figure (P3), a capacitance, Ca, is appended in shunt with resistance Ra. Assume that the parameters in this circuit satisfy the inequalities,
R
R
a .
1
g R 
; 1  g r 
m a
m
i
R R
R R
1
2
1
V1
I1
I2

Is
2
Rs
Va
V2

ri
gmV a
Ra

Ca V b
ri
gmVb
Rl

R2
R1
Figure (P3)
(a). Derive an expression for the time constant, say a, associated with capacitance Ca and use
this time constant relationship to deduce the 3-dB bandwidth of the network.
(b). Give engineering design arguments that support an increase in the closed loop bandwidth.
Homework #01
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Fall Semester, 2013
EE 536a
USC Viterbi School of Engineering
J. Choma
(c). What major disadvantage surfaces if attempts are made to set the 3-dB bandwidth by
connecting capacitance Ca directly across the input port of the amplifier, as opposed to the
indicated shunt incidence with resistance Ra?
(d). The driving point closed loop output resistance of the feedback amplifier is infinitely large.
This attribute allows the amplifier to deliver a prescribed I/O current gain for broad ranges
of load resistance. In light of this observation, is there an engineering disadvantage to setting the bandwidth by placing capacitance Ca in shunt with the load termination, Rl?
Problem #04:
For the two RC networks appearing in Figure (P4), use the appropriate two-port parameters to evaluate the frequencies associated with the pole and zero of the forward transadmittance function.
V1
I1
R
C
I2
V2
V1
I1
R
R
I2
V2
C
(a).
(b).
Figure (P4)
Problem #05:
Under commonly encountered operating conditions, Figure (P5) is a valid linearized
equivalent circuit of a voltage buffer realized in MOSFET device technology. The input signal
source is represented by its Thévenin equivalent circuit, which consists of voltage source Vs and
resistance Rs. The response to this input signal is the indicated voltage, Vo, which is developed
across the shunt interconnection of load resistance Rl and load capacitance Cl. The actual MOS
transistor is typified by the two voltage controlled current sources, gmVi and λbgmVb, where gm
(typically of the order of hundreds of micromhos to a few millimhos) is the forward transconductance of the transistor, and λb (a dimensionless number generally smaller than 0.2) emulates
the impact exerted by the substrate on device forward transfer characteristics. Note that regardless of the nature of the transistor parameters, the model in Figure (P5) is a linear active circuit.
(a). Determine, and express as a function of Vs, the Thévenin equivalent voltage, say Vot, which
drives the load capacitor, Cl. Simplify the expression for Vot for the special case of an infinitely large load resistance, Rl. If Rl were to be omitted from the diagram in Figure (P5),
would the resultant expression for Vot be identical to the originally derived expression?
(b). What is the low frequency value of the voltage gain, Vo/Vs, of the circuit and how does this
gain relate to the ratio, Vot/Vs?
(c). Derive an expression for the Thévenin equivalent resistance, Rout, facing capacitance Cl.
(d). Derive an expression for the low frequency input resistance, Rin, “seen” by the signal
source.
(e). What is the significance of the time constant, RoutCl, to the frequency domain transfer function, H(jω) = Vo(jω)/Vs(jω)? Give an expression for this transfer relationship in terms of
Vot/Vs and the subject time constant.
Homework #01
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Fall Semester, 2013
EE 536a
USC Viterbi School of Engineering
J. Choma
gmVi
bgmVb
Rs
Vi

Vb
 Rl

Vs

Vo
Cl
Rin
Rout
Figure (P5)
(f). Give a simple expression for the 3–dB bandwidth of the circuit.
(g). Is there anything interesting about the gain bandwidth product, which is cleverly defined
as the product of the magnitude of zero frequency gain and 3–dB bandwidth?
(h). Take Rs = 300 Ω, Rl = 1,000 Ω, gm = 5 mmho, λb = 0.08, and Cl = 8 pF. Calculate the low
frequency voltage gain, the output resistance, the time constant of the circuit, and the 3-dB
bandwidth of the circuit.
Problem #06:
Under commonly encountered operating conditions, Figure (P6) is a valid linearized
equivalent circuit of a voltage amplifier realized in bipolar junction transistor (BJT) device technology. The input signal source is represented by its Thévenin equivalent circuit, which consists
of voltage source Vs and resistance Rs. The output, or response, to this input signal is the indicated voltage, Vo, which is developed across the shunt interconnection of load resistance Rl and
load capacitance Cl. The actual BJT is modeled by the current controlled current source, βI, and
the two resistances, rb and rπ. Typically, β is of the order of 100 amps/amp, rb can be as large as
200 Ω, and rπ is of the order of a few thousand ohms. The resistance, Re, is a circuit element
used for biasing and linearization purposes. It is generally chosen to be of the order of fifty to a
few hundred ohms.
(a). Determine, and express as a function of Vs, the Thévenin equivalent voltage, say Vot, that
drives the load capacitor, Cl. Simplify the expression for Vot for the special case of a very
large current gain parameter, β.
(b). What is the low frequency value of the voltage gain, Vo/Vs, of the circuit and how does this
gain relate to the ratio, Vot /Vs?
(c). Derive an expression for the Thévenin equivalent resistance, Rout, facing capacitance Cl.
(d). Derive an expression for the low frequency input resistance, Rin, “seen” by the signal
source.
(e). Derive an expression for the net effective resistance, say Rte, established across the terminals where resistance Re is connected.
(f). What is the significance of the time constant, RoutCl, to the frequency domain transfer function, H(jω) = Vo(jω)/Vs(jω)? Give an expression for this transfer relationship in terms of
Vot/Vs and the subject time constant.
(g). Give a simple expression for the 3–dB bandwidth of the circuit.
(h). Take Rs = 300 Ω, Rl = 1,000 Ω, β = 120mamps/amp, rb = 190 Ω, rπ = 1.5 KΩ, Re = 100 Ω,
and Cl = 8 pF. Calculate the low frequency voltage gain, the output resistance, the time
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Fall Semester, 2013
EE 536a
USC Viterbi School of Engineering
J. Choma
constant attributed to capacitance Cl the circuit, the circuit 3-dB bandwidth, and the indicated resistance parameter, Rte.
Rout
Rs
rb
Vo

r
Vs
Rin

I
Rl
Cl
I
Rte
Re
Figure (P6)
Problem #07:
The circuit in Figure (P7) is a model of a commonly utilized amplifier that is compensated to ensure stable performance at high signal frequencies.
C
Vo
Rs

Vs

V

Ri
gmV
Rl

Figure (P7)
(a). Derive a generalized expression for the low frequency voltage gain, Av(0)  Avo = Vo /Vs.
(b). Derive an expression for the time constant, τc, attributed to the pole incurred by the indicated capacitance, C.
(c). If the transconductance parameter, gm, can be adjusted electronically, what is the maximum attainable gain-bandwidth product of the circuit?
(d). Derive an expression for the driving point input impedance seen by the signal source comprised of Thévenin voltage Vs and Thévenin resistance, Rs.
(e). Derive an expression for the driving point output impedance seen by load resistance, Rl.
Problem #08:
The circuit in Figure (P8a) is an equivalent circuit for a transconductance amplifier
whose output port is terminated in a shunt interconnection of a load resistance, RL, and a load
capacitance, CL. This equivalent circuit is to be reduced to the Norton architecture shown in
Figure (P8b), where the Norton transadmittance, Yn(s), is understood to be a function of freHomework #01
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Fall Semester, 2013
EE 536a
USC Viterbi School of Engineering
quency and pertinent circuit parameters.
Vo
V
Rss
Css
RL
CL
Yn(s)Vs

(a).
Zth (s)
Vs
Vo
gmV
Rs

J. Choma
RL
CL
(b).
Figure (P8)
(a). Derive an expression for the Norton transadmittance function, Yn(s).
(b). Derive an expression for the indicated Thévenin impedance, Zth(s).
(c). The capacitance, Css, creates both a left half plane pole and a left half plane zero in the voltage transfer function, Vo/Vs. If the time constant associated with the left half plane zero
established by Css is selected to cancel, the time constant, RLCL, of the shunt load, give an
expression for the resultant 3-dB bandwidth of the circuit.
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Fall Semester, 2013