A 0.9V, 0.5pA Rail-to-Rail CMOS Operational Amplifier
Troy Stockstad’, Hirokazu Yoshizawa*
‘Gain Technology, Phoenix, AZ
’Seiko Instruments Inc., Chiba, Japan
Abstract
A 0.9V, OSpA, rail-to-rail CMOS operational amplifier
designed with weak inversion techniques is presented.
Depletion-mode NMOS transistors buffer a bulk-driven
PMOS differential pair to realize wide input dynamic range,
while the output stage architecture provides symmetric railto-rail output drive through the use of a low voltage
translinear control circuit.
Introduction
Reducing power consumption in portable applications has
made lower supply voltages increasingly common, migrating
down to 0.9V for a single battery cell. Operational amplifiers
used in these conditions require circuit architectures which
maximize dynamic range while still performing with the
reduced supply voltage headroom. Additionally, the supply
current of the amplifier should be minimized to improve the
battery life of the product. This operational amplifier
achieves a common-mode input voltage range which includes
the supply rails and an output dynamic range within lOmV of
the supplies with a 100kQ load, while drawing a bias current
of 0.SpA from a 0.9V supply. The amplifier, designed with
weak inversion techniques, utilizes an input stage with a
combination of depletion-mode N-channel transistors and a
bulk-driven P-channel differential pair to achieve wide
common-mode input voltage range. The output stage includes
a low-voltage, class AB rail-to-rail architecture with
symmetrical output drive capabilities. The amplifier is
designed in a 2.5pm Nwell CMOS process.
“dead zone” in the amplifier’s common-mode input range.
The complementary input architecture also suffers from
reduced common-mode rejection as the input control of the
amplifier is switched from the P-channel to the N-channel
differential pairs. Another technique utilizes a bulk-driven
differential pair for the input stage (3). This architecture,
however, suffers from increased input capacitance and
increased input bias currents at low common-mode input
voltages as the source-bulk junction becomes forward biased.
A third rail-to-rail input stage technique utilizes an N-channel
depletion-mode differential pair (43, which relies upon
modulating the source-bulk bias voltage as a function of the
input common-mode voltage. This dynamically increases the
threshold voltage of the depletion input differential pair to
maintain the operation of the transistors in saturation.
However, the use of the N-channel depletion-mode
differential pair places constraints upon the intrinsic threshold
voltage and the bulk doping concentration in the N-channel
depletion-mode transistors when operating with a 0.9V
voltage supply, which may conflict with the designer’s
standard process flow.
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Circuit Architectures
A. Input Stage
Perhaps the most difficult circuit design challenge for the low
voltage amplifier is the design of an input stage with a rail-torail common-mode voltage range. Much work has been
reported on input stages with complementary differential
pairs and associated circuit networks used to maintain
constant transconductance over the input voltage range (1,2).
At low supply voltages, the sum of the common-mode ranges
of the N-channel and P-channel differential pairs may
become larger than the available supply voltage. This
common-mode range overlap at low supply voltages creates a
Fig. 1. Amplifier Input Stage.
The input stage architecture used in this amplifier is shown in
Fig. 1. An enhancement, bulk-driven differential pair of Pchannel transistors, MP1 and MP2, is used to generate
transconductance. However, instead of driving the bulks
directly from the inputs, depletion-mode N-channel
transistors MN1 and MN2 are used as source followers to
buffer the inputs from the P-channel bulk terminals. MN1
and MN2 also provide a common-mode dependent levelshifting function to the bulk terminals, which minimizes
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0-7803-6591-7/0l/$10.00
0 2001 IEEE
IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE
467
excess bulk currents when the input common-mode voltages
are near VEEpotentials. The modulated drain currents of MP1
and MP2 are folded into the current summing nodes of the
cascode circuit at the sources of MN3 and MN4, with current
mirror MP3 and MP4 performing a differential-to-singleended conversion to the high impedance output node Vol.
The use of the depletion-mode source followers MN1 and
MN2, in conjunction with the bulk-driven P-channel
differential pair MP1 and MP2, allows additional design
flexibility to meet the rail-to-rail input requirements of the
amplifier. The input depletion-mode source followers may
be designed to level-shift the input signal to MP1 and MF'2
without a large impact on the overall transconductance of the
input stage, which is mainly determined by MP1 and MP2
and their bias current. This allows the input circuit
architecture to be used over a greater range of threshold
voltages and background concentrations for the depletionmode transistors.
The design methodology for input source followers MNI and
MN2 is shown below. The drain current in a MOS transistor
operating in weak inversion is given by (6)
MN7. Replica transistor MP6 provides a current proportional
to the current in MP5 to current mirror MN9 and MN10. The
output P-channel replica current is then introduced to the
control loop, which drives the gate of MN8. Resistors R1
and R2 provide sufficient voltage for current sources I7 and
MNlO to operate in saturation. Assuming weak inversion
operation in the transistors, the current in MN8 is given by
(4)
where I is the unit current of 20nA. Current sources I5 and I7
each draw a unit current I, while current source I6 is set to
2*I. The inverse relationship between Img and Ihlp~igives the
desired push-pull functionality required for the output stage.
Additionally, the control circuit may drive the gate of MN8
nearly to VCC,since current I6 is larger than 17. This allows
output transistors MP5 and MN8 to supply large symmetrical
output currents when the amplifier is overdriven to either
supply. Capacitor Cc sets the unity gain bandwidth of the
amplifier, and capacitor CM provides local Miller
compensation for the output stage.
where n is the subthreshold slope factor, V, is the thermal
voltage, and IDo is the characteristic current of the device.
Solving (2) for VGs gives
-"SE
v,, = izvt ( l n ( e 7 - e
- v ~ ~
T >+ In(%)>,
(2)
'Do,
which can be further'simplified (assuming VDB>> Vse,
which does not hold when VCM= VCC)to
V,, = nVsB+ C.
(3)
Therefore, VGS increases as a function of VsB and the
subthreshold slope factor n. As Vse increases to the positive
supply voltage VCc, the influence of the VDBterm becomes
significant, and VGSincreases at a higher rate. Given a circuit
designer may have no cqntrol over the subthreshold slope
factor, the constant C can be adjusted to give a desired VGS
value when VsB = 0 (VCM = 0) to meet biasing requirements,
such as for current source 1, in Fig. 1.
E. Output Stage
The output stage of the amplifier is shown in Fig. 2. The
output P-channel transistor MP5 is driven directly from the
high impedance node of the amplifier at node Vo, to attain
minimal phase loss through the slower P-channel signal path.
The N-channel output transistor MN8 is controlled through a
translinear loop, which includes transistors MN5, MN6, and
468
Fig. 2. Amplifier Output Stage.
C. Ampli$er Schematic
Fig. 3 shows a schematic of the entire amplifier including
biasing. The amplifier utilizes a poly fuse trimming
technique to adjust the input offset voltage and overall bias
current of the amplifier. The input offset voltage of the
amplifier is adjusted by trimming the bias current to the input
N-channel depletion-mode followers MN1 and MN2. The
bias circuit uses a positive feedback delta V G circuit
~
which
incorporates two trimmed linear depletion-mode N-channel
transistors to control the magnitude of the bias current. The
linear depletion-mode N-channel devices compensate the
temperature coefficient (TC) of the delta VGS voltage to
21-6-2
Fig. 3. Schematic of Entire 0.9V Rail-to-Rail Amplifier.
generate a low TC, supply independent bias current. A
startup circuit is used to compare the bias current to a
depletion NMOS current source to ensure the biasing
operates properly.
Experimental Results
Input Voltage Range
Output Voltage Swing
VEE < VIN < VCC
+O. 89V/+O.O1
NMOS followers at worst case process and temperature
corners. CMRR improves to over 50dB worst case with a
supply voltage of 3V, since a larger change in common-mode
voltage causes a larger threshold voltage change in the
depletion-mode NMOS input transistors as the commonmode voltage nears VCC. The amplifier is capable of a large
output drive current of over 30pA compared to its quiescent
current, due to the drive capability of the class AB output
stage.
TeK Run: 2.50kWs
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31pA min./88pA max.
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Vin = lOmV, Vout =
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(V, = 0.45V, Z L =
Table 1: Performance Summary, VCC= 0.9V, VE = OV, T=
25C.
The amplifier's characteristics are summarized in Table 1 for
a 0.9V supply. The amplifier is rated to operate on a supply
voltage of up to 6V. Common-mode rejection ratio (CMRR)
suffers at the lowest supply voltage of 0.9V due to
insufficient threshold voltage shift in the depletion-mode
Fig, 4. Amplifier Input and Output Rail-to-Rail Waveforms
at 0.9V supply.
Fig. 4 shows the input and output waveforms of the amplifier
in a unity-gain buffer configuration with a single 0.9V
supply. An input signal of greater than 1.1V is applied to
illustrate the rail-to-rail capabilities of the input and output
circuits of the amplifier. An input frequency of lOHz is used
to maintain sufficient loop gain during the measurement.
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469
Acknowledgements
The authors would like to acknowledge Kimio Shibata for
product definition, Monty Palmer for his expertise in mask
design, and Chris Fishbach and Mike Nunnery for their
characterization effort.
References
Fig. 5. Die Photograph.
Fig. 5 shows a die photograph of the amplifier. The amplifier
has a die area of approximately 0.5 mm2 in a 2.5pm Nwell
CMOS process.
Conclusions
A 0.9V, O S @ rail-to-rail CMOS operational amplifier has
been presented. A new low-voltage input stage has been
described which utilizes the body effect to modulate the
threshold voltage of depletion-mode N-channel input voltage
followers, which level-shift the input voltage to a bulk-driven
P-channel differential pair. A new output stage circuit has
also been described which provides high output current drive
capability at low supply voltages, while maintaining good
stability and symmetry. The amplifier has a DC gain of 70dB
with a 1MS2 load, and drives over 30pA from a 0.9V supply.
470
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